int acpi_pci_bind(struct acpi_device *device) { int result = 0; acpi_status status; struct acpi_pci_data *data; struct acpi_pci_data *pdata; struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; acpi_handle handle; if (!device || !device->parent) return -EINVAL; data = kzalloc(sizeof(struct acpi_pci_data), GFP_KERNEL); if (!data) return -ENOMEM; status = acpi_get_name(device->handle, ACPI_FULL_PATHNAME, &buffer); if (ACPI_FAILURE(status)) { kfree(data); return -ENODEV; } ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Binding PCI device [%s]...\n", (char *)buffer.pointer)); /* * Segment & Bus * ------------- * These are obtained via the parent device's ACPI-PCI context. */ status = acpi_get_data(device->parent->handle, acpi_pci_data_handler, (void **)&pdata); if (ACPI_FAILURE(status) || !pdata || !pdata->bus) { ACPI_EXCEPTION((AE_INFO, status, "Invalid ACPI-PCI context for parent device %s", acpi_device_bid(device->parent))); result = -ENODEV; goto end; } data->id.segment = pdata->id.segment; data->id.bus = pdata->bus->number; /* * Device & Function * ----------------- * These are simply obtained from the device's _ADR method. Note * that a value of zero is valid. */ data->id.device = device->pnp.bus_address >> 16; data->id.function = device->pnp.bus_address & 0xFFFF; ACPI_DEBUG_PRINT((ACPI_DB_INFO, "...to %04x:%02x:%02x.%d\n", data->id.segment, data->id.bus, data->id.device, data->id.function)); /* * TBD: Support slot devices (e.g. function=0xFFFF). */ /* * Locate PCI Device * ----------------- * Locate matching device in PCI namespace. If it doesn't exist * this typically means that the device isn't currently inserted * (e.g. docking station, port replicator, etc.). */ data->dev = pci_get_slot(pdata->bus, PCI_DEVFN(data->id.device, data->id.function)); if (!data->dev) { ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Device %04x:%02x:%02x.%d not present in PCI namespace\n", data->id.segment, data->id.bus, data->id.device, data->id.function)); result = -ENODEV; goto end; } if (!data->dev->bus) { printk(KERN_ERR PREFIX "Device %04x:%02x:%02x.%d has invalid 'bus' field\n", data->id.segment, data->id.bus, data->id.device, data->id.function); result = -ENODEV; goto end; } /* * PCI Bridge? * ----------- * If so, set the 'bus' field and install the 'bind' function to * facilitate callbacks for all of its children. */ if (data->dev->subordinate) { ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Device %04x:%02x:%02x.%d is a PCI bridge\n", data->id.segment, data->id.bus, data->id.device, data->id.function)); data->bus = data->dev->subordinate; device->ops.bind = acpi_pci_bind; device->ops.unbind = acpi_pci_unbind; } /* * Attach ACPI-PCI Context * ----------------------- * Thus binding the ACPI and PCI devices. */ status = acpi_attach_data(device->handle, acpi_pci_data_handler, data); if (ACPI_FAILURE(status)) { ACPI_EXCEPTION((AE_INFO, status, "Unable to attach ACPI-PCI context to device %s", acpi_device_bid(device))); result = -ENODEV; goto end; } /* * PCI Routing Table * ----------------- * Evaluate and parse _PRT, if exists. This code is independent of * PCI bridges (above) to allow parsing of _PRT objects within the * scope of non-bridge devices. Note that _PRTs within the scope of * a PCI bridge assume the bridge's subordinate bus number. * * TBD: Can _PRTs exist within the scope of non-bridge PCI devices? */ status = acpi_get_handle(device->handle, METHOD_NAME__PRT, &handle); if (ACPI_SUCCESS(status)) { if (data->bus) /* PCI-PCI bridge */ acpi_pci_irq_add_prt(device->handle, data->id.segment, data->bus->number); else /* non-bridge PCI device */ acpi_pci_irq_add_prt(device->handle, data->id.segment, data->id.bus); } end: kfree(buffer.pointer); if (result) { pci_dev_put(data->dev); kfree(data); } return result; }
static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; static const char productid[12] = "P4DPE "; struct mp_config_table *mc; int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { device_t dev; struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 3, 0x20, res->base); } } dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 4, 0x20, res->base); } } dev = dev_find_slot(4, PCI_DEVFN(0x1e,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 5, 0x20, res->base); } } dev = dev_find_slot(4, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 8, 0x20, res->base); } } } mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x42, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x46, 0x2, 0x16); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x48, 0x2, 0x17); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3d, 0x2, 0x14); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
/* PC hardware initialisation */ static void pc_q35_init(QEMUMachineInitArgs *args) { ram_addr_t below_4g_mem_size, above_4g_mem_size; Q35PCIHost *q35_host; PCIHostState *phb; PCIBus *host_bus; PCIDevice *lpc; BusState *idebus[MAX_SATA_PORTS]; ISADevice *rtc_state; ISADevice *floppy; MemoryRegion *pci_memory; MemoryRegion *rom_memory; MemoryRegion *ram_memory; GSIState *gsi_state; ISABus *isa_bus; int pci_enabled = 1; qemu_irq *cpu_irq; qemu_irq *gsi; qemu_irq *i8259; int i; ICH9LPCState *ich9_lpc; PCIDevice *ahci; DeviceState *icc_bridge; PcGuestInfo *guest_info; ram_addr_t lowmem; /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping * also known as MMCFG). * If it doesn't, we need to split it in chunks below and above 4G. * In any case, try to make sure that guest addresses aligned at * 1G boundaries get mapped to host addresses aligned at 1G boundaries. * For old machine types, use whatever split we used historically to avoid * breaking migration. */ if (args->ram_size >= 0xb0000000) { lowmem = gigabyte_align ? 0x80000000 : 0xb0000000; } else { lowmem = 0xb0000000; } /* Handle the machine opt max-ram-below-4g. It is basicly doing * min(qemu limit, user limit). */ if (lowmem > max_ram_below_4g) { lowmem = max_ram_below_4g; if (args->ram_size - lowmem > lowmem && lowmem & ((1ULL << 30) - 1)) { error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64 ") not a multiple of 1G; possible bad performance.", max_ram_below_4g); } } if (args->ram_size >= lowmem) { above_4g_mem_size = args->ram_size - lowmem; below_4g_mem_size = lowmem; } else { above_4g_mem_size = 0; below_4g_mem_size = args->ram_size; } if (xen_enabled() && xen_hvm_init(&below_4g_mem_size, &above_4g_mem_size, &ram_memory) != 0) { fprintf(stderr, "xen hardware virtual machine initialisation failed\n"); exit(1); } icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); object_property_add_child(qdev_get_machine(), "icc-bridge", OBJECT(icc_bridge), NULL); pc_cpus_init(args->cpu_model, icc_bridge); pc_acpi_init("q35-acpi-dsdt.aml"); kvmclock_create(); /* pci enabled */ if (pci_enabled) { pci_memory = g_new(MemoryRegion, 1); memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); rom_memory = pci_memory; } else { pci_memory = NULL; rom_memory = get_system_memory(); } guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); guest_info->has_pci_info = has_pci_info; guest_info->isapc_ram_fw = false; guest_info->has_acpi_build = has_acpi_build; if (smbios_defaults) { /* These values are guest ABI, do not change */ smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", args->machine->name); } /* allocate ram and load rom/bios */ if (!xen_enabled()) { pc_memory_init(get_system_memory(), args->kernel_filename, args->kernel_cmdline, args->initrd_filename, below_4g_mem_size, above_4g_mem_size, rom_memory, &ram_memory, guest_info); } /* irq lines */ gsi_state = g_malloc0(sizeof(*gsi_state)); if (kvm_irqchip_in_kernel()) { kvm_pc_setup_irq_routing(pci_enabled); gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, GSI_NUM_PINS); } else { gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); } /* create pci host bus */ q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); q35_host->mch.ram_memory = ram_memory; q35_host->mch.pci_address_space = pci_memory; q35_host->mch.system_memory = get_system_memory(); q35_host->mch.address_space_io = get_system_io(); q35_host->mch.below_4g_mem_size = below_4g_mem_size; q35_host->mch.above_4g_mem_size = above_4g_mem_size; q35_host->mch.guest_info = guest_info; /* pci */ qdev_init_nofail(DEVICE(q35_host)); phb = PCI_HOST_BRIDGE(q35_host); host_bus = phb->bus; /* create ISA bus */ lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true, TYPE_ICH9_LPC_DEVICE); ich9_lpc = ICH9_LPC_DEVICE(lpc); ich9_lpc->pic = gsi; ich9_lpc->ioapic = gsi_state->ioapic_irq; pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, ICH9_LPC_NB_PIRQS); pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); isa_bus = ich9_lpc->isa_bus; /*end early*/ isa_bus_irqs(isa_bus, gsi); if (kvm_irqchip_in_kernel()) { i8259 = kvm_i8259_init(isa_bus); } else if (xen_enabled()) { i8259 = xen_interrupt_controller_init(); } else { cpu_irq = pc_allocate_cpu_irq(); i8259 = i8259_init(isa_bus, cpu_irq[0]); } for (i = 0; i < ISA_NUM_IRQS; i++) { gsi_state->i8259_irq[i] = i8259[i]; } if (pci_enabled) { ioapic_init_gsi(gsi_state, NULL); } qdev_init_nofail(icc_bridge); pc_register_ferr_irq(gsi[13]); /* init basic PC hardware */ pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false, 0xff0104); /* connect pm stuff to lpc */ ich9_lpc_pm_init(lpc); /* ahci and SATA device, for q35 1 ahci controller is built-in */ ahci = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_SATA1_DEV, ICH9_SATA1_FUNC), true, "ich9-ahci"); idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); if (usb_enabled(false)) { /* Should we create 6 UHCI according to ich9 spec? */ ehci_create_ich9_with_companions(host_bus, 0x1d); } /* TODO: Populate SPD eeprom data. */ smbus_eeprom_init(ich9_smb_init(host_bus, PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 0xb100), 8, NULL, 0); pc_cmos_init(below_4g_mem_size, above_4g_mem_size, args->boot_order, floppy, idebus[0], idebus[1], rtc_state); /* the rest devices to which pci devfn is automatically assigned */ pc_vga_init(isa_bus, host_bus); pc_nic_init(isa_bus, host_bus); if (pci_enabled) { pc_pci_device_init(host_bus); } }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; u32 apicid_sp5100; u32 apicid_sr5650; device_t dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); get_bus_conf(); mptable_write_buses(mc, NULL, &bus_isa); /* * AGESA v5 Apply apic enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * For systems with < 16 APICs, put the Local-APICs at 0..n and * put the IO-APICs at (n + 1)..z */ if (CONFIG_MAX_CPUS >= 16) apicid_sp5100 = 0x0; else apicid_sp5100 = CONFIG_MAX_CPUS + 1; apicid_sr5650 = apicid_sp5100 + 1; dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); if (dev) { /* Set SP5100 IOAPIC ID */ dword = pci_read_config32(dev, 0x74) & 0xfffffff0; smp_write_ioapic(mc, apicid_sp5100, 0x20, dword); #ifdef UNUSED_CODE u8 byte; /* Initialize interrupt mapping */ /* aza */ byte = pci_read_config8(dev, 0x63); byte &= 0xf8; byte |= 0; /* 0: INTA, ...., 7: INTH */ pci_write_config8(dev, 0x63, byte); /* SATA */ dword = pci_read_config32(dev, 0xAC); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ /* dword |= 1<<22; PIC and APIC co exists */ pci_write_config32(dev, 0xAC, dword); #endif /* * 00:12.0: PROG SATA : INT F * 00:13.0: INTA USB_0 * 00:13.1: INTB USB_1 * 00:13.2: INTC USB_2 * 00:13.3: INTD USB_3 * 00:13.4: INTC USB_4 * 00:13.5: INTD USB2 * 00:14.1: INTA IDE * 00:14.2: Prog HDA : INT E * 00:14.5: INTB ACI * 00:14.6: INTB MCI */ /* Set RS5650 IOAPIC ID */ dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (dev) { pci_write_config32(dev, 0xF8, 0x1); dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; smp_write_ioapic(mc, apicid_sr5650, 0x20, dword); } } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sp5100, (pin)) /* SMBUS */ //PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0 /* HD Audio */ PCI_INT(0x0, 0x14, 0x2, 0x10); /* USB */ /* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */ /* EHCI hard-wired to 02h, corresponding to using INTB# */ /* USB1 */ PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */ PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */ PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */ /* USB2 */ PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */ PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */ PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */ /* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */ PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */ /* SATA */ PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG /* on board NIC & Slot PCIE. */ /* configuration B doesnt need dev 5,6,7 */ /* * PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11); * PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12); * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13); */ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */ /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14); PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15); PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16); PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15); PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16); PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17); PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16); PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17); PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14); PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffe; memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 1; fadt->firmware_ctrl = (unsigned long)facs; fadt->dsdt = (unsigned long)dsdt; fadt->model = 1; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; fadt->s4bios_req = 0x0; fadt->pstate_cnt = APM_CNT_PST_CONTROL; fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; fadt->pm1a_cnt_blk = pmbase + 0x4; fadt->pm1b_cnt_blk = 0x0; fadt->pm2_cnt_blk = pmbase + 0x20; fadt->pm_tmr_blk = pmbase + 0x8; fadt->gpe0_blk = pmbase + 0x28; fadt->gpe1_blk = 0; fadt->pm1_evt_len = 4; fadt->pm1_cnt_len = 2; // XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0) fadt->pm2_cnt_len = 2; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 8; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; fadt->cst_cnt = APM_CNT_CST_CONTROL; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 85; fadt->flush_size = 1024; fadt->flush_stride = 16; fadt->duty_offset = 1; fadt->duty_width = 0; fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x00; fadt->iapc_boot_arch = 0x03; fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; fadt->reset_reg.space_id = 0; fadt->reset_reg.bit_width = 0; fadt->reset_reg.bit_offset = 0; fadt->reset_reg.resv = 0; fadt->reset_reg.addrl = 0x0; fadt->reset_reg.addrh = 0x0; fadt->reset_value = 0; fadt->x_firmware_ctl_l = (unsigned long)facs; fadt->x_firmware_ctl_h = 0; fadt->x_dsdt_l = (unsigned long)dsdt; fadt->x_dsdt_h = 0; fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.resv = 0; fadt->x_pm1a_evt_blk.addrl = pmbase; fadt->x_pm1a_evt_blk.addrh = 0x0; fadt->x_pm1b_evt_blk.space_id = 1; fadt->x_pm1b_evt_blk.bit_width = 0; fadt->x_pm1b_evt_blk.bit_offset = 0; fadt->x_pm1b_evt_blk.resv = 0; fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0; fadt->x_pm1a_cnt_blk.space_id = 1; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.resv = 0; fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; fadt->x_pm1a_cnt_blk.addrh = 0x0; fadt->x_pm1b_cnt_blk.space_id = 1; fadt->x_pm1b_cnt_blk.bit_width = 0; fadt->x_pm1b_cnt_blk.bit_offset = 0; fadt->x_pm1b_cnt_blk.resv = 0; fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.resv = 0; fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.resv = 0; fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 64; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.resv = 0; fadt->x_gpe0_blk.addrl = pmbase + 0x28; fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; fadt->x_gpe1_blk.bit_width = 0; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.resv = 0; fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; header->checksum = acpi_checksum((void *)fadt, header->length); }
static int via_cx700_int15_handler(void) { int res = 0; u8 mem_speed; #define MEMORY_SPEED_66MHZ (0 << 4) #define MEMORY_SPEED_100MHZ (1 << 4) #define MEMORY_SPEED_133MHZ (1 << 4) #define MEMORY_SPEED_200MHZ (3 << 4) // DDR200 #define MEMORY_SPEED_266MHZ (4 << 4) // DDR266 #define MEMORY_SPEED_333MHZ (5 << 4) // DDR333 #define MEMORY_SPEED_400MHZ (6 << 4) // DDR400 #define MEMORY_SPEED_533MHZ (7 << 4) // DDR533 #define MEMORY_SPEED_667MHZ (8 << 4) // DDR667 const u8 memory_mapping[6] = { MEMORY_SPEED_200MHZ, MEMORY_SPEED_266MHZ, MEMORY_SPEED_333MHZ, MEMORY_SPEED_400MHZ, MEMORY_SPEED_533MHZ, MEMORY_SPEED_667MHZ }; printk(BIOS_DEBUG, "via_cx700_int15_handler\n"); switch(X86_EAX & 0xffff) { case 0x5f00: /* VGA POST Initialization Signal */ X86_EAX = (X86_EAX & 0xffff0000 ) | 0x5f; res = 1; break; case 0x5f01: /* Software Panel Type Configuration */ X86_EAX = (X86_EAX & 0xffff0000 ) | 0x5f; // panel type = 2 = 1024 * 768 X86_ECX = (X86_ECX & 0xffffff00 ) | 2; res = 1; break; case 0x5f27: /* Boot Device Selection */ X86_EAX = (X86_EAX & 0xffff0000 ) | 0x5f; X86_EBX = 0x00000000; // 0 -> default X86_ECX = 0x00000000; // 0 -> default // TV Layout - default X86_EDX = (X86_EDX & 0xffffff00) | 0; res = 1; break; case 0x5f0b: /* Get Expansion Setting */ X86_EAX = (X86_EAX & 0xffff0000 ) | 0x5f; X86_ECX = X86_ECX & 0xffffff00; // non-expansion // regs->ecx = regs->ecx & 0xffffff00 | 1; // expansion res = 1; break; case 0x5f0f: /* VGA Post Completion */ X86_EAX = (X86_EAX & 0xffff0000 ) | 0x5f; res = 1; break; case 0x5f18: X86_EAX = (X86_EAX & 0xffff0000 ) | 0x5f; #define UMA_SIZE_8MB (3 << 0) #define UMA_SIZE_16MB (4 << 0) #define UMA_SIZE_32MB (5 << 0) X86_EBX = (X86_EBX & 0xffff0000 ) | MEMORY_SPEED_533MHZ | UMA_SIZE_32MB; mem_speed = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 4)), SCRATCH_DRAM_FREQ); if (mem_speed > 5) mem_speed = 5; X86_EBX |= memory_mapping[mem_speed]; res = 1; break; default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_EAX & 0xffff); break; } return res; }
/* PC hardware initialisation */ static void pc_q35_init(MachineState *machine) { PCMachineState *pcms = PC_MACHINE(machine); PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); Q35PCIHost *q35_host; PCIHostState *phb; PCIBus *host_bus; PCIDevice *lpc; DeviceState *lpc_dev; BusState *idebus[MAX_SATA_PORTS]; ISADevice *rtc_state; MemoryRegion *system_io = get_system_io(); MemoryRegion *pci_memory; MemoryRegion *rom_memory; MemoryRegion *ram_memory; GSIState *gsi_state; ISABus *isa_bus; qemu_irq *i8259; int i; ICH9LPCState *ich9_lpc; PCIDevice *ahci; ram_addr_t lowmem; DriveInfo *hd[MAX_SATA_PORTS]; MachineClass *mc = MACHINE_GET_CLASS(machine); /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping * also known as MMCFG). * If it doesn't, we need to split it in chunks below and above 4G. * In any case, try to make sure that guest addresses aligned at * 1G boundaries get mapped to host addresses aligned at 1G boundaries. */ if (machine->ram_size >= 0xb0000000) { lowmem = 0x80000000; } else { lowmem = 0xb0000000; } /* Handle the machine opt max-ram-below-4g. It is basically doing * min(qemu limit, user limit). */ if (!pcms->max_ram_below_4g) { pcms->max_ram_below_4g = 1ULL << 32; /* default: 4G */; } if (lowmem > pcms->max_ram_below_4g) { lowmem = pcms->max_ram_below_4g; if (machine->ram_size - lowmem > lowmem && lowmem & ((1ULL << 30) - 1)) { error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64 ") not a multiple of 1G; possible bad performance.", pcms->max_ram_below_4g); } } if (machine->ram_size >= lowmem) { pcms->above_4g_mem_size = machine->ram_size - lowmem; pcms->below_4g_mem_size = lowmem; } else { pcms->above_4g_mem_size = 0; pcms->below_4g_mem_size = machine->ram_size; } if (xen_enabled()) { xen_hvm_init(pcms, &ram_memory); } pc_cpus_init(pcms); kvmclock_create(); /* pci enabled */ if (pcmc->pci_enabled) { pci_memory = g_new(MemoryRegion, 1); memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); rom_memory = pci_memory; } else { pci_memory = NULL; rom_memory = get_system_memory(); } pc_guest_info_init(pcms); if (pcmc->smbios_defaults) { /* These values are guest ABI, do not change */ smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", mc->name, pcmc->smbios_legacy_mode, pcmc->smbios_uuid_encoded, SMBIOS_ENTRY_POINT_21); } /* allocate ram and load rom/bios */ if (!xen_enabled()) { pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory); } /* irq lines */ gsi_state = g_malloc0(sizeof(*gsi_state)); if (kvm_ioapic_in_kernel()) { kvm_pc_setup_irq_routing(pcmc->pci_enabled); pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, GSI_NUM_PINS); } else { pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); } /* create pci host bus */ q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory), MCH_HOST_PROP_RAM_MEM, NULL); object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory), MCH_HOST_PROP_PCI_MEM, NULL); object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()), MCH_HOST_PROP_SYSTEM_MEM, NULL); object_property_set_link(OBJECT(q35_host), OBJECT(system_io), MCH_HOST_PROP_IO_MEM, NULL); object_property_set_int(OBJECT(q35_host), pcms->below_4g_mem_size, PCI_HOST_BELOW_4G_MEM_SIZE, NULL); object_property_set_int(OBJECT(q35_host), pcms->above_4g_mem_size, PCI_HOST_ABOVE_4G_MEM_SIZE, NULL); /* pci */ qdev_init_nofail(DEVICE(q35_host)); phb = PCI_HOST_BRIDGE(q35_host); host_bus = phb->bus; /* create ISA bus */ lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true, TYPE_ICH9_LPC_DEVICE); object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, TYPE_HOTPLUG_HANDLER, (Object **)&pcms->acpi_dev, object_property_allow_set_link, OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); object_property_set_link(OBJECT(machine), OBJECT(lpc), PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); ich9_lpc = ICH9_LPC_DEVICE(lpc); lpc_dev = DEVICE(lpc); for (i = 0; i < GSI_NUM_PINS; i++) { qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, pcms->gsi[i]); } pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, ICH9_LPC_NB_PIRQS); pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); isa_bus = ich9_lpc->isa_bus; if (kvm_pic_in_kernel()) { i8259 = kvm_i8259_init(isa_bus); } else if (xen_enabled()) { i8259 = xen_interrupt_controller_init(); } else { i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq()); } for (i = 0; i < ISA_NUM_IRQS; i++) { gsi_state->i8259_irq[i] = i8259[i]; } g_free(i8259); if (pcmc->pci_enabled) { ioapic_init_gsi(gsi_state, "q35"); } pc_register_ferr_irq(pcms->gsi[13]); assert(pcms->vmport != ON_OFF_AUTO__MAX); if (pcms->vmport == ON_OFF_AUTO_AUTO) { pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; } /* init basic PC hardware */ pc_basic_device_init(isa_bus, pcms->gsi, &rtc_state, !mc->no_floppy, (pcms->vmport != ON_OFF_AUTO_ON), pcms->pit, 0xff0104); /* connect pm stuff to lpc */ ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms)); if (pcms->sata) { /* ahci and SATA device, for q35 1 ahci controller is built-in */ ahci = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_SATA1_DEV, ICH9_SATA1_FUNC), true, "ich9-ahci"); idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports); ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports); ahci_ide_create_devs(ahci, hd); } else { idebus[0] = idebus[1] = NULL; } if (machine_usb(machine)) { /* Should we create 6 UHCI according to ich9 spec? */ ehci_create_ich9_with_companions(host_bus, 0x1d); } if (pcms->smbus) { /* TODO: Populate SPD eeprom data. */ smbus_eeprom_init(ich9_smb_init(host_bus, PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 0xb100), 8, NULL, 0); } pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); /* the rest devices to which pci devfn is automatically assigned */ pc_vga_init(isa_bus, host_bus); pc_nic_init(isa_bus, host_bus); if (pcmc->pci_enabled) { pc_pci_device_init(host_bus); } if (pcms->acpi_nvdimm_state.is_enabled) { nvdimm_init_acpi_state(&pcms->acpi_nvdimm_state, system_io, pcms->fw_cfg, OBJECT(pcms)); } }
static void usb_init2(struct device *dev) { u32 dword; void *usb2_bar0; device_t sm_dev; u8 rev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); rev = get_sb700_revision(sm_dev); /* dword = pci_read_config32(dev, 0xf8); */ /* dword |= 40; */ /* pci_write_config32(dev, 0xf8, dword); */ usb2_bar0 = (void *)(pci_read_config32(dev, 0x10) & ~0xFF); printk(BIOS_INFO, "usb2_bar0=0x%p\n", usb2_bar0); /* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */ dword = 0x00020F00; write32(usb2_bar0 + 0xC0, dword); /* RPR6.9 Sets In/OUT FIFO threshold for best performance */ dword = 0x00400040; write32(usb2_bar0 + 0xA4, dword); /* RPR6.11 Disabling EHCI Advance Asynchronous Enhancement */ dword = pci_read_config32(dev, 0x50); dword |= (1 << 28); pci_write_config32(dev, 0x50, dword); /* RPR 6.12 EHCI Advance PHY Power Savings */ /* RPR says it is just for A12. CIMM sets it when it is above A11. */ /* But it makes the linux crash, so we skip it */ dword = pci_read_config32(dev, 0x50); dword |= 1 << 31; pci_write_config32(dev, 0x50, dword); /* RPR6.13 Enabling Fix for EHCI Controller Driver Yellow Sign Issue */ /* RPR says it is just for A12. CIMx sets it when it is above A11. */ dword = pci_read_config32(dev, 0x50); dword |= (1 << 20); pci_write_config32(dev, 0x50, dword); /* RPR6.15 EHCI Async Park Mode */ dword = pci_read_config32(dev, 0x50); dword |= (1 << 23); pci_write_config32(dev, 0x50, dword); /* Each step below causes the linux crashes. Leave them here * for future debugging. */ u8 byte; u16 word; /* RPR6.16 Disable EHCI MSI support */ byte = pci_read_config8(dev, 0x50); byte |= (1 << 6); pci_write_config8(dev, 0x50, byte); /* RPR6.17 Disable the EHCI Dynamic Power Saving feature */ word = read32(usb2_bar0 + 0xBC); word &= ~(1 << 12); write16(usb2_bar0 + 0xBC, word); /* RPR6.19 USB Controller DMA Read Delay Tolerant. */ if (rev >= REV_SB700_A14) { byte = pci_read_config8(dev, 0x50); byte |= (1 << 7); pci_write_config8(dev, 0x50, byte); } /* SB700_A15, USB-2_EHCI_PID_ERROR_CHECKING */ if (rev == REV_SB700_A15) { word = pci_read_config16(dev, 0x50); word |= (1 << 9); pci_write_config16(dev, 0x50, word); } /* RPR6.20 Async Park Mode. */ /* RPR recommends not to set these bits. */ #if 0 dword = pci_read_config32(dev, 0x50); dword |= 1 << 23; if (rev >= REV_SB700_A14) { dword &= ~(1 << 2); } pci_write_config32(dev, 0x50, dword); #endif /* RPR6.22 Advance Async Enhancement */ /* RPR6.23 USB Periodic Cache Setting */ dword = pci_read_config32(dev, 0x50); if (rev == REV_SB700_A12) { dword |= 1 << 28; /* 6.22 */ dword |= 1 << 27; /* 6.23 */ } else if (rev >= REV_SB700_A14) { dword |= 1 << 3; dword &= ~(1 << 28); /* 6.22 */ dword |= 1 << 8; dword &= ~(1 << 27); /* 6.23 */ } pci_write_config32(dev, 0x50, dword); printk(BIOS_DEBUG, "rpr 6.23, final dword=%x\n", dword); }
void get_bus_conf(void) { u32 status; device_t dev; int i, j; if (get_bus_conf_done == 1) return; /* do it only once */ get_bus_conf_done = 1; /* * This is the call to AmdInitLate. It is really in the wrong place, conceptually, * but functionally within the coreboot model, this is the best place to make the * call. The logically correct place to call AmdInitLate is after PCI scan is done, * after the decision about S3 resume is made, and before the system tables are * written into RAM. The routine that is responsible for writing the tables is * "write_tables", called near the end of "hardwaremain". There is no platform * specific entry point between the S3 resume decision point and the call to * "write_tables", and the next platform specific entry points are the calls to * the ACPI table write functions. The first of ose would seem to be the right * place, but other table write functions, e.g. the PIRQ table write function, are * called before the ACPI tables are written. This routine is called at the beginning * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ status = agesawrapper_amdinitlate(); if(status) { printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); } sbdn_sp5100 = 0; for (i = 0; i < ARRAY_SIZE(bus_sp5100); i++) { bus_sp5100[i] = 0; } for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) { bus_sr5650[i] = 0; } for (i = 0; i < 256; i++) { bus_type[i] = 0; /* default ISA bus. */ } bus_type[0] = 1; /* pci */ bus_sr5650[0] = 0; bus_sp5100[0] = bus_sr5650[0]; /* sp5100 */ dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4)); if (dev) { bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; for (j = bus_sp5100[1]; j < bus_isa; j++) bus_type[j] = 1; } /* sr5650 */ for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) { dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sbdn_sr5650 + i, 0)); if (dev) { bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); if(255 != bus_sr5650[i]) { bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; bus_type[bus_sr5650[i]] = 1; /* PCI bus. */ } } } /* for (i = 0; i < 4; i++) { dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, i)); if (dev) { bus_sp5100[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; } } for (j = bus_sp5100[2]; j < bus_isa; j++) bus_type[j] = 1; */ /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; #if CONFIG_AMD_SB_CIMX sb_After_Pci_Init(); sb_Late_Post(); #endif }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int i, j, bus_isa; struct mb_sysconf_t *m; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); smp_write_processors(mc); get_bus_conf(); m = sysconf.mb; mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 { device_t dev; struct resource *res; dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base); } } dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base); } } j = 0; for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; switch(sysconf.hcid[i]) { case 1: // 8132 case 3: // 8131 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base); } } dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base); } } break; } j++; } } mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ //??? What smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); // Onboard AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13); //Slot 3 PCI 32 for(i=0; i<4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 } //Slot 4 PCI 32 for(i=0; i<4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 } //Slot 1 PCI-X 133/100/66 for(i=0; i<4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); // } //Slot 2 PCI-X 133/100/66 for(i=0; i<4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25 } j = 0; for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; device_t dev; struct resource *res; switch(sysconf.hcid[i]) { case 1: case 3: dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { //Slot 1 PCI-X 133/100/66 for(ii=0; ii<4; ii++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // } } } dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { //Slot 2 PCI-X 133/100/66 for(ii=0; ii<4; ii++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 } } } break; case 2: // Slot AGP smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11); break; } j++; } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
static unsigned int init_chipset_ali15x3(struct pci_dev *dev) { unsigned long flags; u8 tmpbyte; struct pci_dev *north = pci_get_slot(dev->bus, PCI_DEVFN(0,0)); m5229_revision = dev->revision; isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL); local_irq_save(flags); if (m5229_revision < 0xC2) { /* * revision 0x20 (1543-E, 1543-F) * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E) * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7 */ pci_read_config_byte(dev, 0x4b, &tmpbyte); /* * clear bit 7 */ pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F); /* * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010 */ if (m5229_revision >= 0x20 && isa_dev) { pci_read_config_byte(isa_dev, 0x5e, &tmpbyte); chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0; } goto out; } /* * 1543C-B?, 1535, 1535D, 1553 * Note 1: not all "motherboard" support this detection * Note 2: if no udma 66 device, the detection may "error". * but in this case, we will not set the device to * ultra 66, the detection result is not important */ /* * enable "Cable Detection", m5229, 0x4b, bit3 */ pci_read_config_byte(dev, 0x4b, &tmpbyte); pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08); /* * We should only tune the 1533 enable if we are using an ALi * North bridge. We might have no north found on some zany * box without a device at 0:0.0. The ALi bridge will be at * 0:0.0 so if we didn't find one we know what is cooking. */ if (north && north->vendor != PCI_VENDOR_ID_AL) goto out; if (m5229_revision < 0xC5 && isa_dev) { /* * set south-bridge's enable bit, m1533, 0x79 */ pci_read_config_byte(isa_dev, 0x79, &tmpbyte); if (m5229_revision == 0xC2) { /* * 1543C-B0 (m1533, 0x79, bit 2) */ pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04); } else if (m5229_revision >= 0xC3) { /* * 1553/1535 (m1533, 0x79, bit 1) */ pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02); } } out: /* * CD_ROM DMA on (m5229, 0x53, bit0) * Enable this bit even if we want to use PIO. * PIO FIFO off (m5229, 0x53, bit1) * The hardware will use 0x54h and 0x55h to control PIO FIFO. * (Not on later devices it seems) * * 0x53 changes meaning on later revs - we must no touch * bit 1 on them. Need to check if 0x20 is the right break. */ if (m5229_revision >= 0x20) { pci_read_config_byte(dev, 0x53, &tmpbyte); if (m5229_revision <= 0x20) tmpbyte = (tmpbyte & (~0x02)) | 0x01; else if (m5229_revision == 0xc7 || m5229_revision == 0xc8) tmpbyte |= 0x03; else tmpbyte |= 0x01; pci_write_config_byte(dev, 0x53, tmpbyte); } pci_dev_put(north); pci_dev_put(isa_dev); local_irq_restore(flags); return 0; }
void adir_find_bridges(void) { struct pci_controller *hose_a, *hose_b; /* Setup PCI32 hose */ hose_a = pcibios_alloc_controller(); if (!hose_a) return; hose_a->first_busno = 0; hose_a->last_busno = 0xff; hose_a->pci_mem_offset = ADIR_PCI32_MEM_BASE; hose_a->io_space.start = 0; hose_a->io_space.end = ADIR_PCI32_VIRT_IO_SIZE - 1; hose_a->mem_space.start = 0; hose_a->mem_space.end = ADIR_PCI32_MEM_SIZE - 1; hose_a->io_resource.start = 0; hose_a->io_resource.end = ADIR_PCI32_VIRT_IO_SIZE - 1; hose_a->io_resource.flags = IORESOURCE_IO; hose_a->mem_resources[0].start = ADIR_PCI32_MEM_BASE; hose_a->mem_resources[0].end = ADIR_PCI32_MEM_BASE + ADIR_PCI32_MEM_SIZE - 1; hose_a->mem_resources[0].flags = IORESOURCE_MEM; hose_a->io_base_phys = ADIR_PCI32_IO_BASE; hose_a->io_base_virt = (void *) ADIR_PCI32_VIRT_IO_BASE; ppc_md.pci_exclude_device = adir_exclude_device; setup_indirect_pci(hose_a, ADIR_PCI32_CONFIG_ADDR, ADIR_PCI32_CONFIG_DATA); /* Initialize PCI32 bus registers */ early_write_config_byte(hose_a, hose_a->first_busno, PCI_DEVFN(0, 0), CPC710_BUS_NUMBER, hose_a->first_busno); early_write_config_byte(hose_a, hose_a->first_busno, PCI_DEVFN(0, 0), CPC710_SUB_BUS_NUMBER, hose_a->last_busno); hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno); /* Write out correct max subordinate bus number for hose A */ early_write_config_byte(hose_a, hose_a->first_busno, PCI_DEVFN(0, 0), CPC710_SUB_BUS_NUMBER, hose_a->last_busno); /* Setup PCI64 hose */ hose_b = pcibios_alloc_controller(); if (!hose_b) return; hose_b->first_busno = hose_a->last_busno + 1; hose_b->last_busno = 0xff; hose_b->pci_mem_offset = ADIR_PCI64_MEM_BASE; hose_b->io_space.start = 0; hose_b->io_space.end = ADIR_PCI64_VIRT_IO_SIZE - 1; hose_b->mem_space.start = 0; hose_b->mem_space.end = ADIR_PCI64_MEM_SIZE - 1; hose_b->io_resource.start = 0; hose_b->io_resource.end = ADIR_PCI64_VIRT_IO_SIZE - 1; hose_b->io_resource.flags = IORESOURCE_IO; hose_b->mem_resources[0].start = ADIR_PCI64_MEM_BASE; hose_b->mem_resources[0].end = ADIR_PCI64_MEM_BASE + ADIR_PCI64_MEM_SIZE - 1; hose_b->mem_resources[0].flags = IORESOURCE_MEM; hose_b->io_base_phys = ADIR_PCI64_IO_BASE; hose_b->io_base_virt = (void *) ADIR_PCI64_VIRT_IO_BASE; setup_indirect_pci(hose_b, ADIR_PCI64_CONFIG_ADDR, ADIR_PCI64_CONFIG_DATA); /* Initialize PCI64 bus registers */ early_write_config_byte(hose_b, 0, PCI_DEVFN(0, 0), CPC710_SUB_BUS_NUMBER, 0xff); early_write_config_byte(hose_b, 0, PCI_DEVFN(0, 0), CPC710_BUS_NUMBER, hose_b->first_busno); hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno); /* Write out correct max subordinate bus number for hose B */ early_write_config_byte(hose_b, hose_b->first_busno, PCI_DEVFN(0, 0), CPC710_SUB_BUS_NUMBER, hose_b->last_busno); ppc_md.pcibios_fixup = NULL; ppc_md.pci_swizzle = common_swizzle; ppc_md.pci_map_irq = adir_map_irq; }
static int pcifront_detach_devices(struct pcifront_device *pdev) { int err = 0; int i, num_devs; unsigned int domain, bus, slot, func; struct pci_bus *pci_bus; struct pci_dev *pci_dev; char str[64]; spin_lock(&pdev->dev_lock); if (xenbus_read_driver_state(pdev->xdev->nodename) != XenbusStateConnected) goto out; err = xenbus_scanf(XBT_NIL, pdev->xdev->otherend, "num_devs", "%d", &num_devs); if (err != 1) { if (err >= 0) err = -EINVAL; xenbus_dev_fatal(pdev->xdev, err, "Error reading number of PCI devices"); goto out; } /* Find devices being detached and remove them. */ for (i = 0; i < num_devs; i++) { int l, state; l = snprintf(str, sizeof(str), "state-%d", i); if (unlikely(l >= (sizeof(str) - 1))) { err = -ENOMEM; goto out; } err = xenbus_scanf(XBT_NIL, pdev->xdev->otherend, str, "%d", &state); if (err != 1) state = XenbusStateUnknown; if (state != XenbusStateClosing) continue; /* Remove device. */ l = snprintf(str, sizeof(str), "vdev-%d", i); if (unlikely(l >= (sizeof(str) - 1))) { err = -ENOMEM; goto out; } err = xenbus_scanf(XBT_NIL, pdev->xdev->otherend, str, "%x:%x:%x.%x", &domain, &bus, &slot, &func); if (err != 4) { if (err >= 0) err = -EINVAL; xenbus_dev_fatal(pdev->xdev, err, "Error reading PCI device %d", i); goto out; } pci_bus = pci_find_bus(domain, bus); if(!pci_bus) { dev_dbg(&pdev->xdev->dev, "Cannot get bus %04x:%02x\n", domain, bus); continue; } pci_dev = pci_get_slot(pci_bus, PCI_DEVFN(slot, func)); if(!pci_dev) { dev_dbg(&pdev->xdev->dev, "Cannot get PCI device %04x:%02x:%02x.%02x\n", domain, bus, slot, func); continue; } pci_remove_bus_device(pci_dev); pci_dev_put(pci_dev); dev_dbg(&pdev->xdev->dev, "PCI device %04x:%02x:%02x.%02x removed.\n", domain, bus, slot, func); } err = xenbus_switch_state(pdev->xdev, XenbusStateReconfiguring); out: spin_unlock(&pdev->dev_lock); return err; }
unsigned long write_pirq_routing_table(unsigned long addr) { struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; u8 *v; u8 sum = 0; int i; /* Align the table to be 16 byte aligned. */ addr += 15; addr &= ~15; /* This table must be between 0xf0000 & 0x100000 */ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); pirq = (void *)(addr); v = (u8 *) (addr); pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; pirq->rtr_bus = 0; pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; pirq->rtr_vendor = 0x1002; pirq->rtr_device = 0x4384; pirq->miniport_data = 0; memset(pirq->rfu, 0, sizeof(pirq->rfu)); pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; /* pci bridge */ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdee8, 0x2, 0xdee8, 0x3, 0xdee8, 0x4, 0xdee8, 0, 0); pirq_info++; slot_num++; pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) sum += v[i]; sum = pirq->checksum - sum; if (sum != pirq->checksum) { pirq->checksum = sum; } printk(BIOS_INFO, "write_pirq_routing_table done.\n"); return (unsigned long)pirq_info; }
unsigned long acpi_fill_madt(unsigned long current) { u32 gsi_base = 0x18; struct mb_sysconf_t *m; m = sysconf.mb; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); /* Write 8111 IOAPIC */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111, IO_APIC_ADDR, 0); /* Write all 8131 IOAPICs */ { device_t dev; struct resource *res; dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1, res->base, gsi_base ); gsi_base+=7; } } dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2, res->base, gsi_base ); gsi_base+=7; } } int i; int j = 0; for(i = 1; i < sysconf.hc_possible_num; i++) { u32 d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; /* 8131 need to use +4 */ switch (sysconf.hcid[i]) { case 1: d = 7; break; case 3: d = 4; break; } switch (sysconf.hcid[i]) { case 1: case 3: dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0], res->base, gsi_base ); gsi_base+=d; } } dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], res->base, gsi_base ); gsi_base+=d; } } break; } j++; } } current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) current, 0, 0, 2, 5 ); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ /* 5 mean: 0101 --> Edge-triggered, Active high*/ /* create all subtables for processors */ current = acpi_create_madt_lapic_nmis(current, 5, 1); /* 1: LINT1 connect to NMI */ return current; }
void get_bus_conf(void) { unsigned apicid_base; device_t dev; int i, j; struct mb_sysconf_t *m; if(get_bus_conf_done == 1) return; //do it only once get_bus_conf_done = 1; sysconf.mb = &mb_sysconf; m = sysconf.mb; sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } get_sblk_pci1234(); sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; m->sbdn3 = sysconf.hcdn[0] & 0xff; m->bus_8132_0 = (sysconf.pci1234[0] >> 16) & 0xff; m->bus_8111_0 = m->bus_8132_0; /* 8111 */ dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn); } /* 8132-1 */ dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3,0)); if (dev) { m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3); } /* 8132-2 */ dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0)); if (dev) { m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1); } /* HT chain 1 */ j=0; for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; // check hcid type here sysconf.hcid[i] = get_hcid(i); switch(sysconf.hcid[i]) { case 1: //8132 case 3: //8131 m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; m->sbdn3a[j] = sysconf.hcdn[i] & 0xff; /* 8132-1 */ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j],0)); if (dev) { m->bus_8132a[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]); } /* 8132-2 */ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1,0)); if (dev) { m->bus_8132a[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1); } break; case 2: //8151 m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; m->sbdn5[j] = sysconf.hcdn[i] & 0xff; /* 8151 */ dev = dev_find_slot(m->bus_8151[j][0], PCI_DEVFN(m->sbdn5[j]+1, 0)); if (dev) { m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS); // printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151[j][1]); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1); } break; } j++; } /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif m->apicid_8111 = apicid_base+0; m->apicid_8132_1 = apicid_base+1; m->apicid_8132_2 = apicid_base+2; for(i=0;i<j;i++) { m->apicid_8132a[i][0] = apicid_base + 3 + i*2; m->apicid_8132a[i][1] = apicid_base + 3 + i*2 + 1; } }
static int __devinit agp_serverworks_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { struct agp_bridge_data *bridge; struct pci_dev *bridge_dev; u32 temp, temp2; u8 cap_ptr = 0; /* Everything is on func 1 here so we are hardcoding function one */ bridge_dev = pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 1)); if (!bridge_dev) { printk(KERN_INFO PFX "Detected a Serverworks chipset " "but could not find the secondary device.\n"); return -ENODEV; } cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); switch (pdev->device) { case 0x0006: /* ServerWorks CNB20HE Fail silently.*/ printk (KERN_ERR PFX "Detected ServerWorks CNB20HE chipset: No AGP present.\n"); return -ENODEV; case PCI_DEVICE_ID_SERVERWORKS_HE: case PCI_DEVICE_ID_SERVERWORKS_LE: case 0x0007: break; default: if (cap_ptr) printk(KERN_ERR PFX "Unsupported Serverworks chipset " "(device id: %04x)\n", pdev->device); return -ENODEV; } serverworks_private.svrwrks_dev = bridge_dev; serverworks_private.gart_addr_ofs = 0x10; pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp); if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) { pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2); if (temp2 != 0) { printk(KERN_INFO PFX "Detected 64 bit aperture address, " "but top bits are not zero. Disabling agp\n"); return -ENODEV; } serverworks_private.mm_addr_ofs = 0x18; } else serverworks_private.mm_addr_ofs = 0x14; pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp); if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) { pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs + 4, &temp2); if (temp2 != 0) { printk(KERN_INFO PFX "Detected 64 bit MMIO address, " "but top bits are not zero. Disabling agp\n"); return -ENODEV; } } bridge = agp_alloc_bridge(); if (!bridge) return -ENOMEM; bridge->driver = &sworks_driver; bridge->dev_private_data = &serverworks_private, bridge->dev = pdev; pci_set_drvdata(pdev, bridge); return agp_add_bridge(bridge); }
static int __devinit ohci_pci_start (struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci (hcd); int ret; if (hcd->pdev) { ohci->hcca = pci_alloc_consistent (hcd->pdev, sizeof *ohci->hcca, &ohci->hcca_dma); if (!ohci->hcca) return -ENOMEM; /* AMD 756, for most chips (early revs), corrupts register * values on read ... so enable the vendor workaround. */ if (hcd->pdev->vendor == PCI_VENDOR_ID_AMD && hcd->pdev->device == 0x740c) { ohci->flags = OHCI_QUIRK_AMD756; ohci_info (ohci, "AMD756 erratum 4 workaround\n"); } /* FIXME for some of the early AMD 760 southbridges, OHCI * won't work at all. blacklist them. */ /* Apple's OHCI driver has a lot of bizarre workarounds * for this chip. Evidently control and bulk lists * can get confused. (B&W G3 models, and ...) */ else if (hcd->pdev->vendor == PCI_VENDOR_ID_OPTI && hcd->pdev->device == 0xc861) { ohci_info (ohci, "WARNING: OPTi workarounds unavailable\n"); } /* Check for NSC87560. We have to look at the bridge (fn1) to * identify the USB (fn2). This quirk might apply to more or * even all NSC stuff. */ else if (hcd->pdev->vendor == PCI_VENDOR_ID_NS) { struct pci_dev *b, *hc; hc = hcd->pdev; b = pci_find_slot (hc->bus->number, PCI_DEVFN (PCI_SLOT (hc->devfn), 1)); if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO && b->vendor == PCI_VENDOR_ID_NS) { ohci->flags |= OHCI_QUIRK_SUPERIO; ohci_info (ohci, "Using NSC SuperIO setup\n"); } } } memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); if ((ret = ohci_mem_init (ohci)) < 0) { ohci_stop (hcd); return ret; } ohci->regs = hcd->regs; if (hc_reset (ohci) < 0) { ohci_stop (hcd); return -ENODEV; } if (hc_start (ohci) < 0) { ohci_err (ohci, "can't start\n"); ohci_stop (hcd); return -EBUSY; } #ifdef DEBUG ohci_dump (ohci, 1); #endif return 0; }
static void mainboard_enable(device_t dev) { u16 pmbase; printk(BIOS_SPEW, "starting SPI configuration\n"); /* Configure SPI. */ RCBA32(0x3800) = 0x07ff0500; RCBA32(0x3804) = 0x3f046008; RCBA32(0x3808) = 0x0058efc0; RCBA32(0x384c) = 0x92000000; RCBA32(0x3850) = 0x00000a0b; RCBA32(0x3858) = 0x07ff0500; RCBA32(0x385c) = 0x04ff0003; RCBA32(0x3860) = 0x00020001; RCBA32(0x3864) = 0x00000fff; RCBA32(0x3874) = 0; RCBA32(0x3890) = 0xf8400000; RCBA32(0x3894) = 0x143b5006; RCBA32(0x3898) = 0x05200302; RCBA32(0x389c) = 0x0601209f; RCBA32(0x38b0) = 0x00000004; RCBA32(0x38b4) = 0x03040002; RCBA32(0x38c0) = 0x00000007; RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; RCBA32(0x3804) = 0x3f04e008; printk(BIOS_SPEW, "SPI configured\n"); int i; const u8 dmp[256] = { 0x00, 0x20, 0x00, 0x00, 0x00, 0x02, 0x89, 0xe4, 0x30, 0x00, 0x40, 0x14, 0x00, 0x00, 0x00, 0x11, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0xf4, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x01, 0x04, 0x00, 0x08, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x42, 0x07, 0x09, 0x09, 0xf0, 0x00, 0x00, 0xf0, 0xa9, 0x00, 0x00, 0x06, 0x00, 0x00, 0xff, 0x00, 0x00, 0x01, 0x00, 0x04, 0xff, 0xff, 0x00, 0x00, 0x00, 0xb1, 0x00, 0x00, 0x00, 0x00, 0x04, 0x0b, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x28, 0x1b, 0x21, 0x00, 0x2c, 0x3b, 0x13, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x5a, 0x57, 0x5c, 0x00, 0x00, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, 0x00, 0x00, 0x52, 0x10, 0x52, 0x10, 0x64, 0x00, 0x00, 0x00, 0x74, 0x30, 0x00, 0x60, 0x00, 0x00, 0xaf, 0x0b, 0x30, 0x45, 0x2e, 0x30, 0x38, 0x41, 0x43, 0x2e, 0x30, 0x31, 0x2e, 0x31, 0x36, 0x20, 0x00, 0x00, }; for (i = 0; i < 256; i++) ec_write (i, dmp[i]); pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), PMBASE) & 0xff80; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); outl(0, pmbase + SMI_EN); enable_lapic(); pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL, 0x10); install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); /* This sneaked in here, because EasyNote has no SuperIO chip. */ pc_keyboard_init(); }
/* * initialise the unit hardware */ asmlinkage void __init unit_pci_init(void) { struct pci_bus bus; /* Fake bus and device */ struct pci_ops *o = &pci_direct_ampci; u32 x; set_intr_level(XIRQ1, NUM2GxICR_LEVEL(CONFIG_PCI_IRQ_LEVEL)); memset(&bus, 0, sizeof(bus)); MEM_PAGING_REG = 0xE8000000; /* we need to set up the bridge _now_ or we won't be able to access the * PCI config registers */ BRIDGEREGW(PCI_COMMAND) |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER; BRIDGEREGW(PCI_STATUS) = 0xF800; BRIDGEREGB(PCI_LATENCY_TIMER) = 0x10; BRIDGEREGL(PCI_BASE_ADDRESS_0) = 0x80000000; BRIDGEREGB(PCI_INTERRUPT_LINE) = 1; BRIDGEREGL(0x48) = 0x98000000; /* AMPCI base addr */ BRIDGEREGB(0x41) = 0x00; /* secondary bus * number */ BRIDGEREGB(0x42) = 0x01; /* subordinate bus * number */ BRIDGEREGB(0x44) = 0x01; BRIDGEREGL(0x50) = 0x00000001; BRIDGEREGL(0x58) = 0x00001002; BRIDGEREGL(0x5C) = 0x00000011; /* we also need to set up the PCI-PCI bridge */ bus.number = 0; /* IO: 0x00000000-0x00020000 */ o->read (&bus, PCI_DEVFN(3, 0), PCI_COMMAND, 2, &x); x |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR | PCI_COMMAND_PARITY; o->write(&bus, PCI_DEVFN(3, 0), PCI_COMMAND, 2, x); o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, &x); o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, &x); o->read (&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, &x); o->read (&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, &x); o->write(&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, 0x01); o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, &x); o->write(&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, 0x00020000); o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, &x); o->write(&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, 0xEBB0EA00); o->read (&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, &x); o->write(&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, 0xE9F0E800); o->read (&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, &x); unit_disable_pcnet(&bus, o); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; struct mb_sysconf_t *m; unsigned sbdn; int i, j, bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); get_bus_conf(); sbdn = sysconf.sbdn; m = sysconf.mb; mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ { device_t dev; struct resource *res; uint32_t dword; dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base); } dword = 0x43c6c643; pci_write_config32(dev, 0x7c, dword); dword = 0x81001a00; pci_write_config32(dev, 0x80, dword); dword = 0xd00002d2; pci_write_config32(dev, 0x84, dword); } } mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 for(j=7; j>=2; j--) { if(!m->bus_mcp55[j]) continue; for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } } for(j=0; j<1; j++) for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; unsigned char bus_8131_1; unsigned char bus_8131_2; unsigned char bus_8111_1; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); { device_t dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); bus_8111_1 = 4; } /* 8131-1 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); if (dev) { bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); bus_8131_1 = 2; } /* 8131-2 */ dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); bus_8131_2 = 3; } } mptable_write_buses(mc, NULL, &bus_isa); /* IOAPIC handling */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { device_t dev; struct resource *res; /* 8131 apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 0x03, 0x11, res->base); } } /* 8131 apic 4 */ dev = dev_find_slot(1, PCI_DEVFN(0x02,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 0x04, 0x11, res->base); } } } mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0); /* Standard local interrupt assignments */ mptable_lintsrc(mc, bus_isa); /* PCI Slot 1 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (1<<2)|0, 0x02, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (1<<2)|1, 0x02, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (1<<2)|2, 0x02, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (1<<2)|3, 0x02, 0x10); /* PCI Slot 2 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (2<<2)|0, 0x02, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (2<<2)|1, 0x02, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (2<<2)|2, 0x02, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (2<<2)|3, 0x02, 0x11); /* PCI Slot 3 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (1<<2)|0, 0x02, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (1<<2)|1, 0x02, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (1<<2)|2, 0x02, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (1<<2)|3, 0x02, 0x10); /* PCI Slot 4 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|0, 0x02, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|1, 0x02, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|2, 0x02, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|3, 0x02, 0x11); /* PCI Slot 5 */ // FIXME get the irqs right, it's just hacked to work for now smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (5<<2)|0, 0x02, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (5<<2)|1, 0x02, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (5<<2)|2, 0x02, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (5<<2)|3, 0x02, 0x10); /* PCI Slot 6 */ // FIXME get the irqs right, it's just hacked to work for now smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (4<<2)|0, 0x02, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (4<<2)|1, 0x02, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (4<<2)|2, 0x02, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (4<<2)|3, 0x02, 0x13); /* On board nics */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (3<<2)|0, 0x02, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (4<<2)|0, 0x02, 0x13); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
unsigned long acpi_fill_madt(unsigned long current) { device_t dev; u32 dword; u32 gsi_base = 0; u32 apicid_sb700; u32 apicid_rd890; /* * AGESA v5 Apply apic enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * For systems with < 16 APICs, put the Local-APICs at 0..n and * put the IO-APICs at (n + 1)..z */ if (CONFIG_MAX_CPUS >= 16) apicid_sb700 = 0x0; else apicid_sb700 = CONFIG_MAX_CPUS + 1; apicid_rd890 = apicid_sb700 + 1; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); /* Write sb700 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb700, IO_APIC_ADDR, 0 ); /* IOAPIC on rs5690 */ gsi_base += IO_APIC_INTERRUPTS; /* sb700 has 24 IOAPIC entries. */ dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (dev) { pci_write_config32(dev, 0xF8, 0x1); dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_rd890, dword, gsi_base ); } current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, //BUS 0, //SOURCE 2, //gsirq 0 //flags ); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ /* 5 mean: 0101 --> Edge-triggered, Active high */ /* create all subtables for processors */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); /* 1: LINT1 connect to NMI */ return current; }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; unsigned sbdn; int i, bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); get_bus_conf(); sbdn = sysconf.sbdn; mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ { device_t dev; struct resource *res; uint32_t dword; dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, apicid_ck804, 0x11, res2mmio(res, 0, 0)); } /* Initialize interrupt mapping*/ dword = 0x0120d218; pci_write_config32(dev, 0x7c, dword); dword = 0x12008a00; pci_write_config32(dev, 0x80, dword); dword = 0x0000007d; pci_write_config32(dev, 0x84, dword); } dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_1, 0x11, res2mmio(res, 0, 0)); } } dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_2, 0x11, res2mmio(res, 0, 0)); } } } mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ // Onboard ck804 smbus smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10 // Onboard ck804 USB 1.1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21 // Onboard ck804 USB 2 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20 // Onboard ck804 SATA 0 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23 // Onboard ck804 SATA 1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22 //Slot PCIE x16 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); } //Slot PCIE x4 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4); } //Slot 2 PCI 32 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); //16 } //Onboard ati smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6<<2)|0, apicid_ck804, 0x12); // 18 //Onboard intel 10/100 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (8<<2)|0, apicid_ck804, 0x12); // 18 //Channel B of 8131 //Onboard Broadcom NIC for(i=0;i<2;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28 } //SO DIMM PCI-X for(i=0;i<2;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (7<<2)|i, apicid_8131_2, (0+i)%4); //28 } //Slot 4 PCIX 133/100/66 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (2+i)%4); //30 } //Channel A of 8131 //Slot 5 PCIX 133/100/66 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|i, apicid_8131_1, (3+i)%4); //27 } //Slot 6 PCIX 133/100/66 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|i, apicid_8131_1, (2+i)%4); //26 } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); get_bus_conf(); mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; u8 byte; dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 0)); if (dev) { dword = pci_read_config32(dev, 0x74) & 0xfffffff0; smp_write_ioapic(mc, apicid_sb600, 0x11,(void *) dword); /* Initialize interrupt mapping */ /* aza */ byte = pci_read_config8(dev, 0x63); byte &= 0xf8; byte |= 0; /* 0: INTA, ...., 7: INTH */ pci_write_config8(dev, 0x63, byte); /* SATA */ dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ /* dword |= 1<<22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* * 00:12.0: PROG SATA : INT F * 00:13.0: INTA USB_0 * 00:13.1: INTB USB_1 * 00:13.2: INTC USB_2 * 00:13.3: INTD USB_3 * 00:13.4: INTC USB_4 * 00:13.5: INTD USB2 * 00:14.1: INTA IDE * 00:14.2: Prog HDA : INT E * 00:14.5: INTB ACI * 00:14.6: INTB MCI */ } } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
/* PC hardware initialisation */ static void pc_q35_init(QEMUMachineInitArgs *args) { ram_addr_t ram_size = args->ram_size; const char *cpu_model = args->cpu_model; const char *kernel_filename = args->kernel_filename; const char *kernel_cmdline = args->kernel_cmdline; const char *initrd_filename = args->initrd_filename; const char *boot_device = args->boot_device; ram_addr_t below_4g_mem_size, above_4g_mem_size; Q35PCIHost *q35_host; PCIBus *host_bus; PCIDevice *lpc; BusState *idebus[MAX_SATA_PORTS]; ISADevice *rtc_state; ISADevice *floppy; MemoryRegion *pci_memory; MemoryRegion *rom_memory; MemoryRegion *ram_memory; GSIState *gsi_state; ISABus *isa_bus; int pci_enabled = 1; qemu_irq *cpu_irq; qemu_irq *gsi; qemu_irq *i8259; int i; ICH9LPCState *ich9_lpc; PCIDevice *ahci; qemu_irq *cmos_s3; pc_cpus_init(cpu_model); pc_acpi_init("q35-acpi-dsdt.aml"); kvmclock_create(); if (ram_size >= 0xb0000000) { above_4g_mem_size = ram_size - 0xb0000000; below_4g_mem_size = 0xb0000000; } else { above_4g_mem_size = 0; below_4g_mem_size = ram_size; } /* pci enabled */ if (pci_enabled) { pci_memory = g_new(MemoryRegion, 1); memory_region_init(pci_memory, "pci", INT64_MAX); rom_memory = pci_memory; } else { pci_memory = NULL; rom_memory = get_system_memory(); } /* allocate ram and load rom/bios */ if (!xen_enabled()) { pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline, initrd_filename, below_4g_mem_size, above_4g_mem_size, rom_memory, &ram_memory); } /* irq lines */ gsi_state = g_malloc0(sizeof(*gsi_state)); if (kvm_irqchip_in_kernel()) { kvm_pc_setup_irq_routing(pci_enabled); gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, GSI_NUM_PINS); } else { gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); } /* create pci host bus */ q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); q35_host->mch.ram_memory = ram_memory; q35_host->mch.pci_address_space = pci_memory; q35_host->mch.system_memory = get_system_memory(); q35_host->mch.address_space_io = get_system_io();; q35_host->mch.below_4g_mem_size = below_4g_mem_size; q35_host->mch.above_4g_mem_size = above_4g_mem_size; /* pci */ qdev_init_nofail(DEVICE(q35_host)); host_bus = q35_host->host.pci.bus; /* create ISA bus */ lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true, TYPE_ICH9_LPC_DEVICE); ich9_lpc = ICH9_LPC_DEVICE(lpc); ich9_lpc->pic = gsi; ich9_lpc->ioapic = gsi_state->ioapic_irq; pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, ICH9_LPC_NB_PIRQS); pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); isa_bus = ich9_lpc->isa_bus; /*end early*/ isa_bus_irqs(isa_bus, gsi); if (kvm_irqchip_in_kernel()) { i8259 = kvm_i8259_init(isa_bus); } else if (xen_enabled()) { i8259 = xen_interrupt_controller_init(); } else { cpu_irq = pc_allocate_cpu_irq(); i8259 = i8259_init(isa_bus, cpu_irq[0]); } for (i = 0; i < ISA_NUM_IRQS; i++) { gsi_state->i8259_irq[i] = i8259[i]; } if (pci_enabled) { ioapic_init_gsi(gsi_state, NULL); } pc_register_ferr_irq(gsi[13]); /* init basic PC hardware */ pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false); /* connect pm stuff to lpc */ cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1); ich9_lpc_pm_init(lpc, *cmos_s3); /* ahci and SATA device, for q35 1 ahci controller is built-in */ ahci = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_SATA1_DEV, ICH9_SATA1_FUNC), true, "ich9-ahci"); idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); if (usb_enabled(false)) { /* Should we create 6 UHCI according to ich9 spec? */ ehci_create_ich9_with_companions(host_bus, 0x1d); } /* TODO: Populate SPD eeprom data. */ smbus_eeprom_init(ich9_smb_init(host_bus, PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 0xb100), 8, NULL, 0); pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, floppy, idebus[0], idebus[1], rtc_state); /* the rest devices to which pci devfn is automatically assigned */ pc_vga_init(isa_bus, host_bus); audio_init(isa_bus, host_bus); pc_nic_init(isa_bus, host_bus); if (pci_enabled) { pc_pci_device_init(host_bus); } }
static void boston_mach_init(MachineState *machine) { DeviceState *dev; BostonState *s; Error *err = NULL; MemoryRegion *flash, *ddr, *ddr_low_alias, *lcd, *platreg; MemoryRegion *sys_mem = get_system_memory(); XilinxPCIEHost *pcie2; PCIDevice *ahci; DriveInfo *hd[6]; Chardev *chr; int fw_size, fit_err; bool is_64b; if ((machine->ram_size % GiB) || (machine->ram_size > (2 * GiB))) { error_report("Memory size must be 1GB or 2GB"); exit(1); } dev = qdev_create(NULL, TYPE_MIPS_BOSTON); qdev_init_nofail(dev); s = BOSTON(dev); s->mach = machine; if (!cpu_supports_cps_smp(machine->cpu_type)) { error_report("Boston requires CPUs which support CPS"); exit(1); } is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64); sysbus_init_child_obj(OBJECT(machine), "cps", OBJECT(&s->cps), sizeof(s->cps), TYPE_MIPS_CPS); object_property_set_str(OBJECT(&s->cps), machine->cpu_type, "cpu-type", &err); object_property_set_int(OBJECT(&s->cps), smp_cpus, "num-vp", &err); object_property_set_bool(OBJECT(&s->cps), true, "realized", &err); if (err != NULL) { error_report("%s", error_get_pretty(err)); exit(1); } sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); flash = g_new(MemoryRegion, 1); memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, &err); memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0); ddr = g_new(MemoryRegion, 1); memory_region_allocate_system_memory(ddr, NULL, "boston.ddr", machine->ram_size); memory_region_add_subregion_overlap(sys_mem, 0x80000000, ddr, 0); ddr_low_alias = g_new(MemoryRegion, 1); memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", ddr, 0, MIN(machine->ram_size, (256 * MiB))); memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); xilinx_pcie_init(sys_mem, 0, 0x10000000, 32 * MiB, 0x40000000, 1 * GiB, get_cps_irq(&s->cps, 2), false); xilinx_pcie_init(sys_mem, 1, 0x12000000, 32 * MiB, 0x20000000, 512 * MiB, get_cps_irq(&s->cps, 1), false); pcie2 = xilinx_pcie_init(sys_mem, 2, 0x14000000, 32 * MiB, 0x16000000, 1 * MiB, get_cps_irq(&s->cps, 0), true); platreg = g_new(MemoryRegion, 1); memory_region_init_io(platreg, NULL, &boston_platreg_ops, s, "boston-platregs", 0x1000); memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0); s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2, get_cps_irq(&s->cps, 3), 10000000, serial_hd(0), DEVICE_NATIVE_ENDIAN); lcd = g_new(MemoryRegion, 1); memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8); memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0); chr = qemu_chr_new("lcd", "vc:320x240", NULL); qemu_chr_fe_init(&s->lcd_display, chr, NULL); qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL, boston_lcd_event, NULL, s, NULL, true); ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, PCI_DEVFN(0, 0), true, TYPE_ICH9_AHCI); g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(ahci)); ide_drive_get(hd, ahci_get_num_ports(ahci)); ahci_ide_create_devs(ahci, hd); if (machine->firmware) { fw_size = load_image_targphys(machine->firmware, 0x1fc00000, 4 * MiB); if (fw_size == -1) { error_report("unable to load firmware image '%s'", machine->firmware); exit(1); } } else if (machine->kernel_filename) { fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s); if (fit_err) { error_report("unable to load FIT image"); exit(1); } gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000, s->kernel_entry, s->fdt_base, is_64b); } else if (!qtest_enabled()) { error_report("Please provide either a -kernel or -bios argument"); exit(1); } }
/* APIC */ unsigned long acpi_fill_madt(unsigned long current) { unsigned long apic_addr; device_t dev; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); /* Write NVIDIA CK804 IOAPIC. */ dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); if (dev) { apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, apic_addr, 0); /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) { u32 dword; dword = 0x0120d218; pci_write_config32(dev, 0x7c, dword); dword = 0x12008a00; pci_write_config32(dev, 0x80, dword); dword = 0x00080d7d; pci_write_config32(dev, 0x84, dword); } #endif } /* Write AMD 8131 two IOAPICs. */ dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); if (dev) { apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 5, apic_addr, 0x18); } dev = dev_find_slot(0x40, PCI_DEVFN(0x1, 1)); if (dev) { apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 6, apic_addr, 0x1C); } /* Write second NVIDIA CK804 IOAPIC. */ dev = dev_find_slot(0x80, PCI_DEVFN(0x1, 0)); if (dev) { apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 7, apic_addr, 0x20); /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) { u32 dword; dword = 0x0000d218; // Why does the factory BIOS have 0? pci_write_config32(dev, 0x7c, dword); dword = 0x00000000; pci_write_config32(dev, 0x80, dword); dword = 0x00000d00; // Same here. pci_write_config32(dev, 0x84, dword); } #endif } /* IRQ9 */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW); /* IRQ0 -> APIC IRQ2. */ /* Doesn't work on this board. */ /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ /* 5 mean: 0101 --> Edge-triggered, Active high */ /* create all subtables for processors */ /* acpi_create_madt_lapic_nmis returns current, not size. */ current = acpi_create_madt_lapic_nmis(current, 5, 1); return current; }
static int __devinit agp_serverworks_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { struct agp_bridge_data *bridge; struct pci_dev *bridge_dev; u32 temp, temp2; u8 cap_ptr = 0; cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); switch (pdev->device) { case 0x0006: dev_err(&pdev->dev, "ServerWorks CNB20HE is unsupported due to lack of documentation\n"); return -ENODEV; case PCI_DEVICE_ID_SERVERWORKS_HE: case PCI_DEVICE_ID_SERVERWORKS_LE: case 0x0007: break; default: if (cap_ptr) dev_err(&pdev->dev, "unsupported Serverworks chipset " "[%04x/%04x]\n", pdev->vendor, pdev->device); return -ENODEV; } /* Everything is on func 1 here so we are hardcoding function one */ bridge_dev = pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 1)); if (!bridge_dev) { dev_info(&pdev->dev, "can't find secondary device\n"); return -ENODEV; } serverworks_private.svrwrks_dev = bridge_dev; serverworks_private.gart_addr_ofs = 0x10; pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp); if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) { pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2); if (temp2 != 0) { dev_info(&pdev->dev, "64 bit aperture address, " "but top bits are not zero; disabling AGP\n"); return -ENODEV; } serverworks_private.mm_addr_ofs = 0x18; } else serverworks_private.mm_addr_ofs = 0x14; pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp); if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) { pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs + 4, &temp2); if (temp2 != 0) { dev_info(&pdev->dev, "64 bit MMIO address, but top " "bits are not zero; disabling AGP\n"); return -ENODEV; } } bridge = agp_alloc_bridge(); if (!bridge) return -ENOMEM; bridge->driver = &sworks_driver; bridge->dev_private_data = &serverworks_private, bridge->dev = pci_dev_get(pdev); pci_set_drvdata(pdev, bridge); return agp_add_bridge(bridge); }
device_t get_node_pci(u32 nodeid, u32 fn) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); }