void
RegAlloc::reset() {
TRACE(1, ">>> regalloc reset! <<<\n");
m_epoch = 0;
m_contToRegMap.clear();
// m_info is sparse.
for (int i = 0; i < kMaxRegs; ++i) {
m_info[i].m_epoch = 0;
m_info[i].m_pReg = PhysReg(i);
m_info[i].m_cont = RegContent();
m_info[i].m_type = KindOfInvalid;
m_info[i].m_state = RegInfo::INVALID;
}
RegSet all = m_allRegs;
PhysReg pr;
for (int i = 0; all.findFirst(pr); i++) {
all.remove(pr);
physRegToInfo(pr)->m_pReg = PhysReg(pr);
stateTransition(physRegToInfo(pr), RegInfo::FREE);
// Put the most favorable register last, so it is picked first.
m_lru[(m_numRegs - 1) - i] = pr;
}
m_branchSynced = false;
verify();
}
void LinearScan::allocRegToTmp(RegState* reg, SSATmp* ssaTmp, uint32_t index) {
reg->m_ssaTmp = ssaTmp;
// mark inst as using this register
ssaTmp->setReg(PhysReg(reg->m_regNo), index);
uint32_t lastUseId = ssaTmp->getLastUseId();
if (reg->isReserved()) {
return;
}
// insert into the list of assigned registers sorted by last use id
std::list<RegState*>::iterator it = m_allocatedRegs.begin();
for (; it != m_allocatedRegs.end(); ++it) {
if (lastUseId > (*it)->m_ssaTmp->getLastUseId()) {
break;
}
}
reg->m_pos = m_allocatedRegs.insert(it, reg);
}
PhysReg rarg_ind_ret(size_t i) {
assertx(i < num_arg_regs_ind_ret());
return PhysReg();
}