void CPU::op_write(uint32 addr, uint8 data) { alu_edge(); status.clock_count = speed(addr); dma_edge(); add_clocks(status.clock_count); bus.write(addr, regs.mdr = data); debugger.op_write(addr, regs.mdr); }
uint8 CPU::op_read(uint32 addr) { status.clock_count = speed(addr); dma_edge(); add_clocks(status.clock_count - 4); regs.mdr = bus.read(addr); add_clocks(4); alu_edge(); debugger.op_read(addr, regs.mdr); return regs.mdr; }
void CPU::dma_run() { add_clocks(8); dma_edge(); for(unsigned i = 0; i < 8; i++) { if(channel[i].dma_enabled == false) continue; add_clocks(8); dma_edge(); unsigned index = 0; do { dma_transfer(channel[i].direction, dma_bbus(i, index++), dma_addr(i)); dma_edge(); } while(channel[i].dma_enabled && --channel[i].transfer_size); channel[i].dma_enabled = false; } status.irq_lock = true; }
void CPU::op_io() { status.clock_count = 6; dma_edge(); add_clocks(6); alu_edge(); }