void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sch4037_early_init (CONFIG_SIO_PORT); /* Detect SMSC SIO1036 LPC Debug Card status */ if (detect_sio1036_chip(0x4E)) { /* Found SMSC SIO1036 LPC Debug Card */ sio1036_early_init(0x4E); } post_code(0x31); uart_init(); console_init(); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. */ sr56x0_rd890_disable_pcie_bridge(); } post_code(0x32); val = agesawrapper_amdinitmmio(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitmmio passed\n"); } /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); if(boot_cpu()) { post_code(0x34); sb_Poweron_Init(); } post_code(0x35); val = agesawrapper_amdinitreset(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n"); } post_code(0x36); val = agesawrapper_amdinitearly (); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n"); } post_code(0x37); nb_Poweron_Init(); post_code(0x38); nb_Ht_Init(); post_code(0x39); val = agesawrapper_amdinitpost (); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); } post_code(0x40); val = agesawrapper_amdinitenv (); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n"); } /* Initialize i8259 pic */ post_code(0x41); setup_i8259 (); /* Initialize i8254 timers */ post_code(0x42); setup_i8254 (); post_code(0x43); print_debug("Disabling cache as ram "); disable_cache_as_ram(); print_debug("done\n"); post_code(0x44); copy_and_run(0); post_code(0x45); // Should never see this post code. }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* Must come first to enable PCI MMCONF. */ amd_initmmio(); post_code(0x31); /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ wpcm450_enable_dev(WPCM450_SP1, 0x164E, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); post_code(0x34); post_code(0x35); console_init(); val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. */ sr56x0_rd890_disable_pcie_bridge(); post_code(0x39); nb_Poweron_Init(); post_code(0x3A); sb_Poweron_Init(); } post_code(0x3B); agesawrapper_amdinitearly(); post_code(0x3C); nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ if (!warm_reset_detect(0)) { printk(BIOS_INFO, "...WARM RESET...\n\n\n"); distinguish_cpu_resets(0); soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } post_code(0x40); agesawrapper_amdinitpost(); post_code(0x41); agesawrapper_amdinitenv(); post_code(0x42); post_code(0x50); printk(BIOS_DEBUG, "Disabling cache as RAM "); disable_cache_as_ram(); printk(BIOS_DEBUG, "done\n"); post_code(0x51); copy_and_run(); /* We will not return, Should never see this message and post code. */ printk(BIOS_DEBUG, "should not be here -\n"); post_code(0x54); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; post_code(0x30); agesawrapper_amdinitmmio(); post_code(0x31); /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ wpcm450_enable_dev(WPCM450_SP1, SIO_PORT, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); post_code(0x34); post_code(0x35); console_init(); val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x37); val = agesawrapper_amdinitreset(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n"); } if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. */ sr56x0_rd890_disable_pcie_bridge(); post_code(0x39); nb_Poweron_Init(); post_code(0x3A); sb_Poweron_Init(); } post_code(0x3B); val = agesawrapper_amdinitearly(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n"); } post_code(0x3C); /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. * In order to access W83795G/ADG HWM using I2C protocol, * we select function to SDA, SCL function (or GP33, GP32 function). */ w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); distinguish_cpu_resets(0); soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } post_code(0x40); val = agesawrapper_amdinitpost(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); } post_code(0x41); val = agesawrapper_amdinitenv(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n"); post_code(0x42); post_code(0x50); print_debug("Disabling cache as ram "); disable_cache_as_ram(); print_debug("done\n"); post_code(0x51); copy_and_run(); /* We will not return, Should never see this message and post code. */ print_debug("should not be here -\n"); post_code(0x54); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sch4037_early_init(0x2e); sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); post_code(0x31); console_init(); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. */ sr56x0_rd890_disable_pcie_bridge(); } /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); if(boot_cpu()) { post_code(0x34); sb_Poweron_Init(); } post_code(0x35); agesawrapper_amdinitreset(); post_code(0x36); agesawrapper_amdinitearly(); post_code(0x37); nb_Poweron_Init(); post_code(0x38); nb_Ht_Init(); post_code(0x39); agesawrapper_amdinitpost(); post_code(0x40); agesawrapper_amdinitenv(); post_code(0x43); printk(BIOS_DEBUG, "Disabling cache as ram "); disable_cache_as_ram(); printk(BIOS_DEBUG, "done\n"); post_code(0x44); copy_and_run(); post_code(0x45); // Should never see this post code. }