static int hiusb_ohci_start(struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci(hcd); int ret; ohci_dbg(ohci, "hiusb_ohci_start, ohci:%p", ohci); ret = ohci_init(ohci); if (ret < 0) return ret; ret = ohci_run(ohci); if (ret < 0) { pr_debug("can't start %s", hcd->self.bus_name); ohci_stop(hcd); return ret; } return 0; }
static int ohci_ppc_of_start(struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci(hcd); int ret; if ((ret = ohci_init(ohci)) < 0) return ret; if ((ret = ohci_run(ohci)) < 0) { dev_err(hcd->self.controller, "can't start %s\n", hcd->self.bus_name); ohci_stop(hcd); return ret; } return 0; }
static int __devinit str9100_ohci_start(struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci(hcd); int ret; //ohci->regs = hcd->regs; //ohci->fminterval = 0x27782edf; if ((ret = ohci_init(ohci)) < 0) return ret; if ((ret = ohci_run(ohci)) < 0) { err("can't start %s", ohci_to_hcd(ohci)->self.bus_name); ohci_stop(hcd); return ret; } return 0; }
static int ohci_s3c2410_start(struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci(hcd); int ret; ret = ohci_init(ohci); if (ret < 0) return ret; ret = ohci_run(ohci); if (ret < 0) { err("can't start %s", hcd->self.bus_name); ohci_stop(hcd); return ret; } return 0; }
static int __devinit ohci_pxa27x_start (struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci (hcd); int ret; ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci); if ((ret = ohci_init(ohci)) < 0) return ret; if ((ret = ohci_run (ohci)) < 0) { err ("can't start %s", ohci->hcd.self.bus_name); ohci_stop (hcd); return ret; } return 0; }
static int __devinit ohci_rtgalaxy_start(struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci(hcd); int ret; ret = ohci_init(ohci); if (ret < 0) return ret; ret = ohci_run(ohci); if (ret < 0) { ohci_err(ohci, "can't start %s", hcd->self.bus_name); ohci_stop(hcd); return ret; } return 0; }
static int __devinit ohci_at91_start (struct usb_hcd *hcd) { struct at91_usbh_data *board = hcd->self.controller->platform_data; struct ohci_hcd *ohci = hcd_to_ohci (hcd); int ret; if ((ret = ohci_init(ohci)) < 0) return ret; ohci->num_ports = board->ports; if ((ret = ohci_run(ohci)) < 0) { err("can't start %s", hcd->self.bus_name); ohci_stop(hcd); return ret; } return 0; }
static int ohci_jz4740_start(struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci(hcd); int ret; ret = ohci_init(ohci); if (ret < 0) return ret; ohci->num_ports = 1; ret = ohci_run(ohci); if (ret < 0) { dev_err(hcd->self.controller, "Can not start %s", hcd->self.bus_name); ohci_stop(hcd); return ret; } return 0; }
static int __devinit ps3_ohci_hc_start(struct usb_hcd *hcd) { int result; struct ohci_hcd *ohci = hcd_to_ohci(hcd); ohci_writel(ohci, 0x7f000000 | RH_A_PSM | RH_A_OCPM, &ohci->regs->roothub.a); ohci_writel(ohci, 0x00060000, &ohci->regs->roothub.b); result = ohci_run(ohci); if (result < 0) { err("can't start %s", hcd->self.bus_name); ohci_stop(hcd); } return result; }
static int __devinit ohci_bcm63xx_start(struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci(hcd); int ret; ohci->num_ports = 1; ret = ohci_init(ohci); if (ret < 0) return ret; /* FIXME: autodetected port 2 is shared with USB slave */ ret = ohci_run(ohci); if (ret < 0) { err("can't start %s", hcd->self.bus_name); ohci_stop(hcd); return ret; } return 0; }
static int __devinit ps3_ohci_hc_start(struct usb_hcd *hcd) { int result; struct ohci_hcd *ohci = hcd_to_ohci(hcd); /* Handle root hub init quirk in spider south bridge. */ /* Also set PwrOn2PwrGood to 0x7f (254ms). */ ohci_writel(ohci, 0x7f000000 | RH_A_PSM | RH_A_OCPM, &ohci->regs->roothub.a); ohci_writel(ohci, 0x00060000, &ohci->regs->roothub.b); result = ohci_run(ohci); if (result < 0) { err("can't start %s", hcd->self.bus_name); ohci_stop(hcd); } return result; }
static int ohci_omap3_start(struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci(hcd); int ret; /* * RemoteWakeupConnected has to be set explicitly before * calling ohci_run. The reset value of RWC is 0. */ ohci->hc_control = OHCI_CTRL_RWC; writel(OHCI_CTRL_RWC, &ohci->regs->control); ret = ohci_run(ohci); if (ret < 0) { dev_err(hcd->self.controller, "can't start\n"); ohci_stop(hcd); } return ret; }
static int __devinit ohci_omap_start (struct usb_hcd *hcd) { struct omap_usb_config *config; struct ohci_hcd *ohci = hcd_to_ohci (hcd); int ret; if ((ret = ohci_init(ohci)) < 0) return ret; config = hcd->self.controller->platform_data; if (config->otg || config->rwc) writel(OHCI_CTRL_RWC, &ohci->regs->control); if ((ret = ohci_run (ohci)) < 0) { err ("can't start %s", ohci->hcd.self.bus_name); ohci_stop (hcd); return ret; } return 0; }
static int ohci_imapx200_start(struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci(hcd); int ret; IMAP_OHCI_DEBUG("++ohci_imapx200_start \r\n"); if((ret = ohci_init(ohci))<0) { return ret; } IMAP_OHCI_DEBUG("++ohci_init success \r\n"); if((ret = ohci_run(ohci)) < 0) { err("ohci can't start %s",hcd->self.bus_name); ohci_stop(hcd); return ret; } IMAP_OHCI_DEBUG("--ohci_imapx200_start \r\n"); return 0; }
static int __devinit ohci_pxa27x_start (struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci (hcd); int ret; ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci); /* The value of NDP in roothub_a is incorrect on this hardware */ ohci->num_ports = 3; if ((ret = ohci_init(ohci)) < 0) return ret; if ((ret = ohci_run (ohci)) < 0) { err ("can't start %s", hcd->self.bus_name); ohci_stop (hcd); return ret; } return 0; }
static int ohci_omap_start (struct usb_hcd *hcd) { struct omap_usb_config *config; struct ohci_hcd *ohci = hcd_to_ohci (hcd); int ret; if (!host_enabled) return 0; config = hcd->self.controller->platform_data; if (config->otg || config->rwc) { ohci->hc_control = OHCI_CTRL_RWC; writel(OHCI_CTRL_RWC, &ohci->regs->control); } if ((ret = ohci_run (ohci)) < 0) { dev_err(hcd->self.controller, "can't start\n"); ohci_stop (hcd); return ret; } return 0; }
static int __devinit ohci_rtl8652_start(struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci(hcd); int ret; unsigned int fminterval; if ((ret = ohci_init(ohci)) < 0) return ret; fminterval = 0x2edf; ohci_writel (ohci,(fminterval * 9) / 10, &ohci->regs->periodicstart); fminterval |= ((((fminterval - 210) * 6) / 7) << 16); ohci_writel (ohci,fminterval, &ohci->regs->fminterval); ohci_writel (ohci,0x628, &ohci->regs->lsthresh); ohci_writel(ohci,0x3e67,&ohci->regs->periodicstart); if ((ret = ohci_run(ohci)) < 0) { err("can't start %s", hcd->self.bus_name); ohci_stop(hcd); return ret; } return 0; }
static int __devinit ohci_spmp_start(struct usb_hcd *hcd) { // #define FSMP_NEW(fi) (0x7fff & ((6 * ((fi) - 210)) / 7)) // modify by eddie 20110217 FSMP shoule have 15 valid bit, but hardware only support 13 bit. // #define FSMP_NEW(fi) (0x7fff & (((6 * ((fi) - 210)) / 7))>>2) #define FSMP_NEW(fi) 2441 struct ohci_hcd *ohci = hcd_to_ohci(hcd); int ret; u32 temp; ohci_dbg(ohci, "ohci_spmp_start, ohci:%p", ohci); /* The value of NDP in roothub_a is incorrect on this hardware */ ohci->num_ports = 2; if ((ret = ohci_init(ohci)) < 0) return ret; temp = ohci_readl (ohci, &ohci->regs->fminterval); ohci->fminterval = temp & 0x7fff; if (ohci->fminterval != FI) { ohci_dbg(ohci, "fminterval delta %d\n", ohci->fminterval - FI); } ohci->fminterval |= FSMP_NEW (ohci->fminterval) << 16; /* also: power/overcurrent flags in roothub.a */ if ((ret = ohci_run(ohci)) < 0) { err ("can't start %s", hcd->self.bus_name); ohci_stop(hcd); return ret; } return 0; }
static int __devinit cns3xxx_ohci_start(struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci(hcd); int ret; /* */ if (atomic_inc_return(&usb_pwr_ref) == 1) { cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), MISC_CHIP_CONFIG_REG); } ret = ohci_init(ohci); if (ret < 0) return ret; ohci->num_ports = 1; ret = ohci_run(ohci); if (ret < 0) { err("can't start %s", hcd->self.bus_name); ohci_stop(hcd); return ret; } return 0; }
static int __devinit ohci_spear_start(struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci(hcd); int ret; ret = ohci_init(ohci); if (ret < 0) return ret; ohci->regs = hcd->regs; ret = ohci_run(ohci); if (ret < 0) { dev_err(hcd->self.controller, "can't start\n"); ohci_stop(hcd); return ret; } create_debug_files(ohci); #ifdef DEBUG ohci_dump(ohci, 1); #endif return 0; }
static int __devinit cns3xxx_ohci_start(struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci(hcd); int ret; /* * EHCI and OHCI share the same clock and power, * resetting twice would cause the 1st controller been reset. * Therefore only do power up at the first up device, and * power down at the last down device. * * Set USB AHB INCR length to 16 */ if (atomic_inc_return(&usb_pwr_ref) == 1) { cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), MISC_CHIP_CONFIG_REG); } ret = ohci_init(ohci); if (ret < 0) return ret; ohci->num_ports = 1; ret = ohci_run(ohci); if (ret < 0) { err("can't start %s", hcd->self.bus_name); ohci_stop(hcd); return ret; } return 0; }
static int __devinit ohci_pci_start (struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci (hcd); int ret; if(hcd->self.controller && hcd->self.controller->bus == &pci_bus_type) { struct pci_dev *pdev = to_pci_dev(hcd->self.controller); /* AMD 756, for most chips (early revs), corrupts register * values on read ... so enable the vendor workaround. */ if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x740c) { ohci->flags = OHCI_QUIRK_AMD756; ohci_dbg (ohci, "AMD756 erratum 4 workaround\n"); // also somewhat erratum 10 (suspend/resume issues) } /* FIXME for some of the early AMD 760 southbridges, OHCI * won't work at all. blacklist them. */ /* Apple's OHCI driver has a lot of bizarre workarounds * for this chip. Evidently control and bulk lists * can get confused. (B&W G3 models, and ...) */ else if (pdev->vendor == PCI_VENDOR_ID_OPTI && pdev->device == 0xc861) { ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n"); } /* Check for NSC87560. We have to look at the bridge (fn1) to * identify the USB (fn2). This quirk might apply to more or * even all NSC stuff. */ else if (pdev->vendor == PCI_VENDOR_ID_NS) { struct pci_dev *b; b = pci_find_slot (pdev->bus->number, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1)); if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO && b->vendor == PCI_VENDOR_ID_NS) { ohci->flags |= OHCI_QUIRK_SUPERIO; ohci_dbg (ohci, "Using NSC SuperIO setup\n"); } } /* Check for Compaq's ZFMicro chipset, which needs short * delays before control or bulk queues get re-activated * in finish_unlinks() */ else if (pdev->vendor == PCI_VENDOR_ID_COMPAQ && pdev->device == 0xa0f8) { ohci->flags |= OHCI_QUIRK_ZFMICRO; ohci_dbg (ohci, "enabled Compaq ZFMicro chipset quirk\n"); } } /* NOTE: there may have already been a first reset, to * keep bios/smm irqs from making trouble */ if ((ret = ohci_run (ohci)) < 0) { ohci_err (ohci, "can't start\n"); ohci_stop (hcd); return ret; } return 0; }
static int __devinit ohci_pci_start (struct usb_hcd *hcd) { struct ohci_hcd *ohci = hcd_to_ohci (hcd); int ret; /* REVISIT this whole block should move to reset(), which handles * all the other one-time init. */ if (hcd->self.controller) { struct pci_dev *pdev = to_pci_dev(hcd->self.controller); /* AMD 756, for most chips (early revs), corrupts register * values on read ... so enable the vendor workaround. */ if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x740c) { ohci->flags = OHCI_QUIRK_AMD756; ohci_dbg (ohci, "AMD756 erratum 4 workaround\n"); /* also erratum 10 (suspend/resume issues) */ device_init_wakeup(&hcd->self.root_hub->dev, 0); } /* FIXME for some of the early AMD 760 southbridges, OHCI * won't work at all. blacklist them. */ /* Apple's OHCI driver has a lot of bizarre workarounds * for this chip. Evidently control and bulk lists * can get confused. (B&W G3 models, and ...) */ else if (pdev->vendor == PCI_VENDOR_ID_OPTI && pdev->device == 0xc861) { ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n"); } /* Check for NSC87560. We have to look at the bridge (fn1) to * identify the USB (fn2). This quirk might apply to more or * even all NSC stuff. */ else if (pdev->vendor == PCI_VENDOR_ID_NS) { struct pci_dev *b; b = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1)); if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO && b->vendor == PCI_VENDOR_ID_NS) { ohci->flags |= OHCI_QUIRK_SUPERIO; ohci_dbg (ohci, "Using NSC SuperIO setup\n"); } pci_dev_put(b); } /* Check for Compaq's ZFMicro chipset, which needs short * delays before control or bulk queues get re-activated * in finish_unlinks() */ else if (pdev->vendor == PCI_VENDOR_ID_COMPAQ && pdev->device == 0xa0f8) { ohci->flags |= OHCI_QUIRK_ZFMICRO; ohci_dbg (ohci, "enabled Compaq ZFMicro chipset quirk\n"); } /* RWC may not be set for add-in PCI cards, since boot * firmware probably ignored them. This transfers PCI * PM wakeup capabilities (once the PCI layer is fixed). */ if (device_may_wakeup(&pdev->dev)) ohci->hc_control |= OHCI_CTRL_RWC; } /* NOTE: there may have already been a first reset, to * keep bios/smm irqs from making trouble */ if ((ret = ohci_run (ohci)) < 0) { ohci_err (ohci, "can't start\n"); ohci_stop (hcd); return ret; } return 0; }