int pwm_set_backlight(int bl_lvl, struct k3_panel_info *pinfo)
{
int ret = 0;
int i = 0;
u32 brightness = 0;
volatile u32 base = IO_ADDRESS(pinfo->pwm_base);
BUG_ON(pinfo == NULL);
mutex_lock(&k3led_backlight_lock);
brightness = (bl_lvl * PWM_MAX_DIV) / pinfo->bl_max;
if (brightness >= PWM_MAX_DIV) {
brightness = PWM_MAX_DIV -1;
}
if (!bklclk_cnt++) {
ret = clk_enable(pinfo->pwm_clk);
#if defined(CONFIG_LCD_PANASONIC_VVX10F002A00)
msleep(90);
#endif
if (ret != 0) {
k3fb_loge("backlight failed to enable pwm_clk!\n");
mutex_unlock(&k3led_backlight_lock);
return ret;
}
}
if (brightness == 0) {
outp32(base + PWM_OUT_OFFSET, brightness);
outp32(base, BACKLIGHT_DISABLE);
msleep(20);
clk_disable(pinfo->pwm_clk);
bklclk_cnt = 0;
} else {
/*wait for display on*/
for (i = 0; i < WAIT_NUMBER; i++) {
if (pinfo->display_on == false) {
msleep(WAIT_TIMERLEN);
continue;
} else {
break;
}
}
if (i >= WAIT_NUMBER) {
k3fb_loge("backlight is time out!\n");
}
outp32(base, BACKLIGHT_ENABLE);
outp32(base + PWM_DIV_OFFSET, PWM_MAX_DIV);
if (brightness_old < brightness) {
for (i = brightness_old + 1; i <= brightness; i++) {
udelay(50);
outp32(base + PWM_OUT_OFFSET, i);
}
} else {
for (i = brightness_old - 1; i >= brightness; i--) {
udelay(50);
outp32(base + PWM_OUT_OFFSET, i);
}
}
}
brightness_old = brightness;
mutex_unlock(&k3led_backlight_lock);
return 0;
}
void mdp_hw_init(int cont_splash)
{
int i;
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
/* debug interface write access */
outpdw(MDP_BASE + 0x60, 1);
outp32(MDP_INTR_ENABLE, MDP_ANY_INTR_MASK);
outp32(MDP_EBI2_PORTMAP_MODE, 0x3);
outpdw(MDP_CMD_DEBUG_ACCESS_BASE + 0x01f8, 0x0);
outpdw(MDP_CMD_DEBUG_ACCESS_BASE + 0x01fc, 0x0);
outpdw(MDP_BASE + 0x60, 0x1);
mdp_load_lut_param();
/*
* clear up unused fg/main registers
*/
/* comp.plane 2&3 ystride */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0120, 0x0);
/* unpacked pattern */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x012c, 0x0);
/* unpacked pattern */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0130, 0x0);
/* unpacked pattern */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0134, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0158, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x15c, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0160, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0170, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0174, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x017c, 0x0);
/* comp.plane 2 */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0114, 0x0);
/* comp.plane 3 */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0118, 0x0);
/* clear up unused bg registers */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01c8, 0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01d0, 0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01dc, 0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01e0, 0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01e4, 0);
#ifndef CONFIG_FB_MSM_MDP22
/* Make sure to disable TG if continuous splash screen
* is not enabled on kernel side. This avoids issues
* when multiple panels are supported on same board
* and all the panels do not have splash screen/continuous
* splash support on the boot loader side.
*/
if (!cont_splash) {
MDP_OUTP(MDP_BASE + 0xE0000, 0);
msleep(20);
MDP_OUTP(MDP_BASE + 0xF0000, 0);
msleep(20);
}
MDP_OUTP(MDP_BASE + 0x100, 0xffffffff);
MDP_OUTP(MDP_BASE + 0x90070, 0);
#endif
/*
* limit vector
* pre gets applied before color matrix conversion
* post is after ccs
*/
writel(mdp_plv[0], MDP_CSC_PRE_LV1n(0));
writel(mdp_plv[1], MDP_CSC_PRE_LV1n(1));
writel(mdp_plv[2], MDP_CSC_PRE_LV1n(2));
writel(mdp_plv[3], MDP_CSC_PRE_LV1n(3));
#ifdef CONFIG_FB_MSM_MDP31
writel(mdp_plv[2], MDP_CSC_PRE_LV1n(4));
writel(mdp_plv[3], MDP_CSC_PRE_LV1n(5));
writel(0, MDP_CSC_POST_LV1n(0));
writel(0xff, MDP_CSC_POST_LV1n(1));
writel(0, MDP_CSC_POST_LV1n(2));
writel(0xff, MDP_CSC_POST_LV1n(3));
writel(0, MDP_CSC_POST_LV1n(4));
writel(0xff, MDP_CSC_POST_LV1n(5));
writel(0, MDP_CSC_PRE_LV2n(0));
writel(0xff, MDP_CSC_PRE_LV2n(1));
writel(0, MDP_CSC_PRE_LV2n(2));
writel(0xff, MDP_CSC_PRE_LV2n(3));
writel(0, MDP_CSC_PRE_LV2n(4));
writel(0xff, MDP_CSC_PRE_LV2n(5));
writel(mdp_plv[0], MDP_CSC_POST_LV2n(0));
writel(mdp_plv[1], MDP_CSC_POST_LV2n(1));
writel(mdp_plv[2], MDP_CSC_POST_LV2n(2));
writel(mdp_plv[3], MDP_CSC_POST_LV2n(3));
writel(mdp_plv[2], MDP_CSC_POST_LV2n(4));
writel(mdp_plv[3], MDP_CSC_POST_LV2n(5));
#endif
/* primary forward matrix */
for (i = 0; i < MDP_CCS_SIZE; i++)
writel(mdp_ccs_rgb2yuv.ccs[i], MDP_CSC_PFMVn(i));
#ifdef CONFIG_FB_MSM_MDP31
for (i = 0; i < MDP_BV_SIZE; i++)
writel(mdp_ccs_rgb2yuv.bv[i], MDP_CSC_POST_BV2n(i));
writel(0, MDP_CSC_PRE_BV2n(0));
writel(0, MDP_CSC_PRE_BV2n(1));
writel(0, MDP_CSC_PRE_BV2n(2));
#endif
/* primary reverse matrix */
for (i = 0; i < MDP_CCS_SIZE; i++)
writel(mdp_ccs_yuv2rgb.ccs[i], MDP_CSC_PRMVn(i));
for (i = 0; i < MDP_BV_SIZE; i++)
writel(mdp_ccs_yuv2rgb.bv[i], MDP_CSC_PRE_BV1n(i));
#ifdef CONFIG_FB_MSM_MDP31
writel(0, MDP_CSC_POST_BV1n(0));
writel(0, MDP_CSC_POST_BV1n(1));
writel(0, MDP_CSC_POST_BV1n(2));
outpdw(MDP_BASE + 0x30010, 0x03e0);
outpdw(MDP_BASE + 0x30014, 0x0360);
outpdw(MDP_BASE + 0x30018, 0x0120);
outpdw(MDP_BASE + 0x3001c, 0x0140);
#endif
mdp_init_scale_table();
#ifndef CONFIG_FB_MSM_MDP31
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0104,
((16 << 6) << 16) | (16) << 6);
#endif
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
void offline_dump_fail_reg(char __iomem *dss_base, dss_overlay_t *req, long timestamp)
{
char filename[128] = {0};
u32 i = 0;
char * str_line = NULL;
u32 len = 0;
BUG_ON(dss_base == NULL);
BUG_ON(req == NULL);
snprintf(filename, sizeof(filename), "/data/hwcdump/offline_%ld_reg.txt", timestamp);
str_line = kmalloc(SZ_64K, GFP_KERNEL);
if(IS_ERR_OR_NULL(str_line)){
printk("offline_dump_fail_reg alloc buffer fail!\n");
return;
}
outp32(dss_base + 0x404, 0x0);
//GLB
len += snprintf(str_line + len, SZ_1K, "CLB reg:\n");
len += print_serial_reg(str_line, len, dss_base, 0x484, 0x484);
len += print_serial_reg(str_line, len, dss_base, 0x4c4, 0x4c4);
len += print_serial_reg(str_line, len, dss_base, 0x730, 0x758);
//ADP
len += snprintf(str_line + len, SZ_1K, "ADP reg:\n");
len += print_serial_reg(str_line, len, dss_base, 0x42530, 0x42538);
//RDMA BRG
len += snprintf(str_line + len, SZ_1K, "RDMA BRG reg:\n");
len += print_serial_reg(str_line, len, dss_base +
g_dss_module_eng_base[DSS_ENG_DPE2][MODULE_ENG_DMA_BRG], 0x1C, 0x2C);
len += print_serial_reg(str_line, len, dss_base +
g_dss_module_eng_base[DSS_ENG_DPE3][MODULE_ENG_DMA_BRG], 0x1C, 0x2C);
for(i = 0; i < req->layer_nums; i++){
int chn = req->layer_infos[i].chn_idx;
len += snprintf(str_line + len, SZ_1K, "layer:%d chn:%d\n", i, chn);
//RDMA
len += snprintf(str_line + len, SZ_1K, "RDMA reg:\n");
len += print_serial_reg(str_line, len, dss_base +
g_dss_module_base[chn][MODULE_DMA0], 0x04, 0x30);
if( isYUVSemiPlanar(req->layer_infos[i].src.format))
len += print_serial_reg(str_line, len, dss_base +
g_dss_module_base[chn][MODULE_DMA1], 0x04, 0x30);
if(isYUVPlanar(req->layer_infos[i].src.format))
len += print_serial_reg(str_line, len, dss_base +
g_dss_module_base[chn + 1][MODULE_DMA0], 0x04, 0x30);
//RDFC
len += snprintf(str_line + len, SZ_1K, "RDFC reg:\n");
len += print_serial_reg(str_line, len, dss_base +
g_dss_module_base[chn][MODULE_DFC], 0x0, 0x24);
//CSC
len += snprintf(str_line + len, SZ_1K, "CSC reg:\n");
len += print_serial_reg(str_line, len, dss_base +
g_dss_module_base[chn][MODULE_CSC], 0x1C, 0x1C);
//SCF
if(req->layer_infos[i].need_cap & CAP_SCL){
len += snprintf(str_line + len, SZ_1K, "SCF reg:\n");
len += print_serial_reg(str_line, len, dss_base +
g_dss_module_base[chn][MODULE_SCF], 0x10, 0x14);
}
}
//WDMA
len += snprintf(str_line + len, SZ_1K, "WDMA reg:\n");
if(WBE1_CHN0 == req->wb_layer_info.chn_idx){
len += print_serial_reg(str_line, len, dss_base +
g_dss_module_base[WBE1_CHN0][MODULE_DMA0], 0x04, 0x30);
len += snprintf(str_line + len, SZ_1K, "WDFC reg:\n");
len += print_serial_reg(str_line, len, dss_base +
g_dss_module_base[WBE1_CHN0][MODULE_DFC], 0x0, 0x24);
}else if(WBE1_CHN1 == req->wb_layer_info.chn_idx) {
len += print_serial_reg(str_line, len, dss_base +
g_dss_module_base[WBE1_CHN1][MODULE_DMA0], 0x04, 0x30);
len += snprintf(str_line + len, SZ_1K, "WDFC reg:\n");
len += print_serial_reg(str_line, len, dss_base +
g_dss_module_base[WBE1_CHN1][MODULE_DFC], 0x0, 0x24);
//CSC
len += snprintf(str_line + len, SZ_1K, "W_CSC reg:\n");
len += print_serial_reg(str_line, len, dss_base +
g_dss_module_base[WBE1_CHN1][MODULE_CSC], 0x1C, 0x1C);
len += snprintf(str_line + len, SZ_1K, "OV reg:\n");
len += print_serial_reg(str_line, len, dss_base +
g_dss_module_ovl_base[DSS_OVL_ADP][MODULE_OVL_BASE], 0x0, 0x150);
}
outp32(dss_base + 0x404, 0x2);
offline_save_bin_file(filename, str_line, len);
kfree(str_line);
return;
}
static int ebi2_lcd_probe(struct platform_device *pdev)
{
struct msm_fb_data_type *mfd;
struct platform_device *mdp_dev = NULL;
struct msm_fb_panel_data *pdata = NULL;
int rc, i;
if (pdev->id == 0) {
for (i = 0; i < pdev->num_resources; i++) {
if (!strncmp(pdev->resource[i].name, "base", 4)) {
ebi2_base = ioremap(pdev->resource[i].start,
pdev->resource[i].end -
pdev->resource[i].start + 1);
if (!ebi2_base) {
printk(KERN_ERR
"ebi2_base ioremap failed!\n");
return -ENOMEM;
}
ebi2_lcd_cfg0 = (void *)(ebi2_base + 0x20);
ebi2_lcd_cfg1 = (void *)(ebi2_base + 0x24);
} else if (!strncmp(pdev->resource[i].name,
"lcd01", 5)) {
lcd01_base = ioremap(pdev->resource[i].start,
pdev->resource[i].end -
pdev->resource[i].start + 1);
if (!lcd01_base) {
printk(KERN_ERR
"lcd01_base ioremap failed!\n");
return -ENOMEM;
}
} else if (!strncmp(pdev->resource[i].name,
"lcd02", 5)) {
lcd02_base = ioremap(pdev->resource[i].start,
pdev->resource[i].end -
pdev->resource[i].start + 1);
if (!lcd02_base) {
printk(KERN_ERR
"lcd02_base ioremap failed!\n");
return -ENOMEM;
}
}
}
ebi2_lcd_resource_initialized = 1;
return 0;
}
if (!ebi2_lcd_resource_initialized)
return -EPERM;
mfd = platform_get_drvdata(pdev);
if (!mfd)
return -ENODEV;
if (mfd->key != MFD_KEY)
return -EINVAL;
if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST)
return -ENOMEM;
if (ebi2_base == NULL)
return -ENOMEM;
mdp_dev = platform_device_alloc("mdp", pdev->id);
if (!mdp_dev)
return -ENOMEM;
/* link to the latest pdev */
mfd->pdev = mdp_dev;
mfd->dest = DISPLAY_LCD;
/* add panel data */
if (platform_device_add_data
(mdp_dev, pdev->dev.platform_data,
sizeof(struct msm_fb_panel_data))) {
printk(KERN_ERR "ebi2_lcd_probe: platform_device_add_data failed!\n");
platform_device_put(mdp_dev);
return -ENOMEM;
}
/* data chain */
pdata = mdp_dev->dev.platform_data;
pdata->on = panel_next_on;
pdata->off = panel_next_off;
pdata->next = pdev;
/* get/set panel specific fb info */
mfd->panel_info = pdata->panel_info;
if (mfd->panel_info.bpp == 24)
mfd->fb_imgType = MDP_RGB_888;
else
mfd->fb_imgType = MDP_RGB_565;
/* config msm ebi2 lcd register */
if (mfd->panel_info.pdest == DISPLAY_1) {
outp32(ebi2_base,
(inp32(ebi2_base) & (~(EBI2_PRIM_LCD_CLR))) |
EBI2_PRIM_LCD_SEL);
/*
* current design has one set of cfg0/1 register to control
* both EBI2 channels. so, we're using the PRIM channel to
* configure both.
*/
outp32(ebi2_lcd_cfg0, mfd->panel_info.wait_cycle);
if (mfd->panel_info.bpp == 18)
outp32(ebi2_lcd_cfg1, 0x01000000);
else
outp32(ebi2_lcd_cfg1, 0x0);
} else {
#ifdef DEBUG_EBI2_LCD
/*
* confliting with QCOM SURF FPGA CS.
* OEM should enable below for their CS mapping
*/
outp32(ebi2_base, (inp32(ebi2_base)&(~(EBI2_SECD_LCD_CLR)))
|EBI2_SECD_LCD_SEL);
#endif
}
/*
* map cs (chip select) address
*/
if (mfd->panel_info.pdest == DISPLAY_1) {
mfd->cmd_port = lcd01_base;
mfd->data_port =
(void *)((uint32) mfd->cmd_port + EBI2_PRIM_LCD_RS_PIN);
mfd->data_port_phys =
(void *)(LCD_PRIM_BASE_PHYS + EBI2_PRIM_LCD_RS_PIN);
} else {
mfd->cmd_port = lcd01_base;
mfd->data_port =
(void *)((uint32) mfd->cmd_port + EBI2_SECD_LCD_RS_PIN);
mfd->data_port_phys =
(void *)(LCD_SECD_BASE_PHYS + EBI2_SECD_LCD_RS_PIN);
}
/*
* set driver data
*/
platform_set_drvdata(mdp_dev, mfd);
/*
* register in mdp driver
*/
rc = platform_device_add(mdp_dev);
if (rc) {
goto ebi2_lcd_probe_err;
}
#if 0 /* FIXME: */
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
#endif
pdev_list[pdev_list_cnt++] = pdev;
return 0;
ebi2_lcd_probe_err:
platform_device_put(mdp_dev);
return rc;
}
static void mdp_dma2_update_lcd(struct msm_fb_data_type *mfd)
{
MDPIBUF *iBuf = &mfd->ibuf;
int mddi_dest = FALSE;
uint32 outBpp = iBuf->bpp;
uint32 dma2_cfg_reg;
uint8 *src;
uint32 mddi_ld_param;
uint16 mddi_vdo_packet_reg;
struct msm_fb_panel_data *pdata =
(struct msm_fb_panel_data *)mfd->pdev->dev.platform_data;
uint32 ystride = mfd->fbi->fix.line_length;
uint32 mddi_pkt_desc;
dma2_cfg_reg = DMA_PACK_ALIGN_LSB |
DMA_OUT_SEL_AHB | DMA_IBUF_NONCONTIGUOUS;
#ifdef CONFIG_FB_MSM_MDP22
dma2_cfg_reg |= DMA_PACK_TIGHT;
#endif
#ifdef CONFIG_FB_MSM_MDP30
if (iBuf->dma_w == 1) {
iBuf->dma_w = 2;
if (iBuf->dma_x == (iBuf->ibuf_width - 2))
iBuf->dma_x--;
}
#endif
if (mfd->fb_imgType == MDP_BGR_565)
dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
else if (mfd->fb_imgType == MDP_RGBA_8888)
dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
else
dma2_cfg_reg |= DMA_PACK_PATTERN_RGB;
if (outBpp == 4) {
dma2_cfg_reg |= DMA_IBUF_C3ALPHA_EN;
dma2_cfg_reg |= DMA_IBUF_FORMAT_xRGB8888_OR_ARGB8888;
}
if (outBpp == 2)
dma2_cfg_reg |= DMA_IBUF_FORMAT_RGB565;
mddi_ld_param = 0;
mddi_vdo_packet_reg = mfd->panel_info.mddi.vdopkt;
if ((mfd->panel_info.type == MDDI_PANEL) ||
(mfd->panel_info.type == EXT_MDDI_PANEL)) {
dma2_cfg_reg |= DMA_OUT_SEL_MDDI;
mddi_dest = TRUE;
if (mfd->panel_info.type == MDDI_PANEL) {
mdp_total_vdopkts++;
if (mfd->panel_info.pdest == DISPLAY_1) {
dma2_cfg_reg |= DMA_MDDI_DMAOUT_LCD_SEL_PRIMARY;
mddi_ld_param = 0;
#ifdef MDDI_HOST_WINDOW_WORKAROUND
mddi_window_adjust(mfd, iBuf->dma_x,
iBuf->dma_w - 1, iBuf->dma_y,
iBuf->dma_h - 1);
#endif
} else {
dma2_cfg_reg |=
DMA_MDDI_DMAOUT_LCD_SEL_SECONDARY;
mddi_ld_param = 1;
#ifdef MDDI_HOST_WINDOW_WORKAROUND
mddi_window_adjust(mfd, iBuf->dma_x,
iBuf->dma_w - 1, iBuf->dma_y,
iBuf->dma_h - 1);
#endif
}
} else {
dma2_cfg_reg |= DMA_MDDI_DMAOUT_LCD_SEL_EXTERNAL;
mddi_ld_param = 2;
}
} else {
if (mfd->panel_info.pdest == DISPLAY_1) {
dma2_cfg_reg |= DMA_AHBM_LCD_SEL_PRIMARY;
outp32(MDP_EBI2_LCD0, mfd->data_port_phys);
} else {
dma2_cfg_reg |= DMA_AHBM_LCD_SEL_SECONDARY;
outp32(MDP_EBI2_LCD1, mfd->data_port_phys);
}
}
dma2_cfg_reg |= DMA_DITHER_EN;
src = (uint8 *) iBuf->buf;
src += iBuf->dma_x * outBpp + iBuf->dma_y * ystride;
mdp_curr_dma2_update_width = iBuf->dma_w;
mdp_curr_dma2_update_height = iBuf->dma_h;
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
#ifdef CONFIG_FB_MSM_MDP22
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0184,
(iBuf->dma_h << 16 | iBuf->dma_w));
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0188, src);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x018C, ystride);
#else
MDP_OUTP(MDP_BASE + 0x90004, (iBuf->dma_h << 16 | iBuf->dma_w));
MDP_OUTP(MDP_BASE + 0x90008, src);
MDP_OUTP(MDP_BASE + 0x9000c, ystride);
#endif
if (mfd->panel_info.bpp == 18) {
mddi_pkt_desc = MDDI_VDO_PACKET_DESC;
dma2_cfg_reg |= DMA_DSTC0G_6BITS |
DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
} else if (mfd->panel_info.bpp == 24) {
mddi_pkt_desc = MDDI_VDO_PACKET_DESC_24;
dma2_cfg_reg |= DMA_DSTC0G_8BITS |
DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS;
} else {
mddi_pkt_desc = MDDI_VDO_PACKET_DESC_16;
dma2_cfg_reg |= DMA_DSTC0G_6BITS |
DMA_DSTC1B_5BITS | DMA_DSTC2R_5BITS;
}
if (mddi_dest) {
#ifdef CONFIG_FB_MSM_MDP22
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0194,
(iBuf->dma_y << 16) | iBuf->dma_x);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01a0, mddi_ld_param);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01a4,
(mddi_pkt_desc << 16) | mddi_vdo_packet_reg);
#else
MDP_OUTP(MDP_BASE + 0x90010, (iBuf->dma_y << 16) | iBuf->dma_x);
MDP_OUTP(MDP_BASE + 0x00090, mddi_ld_param);
MDP_OUTP(MDP_BASE + 0x00094,
(mddi_pkt_desc << 16) | mddi_vdo_packet_reg);
#endif
} else {
pdata->set_rect(iBuf->dma_x, iBuf->dma_y, iBuf->dma_w,
iBuf->dma_h);
}
#ifdef MDP_HW_VSYNC
MDP_OUTP(MDP_BASE + 0x90000, dma2_cfg_reg);
if ((mfd->use_mdp_vsync) &&
(mfd->ibuf.vsync_enable) && (mfd->panel_info.lcd.vsync_enable)) {
uint32 start_y;
if (vsync_start_y_adjust <= iBuf->dma_y)
start_y = iBuf->dma_y - vsync_start_y_adjust;
else
start_y =
(mfd->total_lcd_lines - 1) - (vsync_start_y_adjust -
iBuf->dma_y);
MDP_OUTP(MDP_BASE + 0x210, start_y);
MDP_OUTP(MDP_BASE + 0x20c, 1);
} else {
MDP_OUTP(MDP_BASE + 0x20c, 0);
}
#else
#ifdef CONFIG_FB_MSM_MDP22
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0180, dma2_cfg_reg);
#else
MDP_OUTP(MDP_BASE + 0x90000, dma2_cfg_reg);
#endif
#endif
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
/*---------------------------------------------------------------------------------------------------------*/
int32_t main (void)
{
uint8_t ch;
uint32_t u32Data;
/* Init System, IP clock and multi-function I/O */
SYS_Init();
/* Init UART0 for printf */
UART0_Init();
/* Unlock protected registers for ISP function */
SYS_UnlockReg();
/* Enable ISP function */
FMC->ISPCON |= FMC_ISPCON_ISPEN_Msk;
/* Check the signature to check if Simple LD code is finished or not */
if (inp32(KEY_ADDR) == SIGNATURE)
{
/* Just clear SIGNATURE and finish the sample code if Simple LD code has been executed. */
outp32(KEY_ADDR, 0);
/* Read BS */
printf(" Boot Mode .................................. ");
if ((FMC->ISPCON & FMC_ISPCON_BS_Msk) == FMC_ISPCON_BS_APROM)
printf("[APROM]\n");
else
{
printf("[LDROM]\n");
printf(" WARNING: The driver sample code must execute in AP mode!\n");
}
goto lexit;
}
/*
This sample code will demo some function about FMC:
1. Check if CPU boots from APROM
2. Read 96-bit UID
3. Erase LDROM, program LD sample code to LDROM, and verify LD sample code
4. Select next booting from LDROM and run LD sample code
*/
printf("\n\n");
printf("+--------------------------------------------------------+\n");
printf("| M05xx Flash Memory Controller Driver Sample Code |\n");
printf("+--------------------------------------------------------+\n");
printf("\nCPU @ %dHz\n\n", SystemCoreClock);
/* Read BS */
printf(" Boot Mode .................................. ");
if ((FMC->ISPCON & FMC_ISPCON_BS_Msk) == FMC_ISPCON_BS_APROM)
printf("[APROM]\n");
else
{
printf("[LDROM]\n");
printf(" WARNING: The driver sample code must execute in AP mode!\n");
goto lexit;
}
/* Read UID */
printf(" UID[ 0:31] ................................. [0x%x]\n", FMC_ReadUID(0));
printf(" UID[32:63] ................................. [0x%x]\n", FMC_ReadUID(1));
printf(" UID[64:95] ................................. [0x%x]\n", FMC_ReadUID(2));
/* Read Data Flash base address */
printf(" Data Flash Base Address .................... [0x%x]\n", FMC->DFBADR);
/* Check the data in LD ROM to avoid overwrite them */
u32Data = FMC_Read(FMC_LDROM_BASE);
if (u32Data != 0xFFFFFFFF)
{
printf("\n WARNING: There is code in LD ROM.\n If you proceed, the code in LD ROM will be corrupted.\n");
printf(" Continue? [y/n]:");
ch = getchar();
putchar(ch);
if (ch != 'y')
goto lexit;
printf("\n\n");
}
/* Check LD image size */
g_u32ImageSize = (uint32_t)&loaderImageLimit - (uint32_t)&loaderImageBase;
if (g_u32ImageSize == 0)
{
printf(" ERROR: Loader Image is 0 bytes!\n");
goto lexit;
}
if (g_u32ImageSize > FMC_LDROM_SIZE)
{
printf(" ERROR: Loader Image is larger than 4KBytes!\n");
goto lexit;
}
/* Erase LDROM, program LD sample code to LDROM, and verify LD sample code */
/* The chip will boot from LDROM and run LD sample code if LD sample code is downloaded successfully */
FMC_LDROM_Test();
lexit:
/* Disable ISP function */
FMC->ISPCON &= ~FMC_ISPCON_ISPEN_Msk;
/* Lock protected registers */
SYS_LockReg();
printf("\nFMC Sample Code Completed.\n");
}
static int mipi_dsi_ulps_exit(struct hisi_fb_data_type *hisifd,
char __iomem *mipi_dsi_base)
{
uint32_t tmp = 0;
uint32_t cmp_val = 0;
uint32_t try_times = 0;
BUG_ON(hisifd == NULL);
BUG_ON(mipi_dsi_base == NULL);
HISI_FB_DEBUG("fb%d, +!\n", hisifd->index);
if (hisifd->panel_info.mipi.lane_nums >= DSI_4_LANES) {
cmp_val = (BIT(3) | BIT(5) | BIT(8) | BIT(10) | BIT(12));
} else if (hisifd->panel_info.mipi.lane_nums >= DSI_3_LANES) {
cmp_val = (BIT(3) | BIT(5) | BIT(8) | BIT(10));
} else if (hisifd->panel_info.mipi.lane_nums >= DSI_2_LANES) {
cmp_val = (BIT(3) | BIT(5) | BIT(8));
} else {
cmp_val = (BIT(3) | BIT(5));
}
/* enable refclk and cfgclk */
if (is_dual_mipi_panel(hisifd))
outp32(hisifd->crgperi_base + PEREN3_OFFSET, 0x500000);
else
outp32(hisifd->crgperi_base + PEREN3_OFFSET, 0x100000);
/* Test Code @ 0x20 = 0x45 */
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, 0x00010020);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, 0x00000045);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
/* enable DPHY PLL, force_pll = 1 */
outp32(mipi_dsi_base + MIPIDSI_PHY_RSTZ_OFFSET, 0xF);
/* wait DPHY PLL Lock */
try_times = 0;
tmp = inp32(mipi_dsi_base + MIPIDSI_PHY_STATUS_OFFSET);
while ((tmp & BIT(0)) != 0X1) {
udelay(10);
if (++try_times > 100) {
HISI_FB_ERR("fb%d, failed to wait DPHY PLL Lock!MIPIDSI_PHY_STATUS=0x%x.\n",
hisifd->index, tmp);
break;
}
tmp = inp32(mipi_dsi_base + MIPIDSI_PHY_STATUS_OFFSET);
}
/* request that data lane and clock lane exit ULPS */
outp32(mipi_dsi_base + MIPIDSI_PHY_ULPS_CTRL_OFFSET, 0xF);
try_times= 0;
tmp = inp32(mipi_dsi_base + MIPIDSI_PHY_STATUS_OFFSET);
while ((tmp & cmp_val) != cmp_val) {
udelay(10);
if (++try_times > 100) {
HISI_FB_ERR("fb%d, failed to request that data lane and clock lane exit ULPS!MIPIDSI_PHY_STATUS=0x%x.\n",
hisifd->index, tmp);
break;
}
tmp = inp32(mipi_dsi_base + MIPIDSI_PHY_STATUS_OFFSET);
}
/* mipi spec */
mdelay(1);
/* clear PHY_ULPS_CTRL */
outp32(mipi_dsi_base + MIPIDSI_PHY_ULPS_CTRL_OFFSET, 0x0);
/* enable DPHY clock lane's Hight Speed Clock */
set_reg(mipi_dsi_base + MIPIDSI_LPCLK_CTRL_OFFSET, 0x1, 1, 0);
HISI_FB_DEBUG("fb%d, -!\n", hisifd->index);
return 0;
}
/**
* w55fa93_edma_setup_pages - setup W55FA93 EDMA channel SG list for source pages
* @length: total length of the transfer request in bytes
* @src_addr: source pages
* @dest_addr: destination physical address
*
* The function sets up EDMA channel state and registers to be ready for
* transfer specified by provided parameters. The scatter-gather emulation
* is set up according to the parameters.
*
* The full preparation of the transfer requires setup of more register
* by the caller before w55fa93_edma_enable() can be called.
*
* Return value: if incorrect parameters are provided -%EINVAL.
* Zero indicates success.
*/
int
w55fa93_edma_setup_pages(struct page **pages, unsigned int nr_pages,
unsigned int dest_addr, unsigned int dma_length)
{
struct w55fa93_edma_channel *w55fa93edma = &w55fa93_edma_channels[0];
S_DRVEDMA_DESCRIPT_FORMAT *psSGFmt;
unsigned int u32Value, u32TranferByte;
unsigned int u32DestAddr;
int i;
if (w55fa93edma->in_use)
return -EBUSY;
if (dma_length <= 0) {
printk(KERN_ERR "w55fa93_edma_setup_pages zero length\n");
return -EINVAL;
}
w55fa93edma->sg = kmalloc(nr_pages * sizeof(S_DRVEDMA_DESCRIPT_FORMAT), GFP_KERNEL);
w55fa93edma->resbytes = dma_length;
// Set channel 0 transfer address and Scatter-Gather
u32Value = inp32(REG_VDMA_CSR);
u32Value = (u32Value & ~SAD_SEL) | (eDRVEDMA_DIRECTION_INCREMENTED << SOURCE_DIRECTION_BIT);
u32Value = (u32Value & ~DAD_SEL) | (eDRVEDMA_DIRECTION_INCREMENTED << DESTINATION_DIRECTION_BIT);
outp32(REG_VDMA_CSR, u32Value);
DrvEDMA_EnableScatterGather(0);
DrvEDMA_SetScatterGatherTblStartAddr(0, virt_to_phys(w55fa93edma->sg));
//printk("DrvEDMA_SetScatterGatherTblStartAddr: %p\n", virt_to_phys(w55fa93edma->sg));
psSGFmt = w55fa93edma->sg;
u32DestAddr = dest_addr;
u32TranferByte = 0;
/* Not contiguous, writeout per-page instead.. */
for (i = 0; i < nr_pages; i++) {
u32TranferByte = (w55fa93edma->resbytes >= PAGE_SIZE) ? PAGE_SIZE : w55fa93edma->resbytes;
w55fa93edma->resbytes -= u32TranferByte;
// set source and destination address
psSGFmt->u32SourceAddr = page_to_phys(pages[i]);
psSGFmt->u32DestAddr = u32DestAddr;
//printk("SG idx=%d, src_phys=%p, dest_phys=%p, lengh=%d\n", i,psSGFmt->u32SourceAddr,psSGFmt->u32DestAddr,u32TranferByte);
// set stride transfer byte count & byte count
psSGFmt->u32StrideAndByteCount = u32TranferByte;
// set source offset byte length and destination offset byte length
psSGFmt->u32Offset = 0;
// set EOT for last descript format
if (w55fa93edma->resbytes == 0)
{
//printk("set EOT for last descript format\n");
psSGFmt->u32Offset |= 0x80000000;
}
// set next Scatter-Gather table address
psSGFmt->u32NextSGTblAddr = (unsigned int)(psSGFmt+1);
psSGFmt++;
u32DestAddr += u32TranferByte;
}
return 0;
}
int mipi_dsi_bit_clk_upt_isr_handler(struct hisi_fb_data_type *hisifd)
{
char __iomem *mipi_dsi0_base = NULL;
struct mipi_dsi_phy_ctrl phy_ctrl = {0};
struct hisi_panel_info *pinfo = NULL;
uint32_t dsi_bit_clk_upt = 0;
uint32_t hline_time = 0;
uint32_t hsa_time = 0;
uint32_t hbp_time = 0;
uint32_t pixel_clk = 0;
uint32_t tmp = 0;
bool is_ready = false;
int i = 0;
BUG_ON(hisifd == NULL);
pinfo = &(hisifd->panel_info);
dsi_bit_clk_upt = pinfo->mipi.dsi_bit_clk_upt;
mipi_dsi0_base = hisifd->mipi_dsi0_base;
if (hisifd->index != PRIMARY_PANEL_IDX) {
HISI_FB_ERR("fb%d, not support!", hisifd->index);
return 0;
}
if (dsi_bit_clk_upt == pinfo->mipi.dsi_bit_clk) {
return 0;
}
HISI_FB_DEBUG("fb%d +.\n", hisifd->index);
/* get new phy_ctrl value according to dsi_bit_clk_next */
get_dsi_phy_ctrl(pinfo->mipi.dsi_bit_clk_upt, &phy_ctrl);
/*
** Configure the DPHY PLL clock frequency through the TEST Interface to
** operate at XX Hz,
*/
/* Write M Pll part 1 */
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, 0x00010018);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, phy_ctrl.m_pll_1);
/*wait until dphy data lane enter into stop state*/
for (i = 0; i < 40; i++) {
tmp = inp32(mipi_dsi0_base + MIPIDSI_PHY_STATUS_OFFSET);
if ((tmp & 0x00000a90) == 0x00000a90) {
is_ready = true;
break;
}
udelay(1);
}
if (!is_ready) {
HISI_FB_ERR("fb%d, phystopstatedatalane is not ready! MIPIDSI_PHY_STATUS_OFFSET=0x%x.\n",
hisifd->index, tmp);
return 0;
}
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
pinfo->mipi.dsi_bit_clk = dsi_bit_clk_upt;
/* Write M Pll part 2 */
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, 0x00010018);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, phy_ctrl.m_pll_2);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
/* Set hsfreqrange */
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, 0x00010044);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, phy_ctrl.hsfreqrange);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
/* Write CP current */
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, 0x00010011);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, phy_ctrl.cp_current);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
/* Write LPF Control */
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, 0x00010012);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, phy_ctrl.lpf_ctrl);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi0_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
if (!is_mipi_cmd_panel(hisifd)) {
/*
** Define the DPI Horizontal timing configuration:
**
** Hsa_time = HSA*(PCLK period/Clk Lane Byte Period);
** Hbp_time = HBP*(PCLK period/Clk Lane Byte Period);
** Hline_time = (HSA+HBP+HACT+HFP)*(PCLK period/Clk Lane Byte Period);
*/
pixel_clk = pinfo->pxl_clk_rate / 1000000;
hsa_time = pinfo->ldi.h_pulse_width * phy_ctrl.lane_byte_clk / pixel_clk;
hbp_time = pinfo->ldi.h_back_porch * phy_ctrl.lane_byte_clk / pixel_clk;
hline_time = (pinfo->ldi.h_pulse_width + pinfo->ldi.h_back_porch +
pinfo->xres + pinfo->ldi.h_front_porch) *
phy_ctrl.lane_byte_clk / pixel_clk;
outp32(mipi_dsi0_base + MIPIDSI_VID_HSA_TIME_OFFSET, hsa_time);
outp32(mipi_dsi0_base + MIPIDSI_VID_HBP_TIME_OFFSET, hbp_time);
outp32(mipi_dsi0_base + MIPIDSI_VID_HLINE_TIME_OFFSET, hline_time);
}
/* Configure core's phy parameters */
outp32(mipi_dsi0_base + MIPIDSI_PHY_TMR_LPCLK_CFG_OFFSET,
(phy_ctrl.clk_lane_lp2hs_time + (phy_ctrl.clk_lane_hs2lp_time << 16)));
outp32(mipi_dsi0_base + MIPIDSI_PHY_TMR_CFG_OFFSET,
(4095 + (phy_ctrl.data_lane_lp2hs_time << 16) + (phy_ctrl.data_lane_hs2lp_time << 24)));
/*
** Configure the TX_ESC clock frequency to a frequency lower than 20 MHz
** that is the maximum allowed frequency for D-PHY ESCAPE mode.
*/
outp32(mipi_dsi0_base + MIPIDSI_CLKMGR_CFG_OFFSET, (phy_ctrl.clk_division + (phy_ctrl.clk_division<<8)));
HISI_FB_DEBUG("fb%d -.\n", hisifd->index);
return 0;
}
static void mipi_init(struct hisi_fb_data_type *hisifd, char __iomem *mipi_dsi_base)
{
uint32_t hline_time = 0;
uint32_t hsa_time = 0;
uint32_t hbp_time = 0;
uint32_t pixel_clk = 0;
unsigned long dw_jiffies = 0;
struct mipi_dsi_phy_ctrl phy_ctrl = {0};
uint32_t tmp = 0;
bool is_ready = false;
struct hisi_panel_info *pinfo = NULL;
BUG_ON(hisifd == NULL);
BUG_ON(mipi_dsi_base == NULL);
pinfo = &(hisifd->panel_info);
get_dsi_phy_ctrl(pinfo->mipi.dsi_bit_clk, &phy_ctrl);
/* config TE */
if (is_mipi_cmd_panel(hisifd)) {
/* config to command mode */
set_reg(mipi_dsi_base + MIPIDSI_MODE_CFG_OFFSET, 0x1, 1, 0);
/* ALLOWED_CMD_SIZE */
set_reg(mipi_dsi_base + MIPIDSI_EDPI_CMD_SIZE_OFFSET, pinfo->xres, 16, 0);
/* cnt=2 in update-patial scene, cnt nees to be checked for different panels*/
set_reg(mipi_dsi_base + MIPIDSI_HS_WR_TO_CNT_OFFSET, 0x1000002, 25, 0);
/* phy_stop_wait_time */
set_reg(mipi_dsi_base + MIPIDSI_PHY_IF_CFG_OFFSET, 0x30, 8, 8);
/* FIXME: test tearing effect, if use gpio, no need */
/*set_reg(mipi_dsi_base + MIPIDSI_CMD_MODE_CFG_OFFSET, 0x1, 1, 0);*/
}
/*--------------configuring the DPI packet transmission----------------*/
/*
** 1. Global configuration
** Configure Register PHY_IF_CFG with the correct number of lanes
** to be used by the controller.
*/
set_reg(mipi_dsi_base + MIPIDSI_PHY_IF_CFG_OFFSET, pinfo->mipi.lane_nums, 2, 0);
/*
** 2. Configure the DPI Interface:
** This defines how the DPI interface interacts with the controller.
*/
set_reg(mipi_dsi_base + MIPIDSI_DPI_VCID_OFFSET, pinfo->mipi.vc, 2, 0);
set_reg(mipi_dsi_base + MIPIDSI_DPI_COLOR_CODING_OFFSET, pinfo->mipi.color_mode, 4, 0);
set_reg(mipi_dsi_base + MIPIDSI_DPI_CFG_POL_OFFSET, pinfo->ldi.data_en_plr, 1, 0);
set_reg(mipi_dsi_base + MIPIDSI_DPI_CFG_POL_OFFSET, pinfo->ldi.vsync_plr, 1, 1);
set_reg(mipi_dsi_base + MIPIDSI_DPI_CFG_POL_OFFSET, pinfo->ldi.hsync_plr, 1, 2);
set_reg(mipi_dsi_base + MIPIDSI_DPI_CFG_POL_OFFSET, 0x0, 1, 3);
set_reg(mipi_dsi_base + MIPIDSI_DPI_CFG_POL_OFFSET, 0x0, 1, 4);
if (pinfo->bpp == LCD_RGB666) {
set_reg(mipi_dsi_base + MIPIDSI_DPI_COLOR_CODING_OFFSET, 0x1, 1, 8);
}
/*
** 3. Select the Video Transmission Mode:
** This defines how the processor requires the video line to be
** transported through the DSI link.
*/
/* video mode: low power mode */
set_reg(mipi_dsi_base + MIPIDSI_VID_MODE_CFG_OFFSET, 0x3f, 6, 8);
/* set_reg(mipi_dsi_base + MIPIDSI_VID_MODE_CFG_OFFSET, 0x0, 1, 14); */
/* burst mode */
set_reg(mipi_dsi_base + MIPIDSI_VID_MODE_CFG_OFFSET, phy_ctrl.burst_mode, 2, 0);
set_reg(mipi_dsi_base + MIPIDSI_VID_PKT_SIZE_OFFSET, pinfo->xres, 14, 0);
/* for dsi read, BTA enable*/
set_reg(mipi_dsi_base + MIPIDSI_PCKHDL_CFG_OFFSET, 0x1, 1, 2);
/*
** 4. Define the DPI Horizontal timing configuration:
**
** Hsa_time = HSA*(PCLK period/Clk Lane Byte Period);
** Hbp_time = HBP*(PCLK period/Clk Lane Byte Period);
** Hline_time = (HSA+HBP+HACT+HFP)*(PCLK period/Clk Lane Byte Period);
*/
pixel_clk = pinfo->pxl_clk_rate / 1000000;
hsa_time = pinfo->ldi.h_pulse_width * phy_ctrl.lane_byte_clk / pixel_clk;
hbp_time = pinfo->ldi.h_back_porch * phy_ctrl.lane_byte_clk / pixel_clk;
hline_time = (pinfo->ldi.h_pulse_width + pinfo->ldi.h_back_porch +
pinfo->xres + pinfo->ldi.h_front_porch) *
phy_ctrl.lane_byte_clk / pixel_clk;
set_reg(mipi_dsi_base + MIPIDSI_VID_HSA_TIME_OFFSET, hsa_time, 12, 0);
set_reg(mipi_dsi_base + MIPIDSI_VID_HBP_TIME_OFFSET, hbp_time, 12, 0);
set_reg(mipi_dsi_base + MIPIDSI_VID_HLINE_TIME_OFFSET, hline_time, 15, 0);
/*
** 5. Define the Vertical line configuration:
*/
set_reg(mipi_dsi_base + MIPIDSI_VID_VSA_LINES_OFFSET, pinfo->ldi.v_pulse_width, 10, 0);
set_reg(mipi_dsi_base + MIPIDSI_VID_VBP_LINES_OFFSET, pinfo->ldi.v_back_porch, 10, 0);
set_reg(mipi_dsi_base + MIPIDSI_VID_VFP_LINES_OFFSET, pinfo->ldi.v_front_porch, 10, 0);
set_reg(mipi_dsi_base + MIPIDSI_VID_VACTIVE_LINES_OFFSET, pinfo->yres, 14, 0);
set_reg(mipi_dsi_base + MIPIDSI_TO_CNT_CFG_OFFSET, 0x7FF, 16, 0);
/* Configure core's phy parameters */
set_reg(mipi_dsi_base + MIPIDSI_PHY_TMR_CFG_OFFSET, 4095, 15, 0);
set_reg(mipi_dsi_base + MIPIDSI_PHY_TMR_LPCLK_CFG_OFFSET, phy_ctrl.clk_lane_lp2hs_time, 10, 0);
set_reg(mipi_dsi_base + MIPIDSI_PHY_TMR_LPCLK_CFG_OFFSET, phy_ctrl.clk_lane_hs2lp_time, 10, 16);
set_reg(mipi_dsi_base + MIPIDSI_PHY_TMR_CFG_OFFSET, phy_ctrl.data_lane_lp2hs_time, 8, 16);
set_reg(mipi_dsi_base + MIPIDSI_PHY_TMR_CFG_OFFSET, phy_ctrl.data_lane_hs2lp_time, 8, 24);
/*------------DSI and D-PHY Initialization-----------------*/
/* 1. Waking up Core */
set_reg(mipi_dsi_base + MIPIDSI_PWR_UP_OFFSET, 0x1, 1, 0);
/*
** 3. Configure the TX_ESC clock frequency to a frequency lower than 20 MHz
** that is the maximum allowed frequency for D-PHY ESCAPE mode.
*/
set_reg(mipi_dsi_base + MIPIDSI_CLKMGR_CFG_OFFSET, phy_ctrl.clk_division, 8, 0);
set_reg(mipi_dsi_base + MIPIDSI_CLKMGR_CFG_OFFSET, phy_ctrl.clk_division, 8, 8);
/*
** 4. Configure the DPHY PLL clock frequency through the TEST Interface to
** operate at XX Hz,
*/
/* Write CP current */
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, 0x00010011);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, phy_ctrl.cp_current);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
/* Write LPF Control */
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, 0x00010012);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, phy_ctrl.lpf_ctrl);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
/*Configured N and M factors effective*/
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, 0x00010019);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, phy_ctrl.factors_effective);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
/* Write N Pll */
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, 0x00010017);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, phy_ctrl.n_pll-1);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
/* Write M Pll part 1 */
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, 0x00010018);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, phy_ctrl.m_pll_1);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
/* Write M Pll part 2 */
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, 0x00010018);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, phy_ctrl.m_pll_2);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
/* Set hsfreqrange */
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, 0x00010044);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, phy_ctrl.hsfreqrange);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
/* Set PLL unlocking filter */
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, 0x00010016);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, phy_ctrl.pll_unlocking_filter);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
#if 0
/* Set the phy direction*/
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, 0x000100b0);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL1_OFFSET, 0x00000001);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000002);
outp32(mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET, 0x00000000);
#endif
outp32(mipi_dsi_base + MIPIDSI_PHY_RSTZ_OFFSET, 0x0000000F);
is_ready = false;
dw_jiffies = jiffies + HZ / 2;
do {
tmp = inp32(mipi_dsi_base + MIPIDSI_PHY_STATUS_OFFSET);
if ((tmp & 0x00000001) == 0x00000001) {
is_ready = true;
break;
}
} while (time_after(dw_jiffies, jiffies));
if (!is_ready) {
HISI_FB_INFO("fb%d, phylock is not ready!MIPIDSI_PHY_STATUS_OFFSET=0x%x.\n",
hisifd->index, tmp);
}
is_ready = false;
dw_jiffies = jiffies + HZ / 2;
do {
tmp = inp32(mipi_dsi_base + MIPIDSI_PHY_STATUS_OFFSET);
if ((tmp & 0x00000004) == 0x00000004) {
is_ready = true;
break;
}
} while (time_after(dw_jiffies, jiffies));
if (!is_ready) {
HISI_FB_INFO("fb%d, phystopstateclklane is not ready! MIPIDSI_PHY_STATUS_OFFSET=0x%x.\n",
hisifd->index, tmp);
}
}
static void mdp_dma_s_update_lcd(struct msm_fb_data_type *mfd)
{
MDPIBUF *iBuf = &mfd->ibuf;
int mddi_dest = FALSE;
uint32 outBpp = iBuf->bpp;
uint32 dma_s_cfg_reg;
uint8 *src;
struct msm_fb_panel_data *pdata =
(struct msm_fb_panel_data *)mfd->pdev->dev.platform_data;
dma_s_cfg_reg = DMA_PACK_TIGHT | DMA_PACK_ALIGN_LSB |
DMA_OUT_SEL_AHB | DMA_IBUF_NONCONTIGUOUS;
if (mfd->fb_imgType == MDP_BGR_565)
dma_s_cfg_reg |= DMA_PACK_PATTERN_BGR;
else
dma_s_cfg_reg |= DMA_PACK_PATTERN_RGB;
if (outBpp == 4)
dma_s_cfg_reg |= DMA_IBUF_C3ALPHA_EN;
if (outBpp == 2)
dma_s_cfg_reg |= DMA_IBUF_FORMAT_RGB565;
if (mfd->panel_info.pdest != DISPLAY_2) {
printk(KERN_ERR "error: non-secondary type through dma_s!\n");
return;
}
if (mfd->panel_info.type == MDDI_PANEL ||
mfd->panel_info.type == EXT_MDDI_PANEL) {
dma_s_cfg_reg |= DMA_OUT_SEL_MDDI;
mddi_dest = TRUE;
} else {
dma_s_cfg_reg |= DMA_AHBM_LCD_SEL_SECONDARY;
outp32(MDP_EBI2_LCD1, mfd->data_port_phys);
}
dma_s_cfg_reg |= DMA_DITHER_EN;
src = (uint8 *) iBuf->buf;
src += (iBuf->dma_x + iBuf->dma_y * iBuf->ibuf_width) * outBpp;
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
if (mfd->panel_info.type == MDDI_PANEL) {
MDP_OUTP(MDP_BASE + 0xa0004,
(iBuf->dma_h << 16 | iBuf->dma_w));
MDP_OUTP(MDP_BASE + 0xa0008, src);
MDP_OUTP(MDP_BASE + 0xa000c,
iBuf->ibuf_width * outBpp);
} else {
MDP_OUTP(MDP_BASE + 0xb0004,
(iBuf->dma_h << 16 | iBuf->dma_w));
MDP_OUTP(MDP_BASE + 0xb0008, src);
MDP_OUTP(MDP_BASE + 0xb000c,
iBuf->ibuf_width * outBpp);
}
if (mfd->panel_info.bpp == 18) {
dma_s_cfg_reg |= DMA_DSTC0G_6BITS |
DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
} else {
dma_s_cfg_reg |= DMA_DSTC0G_6BITS |
DMA_DSTC1B_5BITS | DMA_DSTC2R_5BITS;
}
if (mddi_dest) {
if (mfd->panel_info.type == MDDI_PANEL) {
MDP_OUTP(MDP_BASE + 0xa0010,
(iBuf->dma_y << 16) | iBuf->dma_x);
MDP_OUTP(MDP_BASE + 0x00090, 1);
} else {
MDP_OUTP(MDP_BASE + 0xb0010,
(iBuf->dma_y << 16) | iBuf->dma_x);
MDP_OUTP(MDP_BASE + 0x00090, 2);
}
MDP_OUTP(MDP_BASE + 0x00094,
(MDDI_VDO_PACKET_DESC << 16) |
mfd->panel_info.mddi.vdopkt);
} else {
pdata->set_rect(iBuf->dma_x, iBuf->dma_y, iBuf->dma_w,
iBuf->dma_h);
}
if (mfd->panel_info.type == MDDI_PANEL)
MDP_OUTP(MDP_BASE + 0xa0000, dma_s_cfg_reg);
else
MDP_OUTP(MDP_BASE + 0xb0000, dma_s_cfg_reg);
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
if (mfd->panel_info.type == MDDI_PANEL)
mdp_pipe_kickoff(MDP_DMA_S_TERM, mfd);
else
mdp_pipe_kickoff(MDP_DMA_E_TERM, mfd);
}
static int mdp_probe(struct platform_device *pdev)
{
struct platform_device *msm_fb_dev = NULL;
struct msm_fb_data_type *mfd;
struct msm_fb_panel_data *pdata = NULL;
int rc;
unsigned long flag;
resource_size_t size ;
if ((pdev->id == 0) && (pdev->num_resources > 0)) {
mdp_pdata = pdev->dev.platform_data;
size = resource_size(&pdev->resource[0]);
msm_mdp_base = ioremap(pdev->resource[0].start, size);
MSM_FB_INFO("MDP HW Base Address = 0x%x\n",
(int)pdev->resource[0].start);
if (unlikely(!msm_mdp_base))
return -ENOMEM;
mdp_resource_initialized = 1;
return 0;
}
if (!mdp_resource_initialized)
return -EPERM;
mfd = platform_get_drvdata(pdev);
if (!mfd)
return -ENODEV;
if (mfd->key != MFD_KEY)
return -EINVAL;
if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST)
return -ENOMEM;
msm_fb_dev = platform_device_alloc("msm_fb", pdev->id);
if (!msm_fb_dev)
return -ENOMEM;
/////////////////////////////////////////
// link to the latest pdev
/////////////////////////////////////////
mfd->pdev = msm_fb_dev;
/////////////////////////////////////////
// add panel data
/////////////////////////////////////////
if (platform_device_add_data
(msm_fb_dev, pdev->dev.platform_data,
sizeof(struct msm_fb_panel_data))) {
printk(KERN_ERR "mdp_probe: platform_device_add_data failed!\n");
rc = -ENOMEM;
goto mdp_probe_err;
}
/////////////////////////////////////////
// data chain
/////////////////////////////////////////
pdata = msm_fb_dev->dev.platform_data;
pdata->on = mdp_on;
pdata->off = mdp_off;
pdata->next = pdev;
switch (mfd->panel.type) {
case EXT_MDDI_PANEL:
case MDDI_PANEL:
case EBI2_PANEL:
INIT_WORK(&mfd->dma_update_worker,
mdp_lcd_update_workqueue_handler);
INIT_WORK(&mfd->vsync_resync_worker,
mdp_vsync_resync_workqueue_handler);
mfd->hw_refresh = FALSE;
if (mfd->panel.type == EXT_MDDI_PANEL)
mfd->refresh_timer_duration = (66 * HZ / 1000); // 15 fps -> 66 msec
else
mfd->refresh_timer_duration = (42 * HZ / 1000); // 24 fps -> 42 msec
#ifdef CONFIG_FB_MSM_MDP22
mfd->dma_fnc = mdp_dma2_update;
mfd->dma = &dma2_data;
#else
if (mfd->panel_info.pdest == DISPLAY_1) {
mfd->dma_fnc = mdp_dma2_update;
mfd->dma = &dma2_data;
} else {
mfd->dma_fnc = mdp_dma_s_update;
mfd->dma = &dma_s_data;
}
#endif
if (mdp_pdata)
mfd->vsync_gpio = mdp_pdata->gpio;
else
mfd->vsync_gpio = -1;
mdp_config_vsync(mfd);
break;
case LCDC_PANEL:
pdata->on = mdp_lcdc_on;
pdata->off = mdp_lcdc_off;
mfd->hw_refresh = TRUE;
mfd->cursor_update = mdp_hw_cursor_update;
mfd->dma_fnc = mdp_lcdc_update;
mfd->dma = &dma2_data;
spin_lock_irqsave(&mdp_spin_lock, flag);
mdp_intr_mask &= ~MDP_DMA_P_DONE;
outp32(MDP_INTR_ENABLE, mdp_intr_mask);
spin_unlock_irqrestore(&mdp_spin_lock, flag);
break;
case TV_PANEL:
pdata->on = mdp_dma3_on;
pdata->off = mdp_dma3_off;
mfd->hw_refresh = TRUE;
mfd->dma_fnc = mdp_dma3_update;
mfd->dma = &dma3_data;
break;
default:
printk(KERN_ERR "mdp_probe: unknown device type!\n");
rc = -ENODEV;
goto mdp_probe_err;
}
/////////////////////////////////////////
// set driver data
/////////////////////////////////////////
platform_set_drvdata(msm_fb_dev, mfd);
rc = platform_device_add(msm_fb_dev);
if (rc) {
goto mdp_probe_err;
}
pdev_list[pdev_list_cnt++] = pdev;
return 0;
mdp_probe_err:
platform_device_put(msm_fb_dev);
return rc;
}
irqreturn_t mdp_isr(int irq, void *ptr)
{
uint32 mdp_interrupt = 0;
struct mdp_dma_data *dma;
mdp_is_in_isr = TRUE;
do {
mdp_interrupt = inp32(MDP_INTR_STATUS);
outp32(MDP_INTR_CLEAR, mdp_interrupt);
mdp_interrupt &= mdp_intr_mask;
if (mdp_interrupt & TV_ENC_UNDERRUN) {
mdp_interrupt &= ~(TV_ENC_UNDERRUN);
mdp_tv_underflow_cnt++;
}
if (!mdp_interrupt)
break;
///////////////////////////////
// DMA3 TV-Out Start
///////////////////////////////
if (mdp_interrupt & TV_OUT_DMA3_START) {
// let's disable TV out interrupt
mdp_intr_mask &= ~TV_OUT_DMA3_START;
outp32(MDP_INTR_ENABLE, mdp_intr_mask);
dma = &dma3_data;
if (dma->waiting) {
dma->waiting = FALSE;
complete(&dma->comp);
}
}
#ifndef CONFIG_FB_MSM_MDP22
///////////////////////////////
// LCDC UnderFlow
///////////////////////////////
if (mdp_interrupt & LCDC_UNDERFLOW) {
mdp_lcdc_underflow_cnt++;
}
///////////////////////////////
// LCDC Frame Start
///////////////////////////////
if (mdp_interrupt & LCDC_FRAME_START) {
// let's disable LCDC interrupt
mdp_intr_mask &= ~LCDC_FRAME_START;
outp32(MDP_INTR_ENABLE, mdp_intr_mask);
dma = &dma2_data;
if (dma->waiting) {
dma->waiting = FALSE;
complete(&dma->comp);
}
}
///////////////////////////////
// DMA2 LCD-Out Complete
///////////////////////////////
if (mdp_interrupt & MDP_DMA_S_DONE) {
dma = &dma_s_data;
dma->busy = FALSE;
mdp_pipe_ctrl(MDP_DMA_S_BLOCK, MDP_BLOCK_POWER_OFF,
TRUE);
complete(&dma->comp);
}
#endif
///////////////////////////////
// DMA2 LCD-Out Complete
///////////////////////////////
if (mdp_interrupt & MDP_DMA_P_DONE) {
struct timeval now;
ktime_t now_k;
now_k = ktime_get_real();
mdp_dma2_last_update_time.tv.sec =
now_k.tv.sec - mdp_dma2_last_update_time.tv.sec;
mdp_dma2_last_update_time.tv.nsec =
now_k.tv.nsec - mdp_dma2_last_update_time.tv.nsec;
if (mdp_debug[MDP_DMA2_BLOCK]) {
jiffies_to_timeval(jiffies, &now);
mdp_dma2_timeval.tv_usec =
now.tv_usec - mdp_dma2_timeval.tv_usec;
}
dma = &dma2_data;
dma->busy = FALSE;
mdp_pipe_ctrl(MDP_DMA2_BLOCK, MDP_BLOCK_POWER_OFF,
TRUE);
complete(&dma->comp);
}
///////////////////////////////
// PPP Complete
///////////////////////////////
if (mdp_interrupt & MDP_PPP_DONE) {
mdp_pipe_ctrl(MDP_PPP_BLOCK, MDP_BLOCK_POWER_OFF, TRUE);
if (mdp_ppp_waiting) {
mdp_ppp_waiting = FALSE;
complete(&mdp_ppp_comp);
}
}
} while (1);
mdp_is_in_isr = FALSE;
return IRQ_HANDLED;
}
void mdp_hw_init(void)
{
int i;
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
/* debug interface write access */
outpdw(MDP_BASE + 0x60, 1);
outp32(MDP_INTR_ENABLE, MDP_ANY_INTR_MASK);
outp32(MDP_EBI2_PORTMAP_MODE, 0x3);
outpdw(MDP_CMD_DEBUG_ACCESS_BASE + 0x01f8, 0x0);
outpdw(MDP_CMD_DEBUG_ACCESS_BASE + 0x01fc, 0x0);
outpdw(MDP_BASE + 0x60, 0x1);
mdp_load_lut_param();
/*
* clear up unused fg/main registers
*/
/* comp.plane 2&3 ystride */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0120, 0x0);
/* unpacked pattern */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x012c, 0x0);
/* unpacked pattern */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0130, 0x0);
/* unpacked pattern */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0134, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0158, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x15c, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0160, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0170, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0174, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x017c, 0x0);
/* comp.plane 2 */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0114, 0x0);
/* comp.plane 3 */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0118, 0x0);
/* clear up unused bg registers */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01c8, 0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01d0, 0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01dc, 0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01e0, 0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01e4, 0);
#ifndef CONFIG_FB_MSM_MDP22
MDP_OUTP(MDP_BASE + 0xE0000, 0);
MDP_OUTP(MDP_BASE + 0x100, 0xffffffff);
MDP_OUTP(MDP_BASE + 0x90070, 0);
MDP_OUTP(MDP_BASE + 0x94010, 1);
MDP_OUTP(MDP_BASE + 0x9401c, 2);
#endif
/*
* limit vector
* pre gets applied before color matrix conversion
* post is after ccs
*/
writel(mdp_plv[0], MDP_CSC_PRE_LV1n(0));
writel(mdp_plv[1], MDP_CSC_PRE_LV1n(1));
writel(mdp_plv[2], MDP_CSC_PRE_LV1n(2));
writel(mdp_plv[3], MDP_CSC_PRE_LV1n(3));
#ifdef CONFIG_FB_MSM_MDP31
writel(mdp_plv[2], MDP_CSC_PRE_LV1n(4));
writel(mdp_plv[3], MDP_CSC_PRE_LV1n(5));
writel(0, MDP_CSC_POST_LV1n(0));
writel(0xff, MDP_CSC_POST_LV1n(1));
writel(0, MDP_CSC_POST_LV1n(2));
writel(0xff, MDP_CSC_POST_LV1n(3));
writel(0, MDP_CSC_POST_LV1n(4));
writel(0xff, MDP_CSC_POST_LV1n(5));
writel(0, MDP_CSC_PRE_LV2n(0));
writel(0xff, MDP_CSC_PRE_LV2n(1));
writel(0, MDP_CSC_PRE_LV2n(2));
writel(0xff, MDP_CSC_PRE_LV2n(3));
writel(0, MDP_CSC_PRE_LV2n(4));
writel(0xff, MDP_CSC_PRE_LV2n(5));
writel(mdp_plv[0], MDP_CSC_POST_LV2n(0));
writel(mdp_plv[1], MDP_CSC_POST_LV2n(1));
writel(mdp_plv[2], MDP_CSC_POST_LV2n(2));
writel(mdp_plv[3], MDP_CSC_POST_LV2n(3));
writel(mdp_plv[2], MDP_CSC_POST_LV2n(4));
writel(mdp_plv[3], MDP_CSC_POST_LV2n(5));
#endif
/* primary forward matrix */
for (i = 0; i < MDP_CCS_SIZE; i++)
writel(mdp_ccs_rgb2yuv.ccs[i], MDP_CSC_PFMVn(i));
#ifdef CONFIG_FB_MSM_MDP31
for (i = 0; i < MDP_BV_SIZE; i++)
writel(mdp_ccs_rgb2yuv.bv[i], MDP_CSC_POST_BV2n(i));
writel(0, MDP_CSC_PRE_BV2n(0));
writel(0, MDP_CSC_PRE_BV2n(1));
writel(0, MDP_CSC_PRE_BV2n(2));
#endif
/* primary reverse matrix */
for (i = 0; i < MDP_CCS_SIZE; i++)
writel(mdp_ccs_yuv2rgb.ccs[i], MDP_CSC_PRMVn(i));
for (i = 0; i < MDP_BV_SIZE; i++)
writel(mdp_ccs_yuv2rgb.bv[i], MDP_CSC_PRE_BV1n(i));
#ifdef CONFIG_FB_MSM_MDP31
writel(0, MDP_CSC_POST_BV1n(0));
writel(0, MDP_CSC_POST_BV1n(1));
writel(0, MDP_CSC_POST_BV1n(2));
outpdw(MDP_BASE + 0x30010, 0x03e0);
outpdw(MDP_BASE + 0x30014, 0x0360);
outpdw(MDP_BASE + 0x30018, 0x0120);
outpdw(MDP_BASE + 0x3001c, 0x0140);
#endif
mdp_init_scale_table();
#ifndef CONFIG_FB_MSM_MDP31
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0104,
((16 << 6) << 16) | (16) << 6);
#endif
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
void w55fa93_adc_recording_setup(void)
{
UINT32 u32Reg;
UINT32 eMode = eDRVADC_RECORD_MODE_1;
ENTER();
#if 1
DrvADC_Open(eDRVADC_RECORD, //Record mode
eDRVSYS_APLL, //Source clock come from UPLL
8); //Deafult 8K sample rate.
DrvADC_SetGainControl(eDRVADC_PRE_P14, eDRVADC_POST_P34P5);
// DrvADC_SetGainControl(eDRVADC_PRE_P14, eDRVADC_POST_P34P5);
//eDRVADC_POST_P0);
DrvADC_SetAutoGainTiming(4, //Period
4, //Attack
4, //Recovery
4); //Hold
DrvADC_SetAutoGainControl(TRUE,
//11, //Output target -12db
//15, //Output target -6db
//13, //Output target -9db
12, //Output target -10.5db
eDRVADC_BAND_P0P5,
eDRVADC_BAND_N0P5);
DrvADC_SetOffsetCancellation(FALSE, //BOOL bIsMuteEnable,
FALSE, //BOOL bIsOffsetCalibration,
FALSE, //BOOL bIsHardwareMode,
0x10); //UINT32 u32Offset
DrvADC_SetOffsetCancellationEx(1, //255 sample
512); //Delay sample count
DrvADC_SetNoiseGate(FALSE, eDRVADC_NG_N48);
#else
DrvADC_Open(eDRVADC_RECORD, //Record mode
eDRVSYS_APLL, //Source clock come from UPLL
8); //Deafult 8K sample rate.
DrvADC_SetGainControl(eDRVADC_PRE_P14,
eDRVADC_POST_P0);
DrvADC_SetClampingAGC(eDRVADC_MAX_P17P25,
eDRVADC_MIN_N12);
DrvADC_SetAutoGainTiming(4, //Period
4, //Attack
4, //Recovery sync
4); //Hold
DrvADC_SetOffsetCancellation(FALSE, //BOOL bIsMuteEnable,
FALSE, //BOOL bIsOffsetCalibration,
FALSE, //BOOL bIsHardwareMode,
0x1A); //UINT32 u32Offset
DrvADC_SetOffsetCancellationEx(1, //255 sample
256); //Delay sample count
DrvADC_SetNoiseGate(FALSE, eDRVADC_NG_N36);
DrvADC_SetAutoGainControl(TRUE,
12, //Output target -10.5db //11, //Output target -12db
eDRVADC_BAND_P0P5,
eDRVADC_BAND_N0P5);
#endif
outp32(REG_AUDIO_CON, inp32(REG_AUDIO_CON) &
~AUDIO_INT_MODE & ~AUDIO_INT_EN); // one sample if finish
outp32(REG_AGCP1,inp32(REG_AGCP1) | 0x80000000); // Enabe EDMA for ADC
}
void mdp_hw_init(void)
{
int i;
/* LGE_CHANGE [[email protected]] 2010-08-28, probe LCD */
#if defined(CONFIG_FB_MSM_MDDI_NOVATEK_HITACHI_HVGA)
lge_probe_lcd();
#endif
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
/* debug interface write access */
outpdw(MDP_BASE + 0x60, 1);
outp32(MDP_INTR_ENABLE, MDP_ANY_INTR_MASK);
outp32(MDP_EBI2_PORTMAP_MODE, 0x3);
outpdw(MDP_CMD_DEBUG_ACCESS_BASE + 0x01f8, 0x0);
outpdw(MDP_CMD_DEBUG_ACCESS_BASE + 0x01fc, 0x0);
outpdw(MDP_BASE + 0x60, 0x1);
mdp_load_lut_param();
/*
* clear up unused fg/main registers
*/
/* comp.plane 2&3 ystride */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0120, 0x0);
/* unpacked pattern */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x012c, 0x0);
/* unpacked pattern */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0130, 0x0);
/* unpacked pattern */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0134, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0158, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x15c, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0160, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0170, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0174, 0x0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x017c, 0x0);
/* comp.plane 2 */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0114, 0x0);
/* comp.plane 3 */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0118, 0x0);
/* clear up unused bg registers */
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01c8, 0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01d0, 0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01dc, 0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01e0, 0);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01e4, 0);
#ifndef CONFIG_FB_MSM_MDP22
MDP_OUTP(MDP_BASE + 0xE0000, 0);
MDP_OUTP(MDP_BASE + 0x100, 0xffffffff);
MDP_OUTP(MDP_BASE + 0x90070, 0);
MDP_OUTP(MDP_BASE + 0x94010, 1);
MDP_OUTP(MDP_BASE + 0x9401c, 2);
#endif
#if defined(CONFIG_MACH_MSM7X27_THUNDERG) || defined(CONFIG_MACH_MSM7X27_THUNDERC)
/* LGE_CHANGE_S
* Change code to apply new LUT for display quality. 2010-08-03. [email protected]
*/
mdp_load_thunder_lut(1); // nornal
#endif
/*
* limit vector
* pre gets applied before color matrix conversion
* post is after ccs
*/
writel(mdp_plv[0], MDP_CSC_PRE_LV1n(0));
writel(mdp_plv[1], MDP_CSC_PRE_LV1n(1));
writel(mdp_plv[2], MDP_CSC_PRE_LV1n(2));
writel(mdp_plv[3], MDP_CSC_PRE_LV1n(3));
#ifdef CONFIG_FB_MSM_MDP31
writel(mdp_plv[2], MDP_CSC_PRE_LV1n(4));
writel(mdp_plv[3], MDP_CSC_PRE_LV1n(5));
writel(0, MDP_CSC_POST_LV1n(0));
writel(0xff, MDP_CSC_POST_LV1n(1));
writel(0, MDP_CSC_POST_LV1n(2));
writel(0xff, MDP_CSC_POST_LV1n(3));
writel(0, MDP_CSC_POST_LV1n(4));
writel(0xff, MDP_CSC_POST_LV1n(5));
writel(0, MDP_CSC_PRE_LV2n(0));
writel(0xff, MDP_CSC_PRE_LV2n(1));
writel(0, MDP_CSC_PRE_LV2n(2));
writel(0xff, MDP_CSC_PRE_LV2n(3));
writel(0, MDP_CSC_PRE_LV2n(4));
writel(0xff, MDP_CSC_PRE_LV2n(5));
writel(mdp_plv[0], MDP_CSC_POST_LV2n(0));
writel(mdp_plv[1], MDP_CSC_POST_LV2n(1));
writel(mdp_plv[2], MDP_CSC_POST_LV2n(2));
writel(mdp_plv[3], MDP_CSC_POST_LV2n(3));
writel(mdp_plv[2], MDP_CSC_POST_LV2n(4));
writel(mdp_plv[3], MDP_CSC_POST_LV2n(5));
#endif
/* primary forward matrix */
for (i = 0; i < MDP_CCS_SIZE; i++)
writel(mdp_ccs_rgb2yuv.ccs[i], MDP_CSC_PFMVn(i));
#ifdef CONFIG_FB_MSM_MDP31
for (i = 0; i < MDP_BV_SIZE; i++)
writel(mdp_ccs_rgb2yuv.bv[i], MDP_CSC_POST_BV2n(i));
writel(0, MDP_CSC_PRE_BV2n(0));
writel(0, MDP_CSC_PRE_BV2n(1));
writel(0, MDP_CSC_PRE_BV2n(2));
#endif
/* primary reverse matrix */
for (i = 0; i < MDP_CCS_SIZE; i++)
writel(mdp_ccs_yuv2rgb.ccs[i], MDP_CSC_PRMVn(i));
for (i = 0; i < MDP_BV_SIZE; i++)
writel(mdp_ccs_yuv2rgb.bv[i], MDP_CSC_PRE_BV1n(i));
#ifdef CONFIG_FB_MSM_MDP31
writel(0, MDP_CSC_POST_BV1n(0));
writel(0, MDP_CSC_POST_BV1n(1));
writel(0, MDP_CSC_POST_BV1n(2));
outpdw(MDP_BASE + 0x30010, 0x03e0);
outpdw(MDP_BASE + 0x30014, 0x0360);
outpdw(MDP_BASE + 0x30018, 0x0120);
outpdw(MDP_BASE + 0x3001c, 0x0140);
#endif
mdp_init_scale_table();
#ifndef CONFIG_FB_MSM_MDP31
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0104,
((16 << 6) << 16) | (16) << 6);
#endif
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
static void dpe_interrupt_unmask(struct k3_fb_data_type *k3fd)
{
char __iomem *dss_base = 0;
u32 unmask = 0;
BUG_ON(k3fd == NULL);
dss_base = k3fd->dss_base;
if (k3fd->index == PRIMARY_PANEL_IDX) {
/* Stage 1 interrupts */
//unmask = ~0;
//unmask &= ~(BIT_PDP_LDI0_IRQ_CPU | BIT_WBE0_MMU_IRQ_CPU);
unmask = 0x0;
outp32(dss_base + DSS_GLB_PDP_CPU_IRQ_MSK, unmask);
/*
** Stage 2 interrupts
** BIT_LDI_UNFLOW_INT in k3_baselayer_init
*/
unmask = ~0;
if (is_mipi_cmd_panel(k3fd))
unmask &= ~(BIT_BACKLIGHT_INT | BIT_VACTIVE0_START_INT | BIT_LDI_TE0_PIN_INT);
else
unmask &= ~(BIT_BACKLIGHT_INT | BIT_VSYNC_INT | BIT_VACTIVE0_START_INT);
outp32(dss_base + PDP_LDI_CPU_IRQ_MSK, unmask);
unmask = ~0;
unmask &= ~(BIT_WBE0_FRAME_END_CPU_CH1 | BIT_WBE0_FRAME_END_CPU_CH0);
outp32(dss_base + DSS_DPE0_OFFSET +
DSS_DP_CTRL_OFFSET + PDP_WBE0_CPU_IRQ_MSK, unmask);
} else if (k3fd->index == EXTERNAL_PANEL_IDX) {
/* Stage 1 interrupts */
//unmask = ~0;
//unmask &= ~(BIT_SDP_LDI1_IRQ_MCU | BIT_WBE0_MMU_IRQ_CPU);
unmask = 0x0;
outp32(dss_base + DSS_GLB_SDP_CPU_IRQ_MSK, unmask);
/* Stage 2 interrupts */
unmask = ~0;
unmask &= ~(BIT_VSYNC_INT | BIT_VACTIVE0_START_INT);
outp32(dss_base + SDP_LDI_CPU_IRQ_MSK, unmask);
unmask = ~0;
unmask &= ~(BIT_WBE0_FRAME_END_CPU_CH1 | BIT_WBE0_FRAME_END_CPU_CH0);
outp32(dss_base + DSS_DPE1_OFFSET +
DSS_DP_CTRL_OFFSET + SDP_WBE0_CPU_IRQ_MSK, unmask);
} else if (k3fd->index == AUXILIARY_PANEL_IDX) {
/* Stage 1 interrupts */
//unmask = ~0;
//unmask &= ~(BIT_OFFLINE_S2_IRQ_CPU_OFF |
// BIT_WBE1_MMU_IRQ_CPU_OFF | BIT_WBE0_MMU_IRQ_CPU_OFF |
// BIT_CMDLIST_IRQ_CPU_OFF);
unmask = 0x0;
outp32(dss_base + DSS_GLB_OFFLINE_CPU_IRQ_MSK, unmask);
/* Stage 2 interrupts */
unmask = ~0;
unmask &= ~(BIT_OFFLINE_WBE1_CH0_FRM_END_CPU |
BIT_OFFLINE_WBE1_CH1_FRM_END_CPU);
outp32(dss_base + DSS_DPE3_OFFSET +
DSS_DP_CTRL_OFFSET + OFFLINE_WBE1_CPU_IRQ_MSK, unmask);
/* enable adp irq */
//outp32(dss_base + DSS_GLB_OFFLINE_S2_CPU_IRQ_MSK, 0);
/* enable cmdlist irq */
//set_reg(dss_base + DSS_CMD_LIST_OFFSET + CMDLIST_CH4_INTE, 0x3F, 6, 0);
//set_reg(dss_base + DSS_CMD_LIST_OFFSET + CMDLIST_CH5_INTE, 0x3F, 6, 0);
} else {
K3_FB_ERR("fb%d, not support this device!\n", k3fd->index);
}
}
/**
* w55fa93_edma_setup_virtual - setup W55FA93 EDMA channel SG list for source virtual address
* @length: total length of the transfer request in bytes
* @src_addr: source virtual address
* @dest_addr: destination physical address
*
* The function sets up EDMA channel state and registers to be ready for
* transfer specified by provided parameters. The scatter-gather emulation
* is set up according to the parameters.
*
* The full preparation of the transfer requires setup of more register
* by the caller before w55fa93_edma_enable() can be called.
*
* Return value: if incorrect parameters are provided -%EINVAL.
* Zero indicates success.
*/
int
w55fa93_edma_setup_virtual(unsigned int src_addr, unsigned int dest_addr,
unsigned int dma_length)
{
struct w55fa93_edma_channel *w55fa93edma = &w55fa93_edma_channels[0];
unsigned int sgcount;
S_DRVEDMA_DESCRIPT_FORMAT *psSGFmt;
unsigned int u32Value, u32TranferByte;
unsigned int u32SrcAddr, u32DestAddr;
if (w55fa93edma->in_use)
return -EBUSY;
if (dma_length <= 0) {
printk(KERN_ERR "w55fa93_edma_setup_virtual zero length\n");
return -EINVAL;
}
if ((src_addr & 0x0FFF) || (src_addr & 0x0FFF)) {
printk(KERN_ERR "w55fa93_edma_setup_virtual address is not PAGE_SIZE alignment\n");
return -EINVAL;
}
sgcount = (dma_length + PAGE_SIZE - 1) / PAGE_SIZE;
w55fa93edma->sg = kmalloc(sgcount * sizeof(S_DRVEDMA_DESCRIPT_FORMAT), GFP_KERNEL);
w55fa93edma->resbytes = dma_length;
// Set channel 0 transfer address and Scatter-Gather
u32Value = inp32(REG_VDMA_CSR);
u32Value = (u32Value & ~SAD_SEL) | (eDRVEDMA_DIRECTION_INCREMENTED << SOURCE_DIRECTION_BIT);
u32Value = (u32Value & ~DAD_SEL) | (eDRVEDMA_DIRECTION_INCREMENTED << DESTINATION_DIRECTION_BIT);
outp32(REG_VDMA_CSR, u32Value);
DrvEDMA_EnableScatterGather(0);
DrvEDMA_SetScatterGatherTblStartAddr(0, virt_to_phys(w55fa93edma->sg));
psSGFmt = w55fa93edma->sg;
u32SrcAddr = src_addr;
u32DestAddr = dest_addr;
u32TranferByte = 0;
do {
u32TranferByte = (w55fa93edma->resbytes >= PAGE_SIZE) ? PAGE_SIZE : w55fa93edma->resbytes;
w55fa93edma->resbytes -= u32TranferByte;
// set source and destination address
psSGFmt->u32SourceAddr = virt_to_phys((void*)u32SrcAddr);
psSGFmt->u32DestAddr = u32DestAddr;
// set stride transfer byte count & byte count
psSGFmt->u32StrideAndByteCount = u32TranferByte;
// set source offset byte length and destination offset byte length
psSGFmt->u32Offset = 0;
// set EOT for last descript format
if (w55fa93edma->resbytes == 0)
psSGFmt->u32Offset |= 0x80000000;
// set next Scatter-Gather table address
//psSGFmt->u32NextSGTblAddr = (unsigned int)(psSGFmt+1);
psSGFmt++;
u32SrcAddr += u32TranferByte;
u32DestAddr += u32TranferByte;
} while (w55fa93edma->resbytes > 0);
return 0;
}
/*---------------------------------------------------------------------------------------------------------*/
void I2S_IRQHandler(void)
{
uint32_t u32Reg;
u32Reg = inpw(&(I2S->I2SSTATUS));
if (u32Reg & I2S_I2STXINT)
{
/* Tx underflow */
if ((u32Reg & I2S_TXUDF) && (I2S->I2SIE.TXUDFIE == 1))
{
if (I2SHandler.TxUnderflowFn)
I2SHandler.TxUnderflowFn(u32Reg);
outp32(&(I2S->I2SSTATUS), I2S_TXUDF);
}
/* Tx overflow */
else if ((u32Reg & I2S_TXOVF) && (I2S->I2SIE.TXOVFIE == 1))
{
if (I2SHandler.TxOverflowFn)
I2SHandler.TxOverflowFn(u32Reg);
outp32(&(I2S->I2SSTATUS), I2S_TXOVF);
}
/* Tx right zero cross */
else if ((u32Reg & I2S_RZCF) && (I2S->I2SIE.RZCIE == 1))
{
if (I2SHandler.TxRightZeroCrossFn)
I2SHandler.TxRightZeroCrossFn(u32Reg);
outp32(&(I2S->I2SSTATUS), I2S_RZCF);
}
/* Tx left zero cross */
else if ((u32Reg & I2S_LZCF) && (I2S->I2SIE.LZCIE == 1))
{
if (I2SHandler.TxLeftZeroCrossFn)
I2SHandler.TxLeftZeroCrossFn(u32Reg);
outp32(&(I2S->I2SSTATUS), I2S_LZCF);
}
/* Tx threshold level */
else if (I2S->I2SIE.TXTHIE == 1)
{
if (I2SHandler.TxFifoThresholdFn)
I2SHandler.TxFifoThresholdFn(u32Reg);
}
}
else if (u32Reg & I2S_I2SRXINT)
{
/* Rx underflow */
if ((u32Reg & I2S_RXUDF) && (I2S->I2SIE.RXUDFIE == 1))
{
if (I2SHandler.RxUnderflowFn)
I2SHandler.RxUnderflowFn(u32Reg);
outp32(&(I2S->I2SSTATUS), I2S_RXUDF);
}
/* Rx overflow */
else if ((u32Reg & I2S_RXOVF) && (I2S->I2SIE.RXOVFIE == 1))
{
if (I2SHandler.RxOverflowFn)
I2SHandler.RxOverflowFn(u32Reg);
outp32(&(I2S->I2SSTATUS), I2S_RXOVF);
}
/* Rx threshold level */
else if (I2S->I2SIE.RXTHIE == 1)
{
if (I2SHandler.RxFifoThresholdFn)
I2SHandler.RxFifoThresholdFn(u32Reg);
}
}
}
void mdp4_overlay_update_lcd(struct msm_fb_data_type *mfd)
{
MDPIBUF *iBuf = &mfd->ibuf;
uint8 *src;
int ptype;
uint32 mddi_ld_param;
uint16 mddi_vdo_packet_reg;
struct mdp4_overlay_pipe *pipe;
int ret;
if (mfd->key != MFD_KEY)
return;
mddi_mfd = mfd; /* keep it */
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
if (mddi_pipe == NULL) {
ptype = mdp4_overlay_format2type(mfd->fb_imgType);
if (ptype < 0)
printk(KERN_INFO "%s: format2type failed\n", __func__);
pipe = mdp4_overlay_pipe_alloc(ptype, FALSE);
if (pipe == NULL)
printk(KERN_INFO "%s: pipe_alloc failed\n", __func__);
pipe->pipe_used++;
pipe->mixer_num = MDP4_MIXER0;
pipe->src_format = mfd->fb_imgType;
mdp4_overlay_panel_mode(pipe->mixer_num, MDP4_PANEL_MDDI);
ret = mdp4_overlay_format2pipe(pipe);
if (ret < 0)
printk(KERN_INFO "%s: format2type failed\n", __func__);
mddi_pipe = pipe; /* keep it */
init_completion(&mddi_delay_comp);
#ifdef MDDI_TIMER
init_timer(&mddi_timer);
mddi_timer.function = mddi_delay_tout;
mddi_timer.data = 0;
#else
init_completion(&mddi_delay_comp);
mdp_intr_mask |= INTR_PRIMARY_READ_PTR;
outp32(MDP_INTR_ENABLE, mdp_intr_mask);
MDP_OUTP(MDP_BASE + 0x0021c, 0x10);
#endif
mddi_pipe->blt_end = 1; /* mark as end */
mddi_ld_param = 0;
mddi_vdo_packet_reg = mfd->panel_info.mddi.vdopkt;
if (mfd->panel_info.type == MDDI_PANEL) {
if (mfd->panel_info.pdest == DISPLAY_1)
mddi_ld_param = 0;
else
mddi_ld_param = 1;
} else {
mddi_ld_param = 2;
}
MDP_OUTP(MDP_BASE + 0x00090, mddi_ld_param);
if (mfd->panel_info.bpp == 24)
MDP_OUTP(MDP_BASE + 0x00094,
(MDDI_VDO_PACKET_DESC_24 << 16) | mddi_vdo_packet_reg);
else if (mfd->panel_info.bpp == 16)
MDP_OUTP(MDP_BASE + 0x00094,
(MDDI_VDO_PACKET_DESC_16 << 16) | mddi_vdo_packet_reg);
else
MDP_OUTP(MDP_BASE + 0x00094,
(MDDI_VDO_PACKET_DESC << 16) | mddi_vdo_packet_reg);
MDP_OUTP(MDP_BASE + 0x00098, 0x01);
} else {
pipe = mddi_pipe;
}
/* 0 for dma_p, client_id = 0 */
MDP_OUTP(MDP_BASE + 0x00090, 0);
src = (uint8 *) iBuf->buf;
#ifdef WHOLESCREEN
{
struct fb_info *fbi;
fbi = mfd->fbi;
pipe->src_height = fbi->var.yres;
pipe->src_width = fbi->var.xres;
pipe->src_h = fbi->var.yres;
pipe->src_w = fbi->var.xres;
pipe->src_y = 0;
pipe->src_x = 0;
pipe->dst_h = fbi->var.yres;
pipe->dst_w = fbi->var.xres;
pipe->dst_y = 0;
pipe->dst_x = 0;
pipe->srcp0_addr = (uint32)src;
pipe->srcp0_ystride = fbi->fix.line_length;
}
#else
if (mdp4_overlay_active(MDP4_MIXER0)) {
struct fb_info *fbi;
fbi = mfd->fbi;
pipe->src_height = fbi->var.yres;
pipe->src_width = fbi->var.xres;
pipe->src_h = fbi->var.yres;
pipe->src_w = fbi->var.xres;
pipe->src_y = 0;
pipe->src_x = 0;
pipe->dst_h = fbi->var.yres;
pipe->dst_w = fbi->var.xres;
pipe->dst_y = 0;
pipe->dst_x = 0;
pipe->srcp0_addr = (uint32) src;
pipe->srcp0_ystride = fbi->fix.line_length;
} else {
/* starting input address */
src += (iBuf->dma_x + iBuf->dma_y * iBuf->ibuf_width)
* iBuf->bpp;
pipe->src_height = iBuf->dma_h;
pipe->src_width = iBuf->dma_w;
pipe->src_h = iBuf->dma_h;
pipe->src_w = iBuf->dma_w;
pipe->src_y = 0;
pipe->src_x = 0;
pipe->dst_h = iBuf->dma_h;
pipe->dst_w = iBuf->dma_w;
pipe->dst_y = iBuf->dma_y;
pipe->dst_x = iBuf->dma_x;
pipe->srcp0_addr = (uint32) src;
pipe->srcp0_ystride = iBuf->ibuf_width * iBuf->bpp;
}
#endif
pipe->mixer_stage = MDP4_MIXER_STAGE_BASE;
mdp4_overlay_rgb_setup(pipe);
mdp4_mixer_stage_up(pipe);
mdp4_overlayproc_cfg(pipe);
mdp4_overlay_dmap_xy(pipe);
mdp4_overlay_dmap_cfg(mfd, 0);
mdp4_mddi_vsync_enable(mfd, pipe, 0);
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
static void mdp_dma2_update_lcd(struct msm_fb_data_type *mfd)
{
MDPIBUF *iBuf = &mfd->ibuf;
int mddi_dest = FALSE;
uint32 outBpp = iBuf->bpp;
uint32 dma2_cfg_reg;
uint8 *src;
uint32 mddi_ld_param;
uint16 mddi_vdo_packet_reg;
uint16 mddi_vdo_packet_descriptor = 0;
struct msm_fb_panel_data *pdata =
(struct msm_fb_panel_data *)mfd->pdev->dev.platform_data;
uint32 ystride = mfd->fbi->fix.line_length;
#if defined(CONFIG_FB_MSM_MDDI_TMD_NT35580)
if (iBuf->dma_h == mfd->panel_info.yres)
mddi_nt35580_lcd_display_on();
#endif
dma2_cfg_reg = DMA_PACK_ALIGN_LSB |
DMA_OUT_SEL_AHB | DMA_IBUF_NONCONTIGUOUS;
#ifdef CONFIG_FB_MSM_MDP22
dma2_cfg_reg |= DMA_PACK_TIGHT;
#endif
#ifdef CONFIG_FB_MSM_MDP30
/*
* Software workaround: On 7x25/7x27, the MDP will not
* respond if dma_w is 1 pixel. Set the update width to
* 2 pixels and adjust the x offset if needed.
*/
if (iBuf->dma_w == 1) {
iBuf->dma_w = 2;
if (iBuf->dma_x == (iBuf->ibuf_width - 2))
iBuf->dma_x--;
}
#endif
if (mfd->fb_imgType == MDP_BGR_565)
dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
else
dma2_cfg_reg |= DMA_PACK_PATTERN_RGB;
if (outBpp == 4)
dma2_cfg_reg |= DMA_IBUF_C3ALPHA_EN;
if (outBpp == 2)
dma2_cfg_reg |= DMA_IBUF_FORMAT_RGB565;
mddi_ld_param = 0;
mddi_vdo_packet_reg = mfd->panel_info.mddi.vdopkt;
if ((mfd->panel_info.type == MDDI_PANEL) ||
(mfd->panel_info.type == EXT_MDDI_PANEL)) {
dma2_cfg_reg |= DMA_OUT_SEL_MDDI;
mddi_dest = TRUE;
if (mfd->panel_info.type == MDDI_PANEL) {
mdp_total_vdopkts++;
if (mfd->panel_info.pdest == DISPLAY_1) {
dma2_cfg_reg |= DMA_MDDI_DMAOUT_LCD_SEL_PRIMARY;
mddi_ld_param = 0;
#if defined(MDDI_HOST_WINDOW_WORKAROUND) \
|| defined(CONFIG_FB_MSM_MDDI_SEMC_LCD_WINDOW_ADJUST)
mddi_window_adjust(mfd, iBuf->dma_x,
iBuf->dma_w - 1, iBuf->dma_y,
iBuf->dma_h - 1);
#endif
} else {
dma2_cfg_reg |=
DMA_MDDI_DMAOUT_LCD_SEL_SECONDARY;
mddi_ld_param = 1;
#if defined(MDDI_HOST_WINDOW_WORKAROUND) \
|| defined(CONFIG_FB_MSM_MDDI_SEMC_LCD_WINDOW_ADJUST)
mddi_window_adjust(mfd, iBuf->dma_x,
iBuf->dma_w - 1, iBuf->dma_y,
iBuf->dma_h - 1);
#endif
}
} else {
dma2_cfg_reg |= DMA_MDDI_DMAOUT_LCD_SEL_EXTERNAL;
mddi_ld_param = 2;
}
} else {
if (mfd->panel_info.pdest == DISPLAY_1) {
dma2_cfg_reg |= DMA_AHBM_LCD_SEL_PRIMARY;
outp32(MDP_EBI2_LCD0, mfd->data_port_phys);
} else {
dma2_cfg_reg |= DMA_AHBM_LCD_SEL_SECONDARY;
outp32(MDP_EBI2_LCD1, mfd->data_port_phys);
}
}
dma2_cfg_reg |= DMA_DITHER_EN;
src = (uint8 *) iBuf->buf;
/* starting input address */
src += iBuf->dma_x * outBpp + iBuf->dma_y * ystride;
mdp_curr_dma2_update_width = iBuf->dma_w;
mdp_curr_dma2_update_height = iBuf->dma_h;
/* SEMC Begin */
#ifdef CONFIG_FB_MSM_MDDI_HITACHI_HVGA_LCD
/* Todo: To be removed!
This is a temporary fix for a HW bug in early driver IC version.
*/
if (pdata->panel_ext->use_dma_edge_pixels_fix == 1) {
struct fb_info *tmp_fbi;
struct fb_fix_screeninfo *tmp_fix;
uint8 *first_packet_in_dma_window_p;
uint8 *last_packet_in_dma_row_p;
int i = 0;
tmp_fbi = mfd->fbi;
tmp_fix = &tmp_fbi->fix;
dma2_cfg_reg &= ~DMA_DITHER_EN;
first_packet_in_dma_window_p = tmp_fbi->screen_base +
(iBuf->dma_x + (iBuf->dma_y + tmp_fbi->var.yoffset) *
iBuf->ibuf_width) * outBpp;
last_packet_in_dma_row_p = first_packet_in_dma_window_p +
(iBuf->dma_w - 1) * outBpp;
for (i=0; i < (iBuf->dma_h - 1); i++) {
/* Check for not allowed data */
if (((last_packet_in_dma_row_p[0] & 0x3F) == 0x2a) ||
((last_packet_in_dma_row_p[0] & 0x3F) == 0x2b)) {
/* clr bit5 */
last_packet_in_dma_row_p[0] &= 0xDF;
}
last_packet_in_dma_row_p += (iBuf->ibuf_width) * outBpp;
}
}
#endif /* CONFIG_FB_MSM_MDDI_HITACHI_HVGA_LCD */
/* SEMC End */
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
#ifdef CONFIG_FB_MSM_MDP22
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0184,
(iBuf->dma_h << 16 | iBuf->dma_w));
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0188, src);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x018C, ystride);
#else
MDP_OUTP(MDP_BASE + 0x90004, (iBuf->dma_h << 16 | iBuf->dma_w));
MDP_OUTP(MDP_BASE + 0x90008, src);
MDP_OUTP(MDP_BASE + 0x9000c, ystride);
#endif
/* adding dynamic setup of register */
if (mfd->panel_info.bpp == 16) {
mddi_vdo_packet_descriptor = 0x5565;
dma2_cfg_reg |= DMA_DSTC0G_6BITS | /* 565 16BPP */
DMA_DSTC1B_5BITS | DMA_DSTC2R_5BITS;
} else if (mfd->panel_info.bpp == 18) {
mddi_vdo_packet_descriptor = 0x5666;
dma2_cfg_reg |= DMA_DSTC0G_6BITS | /* 666 18BPP */
DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
} else {
/* assuming 24 bpp */
mddi_vdo_packet_descriptor = 0x5888;
dma2_cfg_reg |= DMA_DSTC0G_8BITS | /* 888 24BPP */
DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS;
}
if (mddi_dest) {
#ifdef CONFIG_FB_MSM_MDP22
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0194,
(iBuf->dma_y << 16) | iBuf->dma_x);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01a0, mddi_ld_param);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01a4,
(mddi_vdo_packet_descriptor << 16) | mddi_vdo_packet_reg);
#else
MDP_OUTP(MDP_BASE + 0x90010, (iBuf->dma_y << 16) | iBuf->dma_x);
MDP_OUTP(MDP_BASE + 0x00090, mddi_ld_param);
MDP_OUTP(MDP_BASE + 0x00094,
(mddi_vdo_packet_descriptor << 16) | mddi_vdo_packet_reg);
#endif
} else {
/* setting EBI2 LCDC write window */
pdata->set_rect(iBuf->dma_x, iBuf->dma_y, iBuf->dma_w,
iBuf->dma_h);
}
/* dma2 config register */
#ifdef MDP_HW_VSYNC
MDP_OUTP(MDP_BASE + 0x90000, dma2_cfg_reg);
if ((mfd->use_mdp_vsync) &&
(mfd->ibuf.vsync_enable) && (mfd->panel_info.lcd.vsync_enable)) {
uint32 start_y;
if (vsync_start_y_adjust <= iBuf->dma_y)
start_y = iBuf->dma_y - vsync_start_y_adjust;
else
start_y =
(mfd->total_lcd_lines - 1) - (vsync_start_y_adjust -
iBuf->dma_y);
/*
* MDP VSYNC clock must be On by now so, we don't have to
* re-enable it
*/
MDP_OUTP(MDP_BASE + 0x210, start_y);
MDP_OUTP(MDP_BASE + 0x20c, 1); /* enable prim vsync */
} else {
MDP_OUTP(MDP_BASE + 0x20c, 0); /* disable prim vsync */
}
#else
#ifdef CONFIG_FB_MSM_MDP22
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0180, dma2_cfg_reg);
#else
MDP_OUTP(MDP_BASE + 0x90000, dma2_cfg_reg);
#endif
#endif /* MDP_HW_VSYNC */
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
int main (void)
{
SystemInit();
#if 0
if (0x00000004 & inp32(0x40000038)) {
outp32(0x40000038, 0x80000000);
}
else {
Led_flash();
while(1);
}
#endif
/* Initialize GPIO */
gpio_init(cb_gpio);
#if TEST_SLEEP_NORMAL == TRUE
// --------------------------------------------
// sleep wakeup
// --------------------------------------------
//set all pin to gpio
syscon_SetPMCR0(QN_SYSCON, 0x00000000);
syscon_SetPMCR1(QN_SYSCON, 0x00000000);
//set all gpio input
gpio_set_direction_field(GPIO_PIN_ALL, GPIO_INPUT);
gpio_write_pin_field(GPIO_PIN_ALL, (uint32_t)GPIO_HIGH);
// pin pull ( 00 : High-Z, 01 : Pull-down, 10 : Pull-up, 11 : Reserved )
syscon_SetPPCR0(QN_SYSCON, 0xAAAA5AAA); // SWD pull-down save 20uA
syscon_SetPPCR1(QN_SYSCON, 0x2AAAAAAA);
// power down BUCK needed
syscon_SetIvrefX32WithMask(QN_SYSCON, SYSCON_MASK_BUCK_BYPASS|SYSCON_MASK_BUCK_DPD, MASK_ENABLE);
// power down Flash
syscon_SetPGCR2WithMask(QN_SYSCON, SYSCON_MASK_FLASH_VCC_EN, MASK_DISABLE);
// enable dbg power down
syscon_SetPGCR2WithMask(QN_SYSCON, SYSCON_MASK_DBGPMUENABLE, MASK_ENABLE);
// dis sar adc buffer
syscon_SetPGCR1WithMask(QN_SYSCON, SYSCON_MASK_DIS_SAR_BUF, MASK_ENABLE);
Led_flash();
do {
delay(10);
} while (gpio_read_pin(GPIO_P14) == GPIO_HIGH);
sleep_init();
wakeup_by_sleep_timer(__32K_TYPE);
wakeup_by_gpio(GPIO_P15, GPIO_WKUP_BY_LOW);
do {
gpio_set_direction(GPIO_P01, GPIO_INPUT);
//enter_sleep(SLEEP_NORMAL, WAKEUP_BY_GPIO, Led_flash);
if (wakeup_from_sleeptimer) {
sleep_timer_set(32000);
wakeup_from_sleeptimer = 0;
#if QN_32K_RCO == TRUE
clock_32k_correction_enable(clock_32k_correction_cb);
#endif
}
#if QN_32K_RCO == TRUE
if (gpio_sleep_allowed() && !dev_get_bf())
#else
if (gpio_sleep_allowed())
#endif
enter_sleep(SLEEP_NORMAL, WAKEUP_BY_OSC_EN|WAKEUP_BY_GPIO, Led_flash);
} while(1);
#endif
#if TEST_SLEEP_DEEP == TRUE
// --------------------------------------------
// deep sleep wakeup
// --------------------------------------------
//set all pin to gpio
syscon_SetPMCR0(QN_SYSCON, 0x00000000);
syscon_SetPMCR1(QN_SYSCON, 0x00000000);
//set all gpio input
gpio_set_direction_field(GPIO_PIN_ALL, (uint32_t)GPIO_INPUT);
gpio_write_pin_field(GPIO_PIN_ALL, (uint32_t)GPIO_HIGH);
// pin pull ( 00 : High-Z, 01 : Pull-down, 10 : Pull-up, 11 : Reserved )
syscon_SetPPCR0(QN_SYSCON, 0xAAAA5AAA); // SWD pull-down save 20uA
syscon_SetPPCR1(QN_SYSCON, 0x2AAAAAAA);
// power down BUCK needed
syscon_SetIvrefX32WithMask(QN_SYSCON, SYSCON_MASK_BUCK_BYPASS|SYSCON_MASK_BUCK_DPD, MASK_ENABLE);
// power down Flash
syscon_SetPGCR2WithMask(QN_SYSCON, SYSCON_MASK_FLASH_VCC_EN, MASK_DISABLE);
// enable dbg power down
syscon_SetPGCR2WithMask(QN_SYSCON, SYSCON_MASK_DBGPMUENABLE, MASK_ENABLE);
// dis sar adc buffer
syscon_SetPGCR1WithMask(QN_SYSCON, SYSCON_MASK_DIS_SAR_BUF, MASK_ENABLE);
Led_flash();
do {
delay(10);
} while (gpio_read_pin(GPIO_P14) == GPIO_HIGH);
sleep_init();
do {
gpio_set_direction(GPIO_P01, GPIO_INPUT);
wakeup_by_gpio(GPIO_P15, GPIO_WKUP_BY_CHANGE);
enter_sleep(SLEEP_DEEP, WAKEUP_BY_GPIO, Led_flash);
} while(1);
#endif
#if TEST_SLEEP_CPU_CLK_OFF == TRUE
// --------------------------------------------
// clock gating
// --------------------------------------------
// Set timer 0 wakeup
timer_init(QN_TIMER0, NULL);
timer_config(QN_TIMER0, TIMER_PSCAL_DIV, TIMER_COUNT_MS(1000, TIMER_PSCAL_DIV));
timer_enable(QN_TIMER0, MASK_ENABLE);
sleep_init();
do {
enter_sleep(SLEEP_CPU_CLK_OFF, WAKEUP_BY_TIMER0, NULL);
Led_flash();
}
while(1);
#endif
}
//debug
void hisifb_disreset_dss(struct hisi_fb_data_type *hisifd)
{
char __iomem *peri_crg_base = hisifd->peri_crg_base;
////////////////////////////////////////////////////////////////////////////
//
// VIVO BUS POWERUP
//
//1:module clk enable
//PLL2 16div
outp32(peri_crg_base + CLKDIV10, 0x0f800780);
//PLL3 16div 100M
outp32(peri_crg_base + CLKDIV10, 0x30003000);
//gt_clk_vivobus
outp32(peri_crg_base + CLKDIV20, 0x00020002);
//gt_clk_vivobus2ddrc
outp32(peri_crg_base + PEREN0, 0x00001000);
//2:module unrst: ip_rst_vivobus
outp32(peri_crg_base + PERRSTDIS0, 0x00000040);
////////////////////////////////////////////////////////////////////////////
//
// DSS POWERUP
//
//1:module mtcmos on, dsssubsyspwren
outp32(peri_crg_base + PERPWREN, 0x00000020);
//udelay(100);
mdelay(1);
//Fix bug
//2:vivo bus module clk enable, //PLL3 16div
outp32(peri_crg_base + CLKDIV10, 0x0F800780);
//before div: gt_clk_edc0 gt_clk_ldi1 gt_clk_ldi0
outp32(peri_crg_base + CLKDIV18, 0x01C001C0);
//after div: gt_clk_edc0, gt_clk_ldi0, gt_clk_ldi1
//gt_aclk_dss, gt_pclk_dss
outp32(peri_crg_base + PEREN3, 0x0002F000);
//udelay(1);
mdelay(1);
//3:module clk disable
outp32(peri_crg_base + PERDIS3, 0x0002F000);
outp32(peri_crg_base + CLKDIV18, 0x01C00000);
//udelay(1);
mdelay(1);
//4:module iso disable, dsssubsysisoen
outp32(peri_crg_base + ISODIS, 0x00000040);
//5:memory rempair
//6:module unrst, ip_prst_dss ip_rst_dss
outp32(peri_crg_base + PERRSTDIS3, 0x00000C00);
outp32(peri_crg_base + PERRSTDIS2, 0x00000001);
//7:module clk enable, sc_div_vivobus, 3 div, PLL3 ????
outp32(peri_crg_base + CLKDIV10, 0x0f800100); //533M
//outp32(peri_crg_base + CLKDIV10, 0x3f800100); //480M
//gt_clk_edc0, gt_clk_ldi1, gt_clk_ldi0
outp32(peri_crg_base + CLKDIV18, 0x01C001C0);
//after div: gt_clk_edc0, gt_clk_ldi0, gt_clk_ldi1
//gt_aclk_dss, gt_pclk_dss
outp32(peri_crg_base + PEREN3, 0x0002F000);
}
static irqreturn_t irq_handler(int irq, void *dev_id, struct pt_regs *r)
{
UINT32 u32IntStatus;
u32FrameNumber = u32FrameNumber+1;
/* Useless to fix FSC bug
if(videoIn_buf[0].u32PhysAddr != videoIn_buf[5].u32PhysAddr)
{//Fix FSC bug
if( inp32(REG_FSC0_WBUF) == videoIn_buf[0].u32PhysAddr)
{
DrvVideoIn_SetBaseStartAddress(eDRVVIDEOIN_PACKET, 0, videoIn_buf[5].u32PhysAddr);
}
else if ( inp32(REG_FSC0_WBUF) == videoIn_buf[1].u32PhysAddr)
{
DrvVideoIn_SetBaseStartAddress(eDRVVIDEOIN_PACKET, 1, videoIn_buf[6].u32PhysAddr);
}
else if ( inp32(REG_FSC0_WBUF) == videoIn_buf[2].u32PhysAddr)
{
DrvVideoIn_SetBaseStartAddress(eDRVVIDEOIN_PACKET, 2, videoIn_buf[7].u32PhysAddr);
}
}
*/
#ifndef CONFIG_FSC
if(inp32( REG_VPECTL ) & PKEN)
{//Packet pipe enable
if( inp32(REG_PACBA0) == vinPackAddr0)
{
DrvVideoIn_SetBaseStartAddress(eDRVVIDEOIN_PACKET, 0, vinPackAddr1);
w55fa93_VIN_PAC_BUFFER = videoIn_buf[0].u32PhysAddr;
}
else if ( inp32(REG_PACBA0) == vinPackAddr1)
{
DrvVideoIn_SetBaseStartAddress(eDRVVIDEOIN_PACKET, 0, vinPackAddr2);
w55fa93_VIN_PAC_BUFFER = videoIn_buf[1].u32PhysAddr;
}
else if ( inp32(REG_PACBA0) == vinPackAddr2)
{
DrvVideoIn_SetBaseStartAddress(eDRVVIDEOIN_PACKET, 0, vinPackAddr0);
w55fa93_VIN_PAC_BUFFER = videoIn_buf[2].u32PhysAddr;
}
}
#endif
if(inp32(REG_YBA0) == w55fa93_JPG_Y0_ADDR )
{//Current use YUV 0. Switch to another one buffer
DrvVideoIn_SetBaseStartAddress(eDRVVIDEOIN_PLANAR, 0, w55fa93_JPG_Y1_ADDR);
DrvVideoIn_SetBaseStartAddress(eDRVVIDEOIN_PLANAR, 1, w55fa93_JPG_U1_ADDR);
DrvVideoIn_SetBaseStartAddress(eDRVVIDEOIN_PLANAR, 2, w55fa93_JPG_V1_ADDR);
//Buffer 0 is valid for JEPG
w55fa93_JPG_Y_ADDR = w55fa93_JPG_Y0_ADDR;
w55fa93_JPG_U_ADDR = w55fa93_JPG_U0_ADDR;
w55fa93_JPG_V_ADDR = w55fa93_JPG_V0_ADDR;
}
else
{
DrvVideoIn_SetBaseStartAddress(eDRVVIDEOIN_PLANAR, 0, w55fa93_JPG_Y0_ADDR);
DrvVideoIn_SetBaseStartAddress(eDRVVIDEOIN_PLANAR, 1, w55fa93_JPG_U0_ADDR);
DrvVideoIn_SetBaseStartAddress(eDRVVIDEOIN_PLANAR, 2, w55fa93_JPG_V0_ADDR);
//Buffer 1 is valid for JEPG
w55fa93_JPG_Y_ADDR = w55fa93_JPG_Y1_ADDR;
w55fa93_JPG_U_ADDR = w55fa93_JPG_U1_ADDR;
w55fa93_JPG_V_ADDR = w55fa93_JPG_V1_ADDR;
}
DrvVideoIn_SetShadowRegister();
u32IntStatus = inp32(REG_VPEINT);
if( (u32IntStatus & (VINTEN | VINT)) == (VINTEN | VINT))
outp32(REG_VPEINT, (u32IntStatus & ~(MDINT | ADDRMINT | MEINT))); /* Clear Frame end interrupt */
else if((u32IntStatus & (ADDRMEN|ADDRMINT)) == (ADDRMEN|ADDRMINT))
outp32(REG_VPEINT, (u32IntStatus & ~(MDINT | VINT | MEINT))); /* Clear Address match interrupt */
else if ((u32IntStatus & (MEINTEN|MEINT)) == (MEINTEN|MEINT))
outp32(REG_VPEINT, (u32IntStatus & ~(MDINT | VINT|ADDRMINT))); /* Clear Memory error interrupt */
else if ((u32IntStatus & (MDINTEN|MDINT)) == (MDINTEN|MDINT))
outp32(REG_VPEINT, (u32IntStatus & ~( VINT | MEINT | ADDRMINT))); /* Clear Memory error interrupt */
wake_up_interruptible(&videoin_wq);
return IRQ_HANDLED;
}
static int __devinit jdi_probe(struct platform_device *pdev)
{
struct k3_panel_info *pinfo = NULL;
struct platform_device *reg_pdev = NULL;
struct lcd_properities lcd_props;
struct k3_fb_data_type *k3fd = NULL;
int i;
g_display_on = false;
pinfo = jdi_panel_data.panel_info;
/* init lcd panel info */
pinfo->xres = 720;
pinfo->yres = 1280;
pinfo->width = 58;
pinfo->height = 103;
pinfo->type = PANEL_MIPI_CMD;
pinfo->orientation = LCD_PORTRAIT;
pinfo->bpp = EDC_OUT_RGB_888;
pinfo->s3d_frm = EDC_FRM_FMT_2D;
pinfo->bgr_fmt = EDC_RGB;
pinfo->bl_set_type = BL_SET_BY_MIPI;
pinfo->bl_min = 1;
pinfo->bl_max = 100;
pinfo->frc_enable = 1;
pinfo->esd_enable = 1;
pinfo->sbl_enable = 1;
pinfo->sbl.bl_max = 0xff;
pinfo->sbl.cal_a = 0x08;
pinfo->sbl.cal_b = 0xd8;
pinfo->sbl.str_limit = 0x40;
pinfo->ldi.h_back_porch = 43;
pinfo->ldi.h_front_porch = 80;
pinfo->ldi.h_pulse_width = 57;
pinfo->ldi.v_back_porch = 12;
pinfo->ldi.v_front_porch = 14;
pinfo->ldi.v_pulse_width = 2;
pinfo->ldi.hsync_plr = 1;
pinfo->ldi.vsync_plr = 0;
pinfo->ldi.pixelclk_plr = 1;
pinfo->ldi.data_en_plr = 0;
pinfo->ldi.disp_mode = LDI_DISP_MODE_NOT_3D_FBF;
/* Note: must init here */
pinfo->frame_rate = 60;
pinfo->clk_rate = 76000000;
pinfo->mipi.lane_nums = DSI_4_LANES;
pinfo->mipi.color_mode = DSI_24BITS_1;
pinfo->mipi.vc = 0;
pinfo->mipi.dsi_bit_clk = 241;
/* tp vcc init */
vcc_cmds_tx(pdev, jdi_tp_vcc_init_cmds, \
ARRAY_SIZE(jdi_tp_vcc_init_cmds));
/* lcd vcc init */
vcc_cmds_tx(pdev, jdi_lcd_vcc_init_cmds, \
ARRAY_SIZE(jdi_lcd_vcc_init_cmds));
/*tk vcc init*/
g_touchkey_enable = get_touchkey_enable();
if (g_touchkey_enable == true) {
vcc_cmds_tx(pdev, jdi_tk_vcc_init_cmds, \
ARRAY_SIZE(jdi_tk_vcc_init_cmds));
}
/* tp iomux init */
iomux_cmds_tx(jdi_tp_iomux_init_cmds, \
ARRAY_SIZE(jdi_tp_iomux_init_cmds));
/* lcd iomux init */
iomux_cmds_tx(jdi_lcd_iomux_init_cmds, \
ARRAY_SIZE(jdi_lcd_iomux_init_cmds));
/* alloc panel device data */
if (platform_device_add_data(pdev, &jdi_panel_data,
sizeof(struct k3_fb_panel_data))) {
k3fb_loge("platform_device_add_data failed!\n");
platform_device_put(pdev);
return -ENOMEM;
}
reg_pdev = k3_fb_add_device(pdev);
k3fd = (struct k3_fb_data_type *)platform_get_drvdata(reg_pdev);
BUG_ON(k3fd == NULL);
/* read product id */
msleep(16); //TE masked in k3_fb_register(), wait 16ms for on-going refreshing
for(i = 0; i < 150; i++){
outp32(k3fd->edc_base + MIPIDSI_GEN_HDR_OFFSET, 0xDA << 8 | 0x06);
udelay(120);
lcd_product_id = inp32(k3fd->edc_base + MIPIDSI_GEN_PLD_DATA_OFFSET);
if(lcd_product_id && (lcd_product_id != 0xff))
break;
}
printk("lcd product id is 0x%x, read times is %d\n", lcd_product_id, i);
sema_init(&ct_sem, 1);
g_csc_value[0] = 0;
g_csc_value[1] = 0;
g_csc_value[2] = 0;
g_csc_value[3] = 0;
g_csc_value[4] = 0;
g_csc_value[5] = 0;
g_csc_value[6] = 0;
g_csc_value[7] = 0;
g_csc_value[8] = 0;
g_is_csc_set = 0;
/* for cabc */
lcd_props.type = TFT;
lcd_props.default_gamma = GAMMA25;
p_tuning_dev = lcd_tuning_dev_register(&lcd_props, &sp_tuning_ops, (void *)reg_pdev);
if (IS_ERR(p_tuning_dev)) {
k3fb_loge("lcd_tuning_dev_register failed!\n");
return -1;
}
jdi_sysfs_init(pdev);
return 0;
}
static void mdp_dma2_update_lcd(struct msm_fb_data_type *mfd)
{
MDPIBUF *iBuf = &mfd->ibuf;
int mddi_dest = FALSE;
int cmd_mode = FALSE;
uint32 outBpp = iBuf->bpp;
uint32 dma2_cfg_reg;
uint8 *src;
uint32 mddi_ld_param;
uint16 mddi_vdo_packet_reg;
#ifndef CONFIG_FB_MSM_MDP303
struct msm_fb_panel_data *pdata =
(struct msm_fb_panel_data *)mfd->pdev->dev.platform_data;
#endif
uint32 ystride = mfd->fbi->fix.line_length;
uint32 mddi_pkt_desc;
dma2_cfg_reg = DMA_PACK_ALIGN_LSB |
DMA_OUT_SEL_AHB | DMA_IBUF_NONCONTIGUOUS;
#ifdef CONFIG_FB_MSM_MDP22
dma2_cfg_reg |= DMA_PACK_TIGHT;
#endif
#ifdef CONFIG_FB_MSM_MDP30
/*
* Software workaround: On 7x25/7x27, the MDP will not
* respond if dma_w is 1 pixel. Set the update width to
* 2 pixels and adjust the x offset if needed.
*/
if (iBuf->dma_w == 1) {
iBuf->dma_w = 2;
if (iBuf->dma_x == (iBuf->ibuf_width - 2))
iBuf->dma_x--;
}
#endif
if (mfd->fb_imgType == MDP_BGR_565)
dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
else if (mfd->fb_imgType == MDP_RGBA_8888)
dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
else
dma2_cfg_reg |= DMA_PACK_PATTERN_RGB;
if (outBpp == 4) {
dma2_cfg_reg |= DMA_IBUF_C3ALPHA_EN;
dma2_cfg_reg |= DMA_IBUF_FORMAT_xRGB8888_OR_ARGB8888;
}
if (outBpp == 2)
dma2_cfg_reg |= DMA_IBUF_FORMAT_RGB565;
mddi_ld_param = 0;
mddi_vdo_packet_reg = mfd->panel_info.mddi.vdopkt;
if ((mfd->panel_info.type == MDDI_PANEL) ||
(mfd->panel_info.type == EXT_MDDI_PANEL)) {
dma2_cfg_reg |= DMA_OUT_SEL_MDDI;
mddi_dest = TRUE;
if (mfd->panel_info.type == MDDI_PANEL) {
mdp_total_vdopkts++;
if (mfd->panel_info.pdest == DISPLAY_1) {
dma2_cfg_reg |= DMA_MDDI_DMAOUT_LCD_SEL_PRIMARY;
mddi_ld_param = 0;
#ifdef MDDI_HOST_WINDOW_WORKAROUND
mddi_window_adjust(mfd, iBuf->dma_x,
iBuf->dma_w - 1, iBuf->dma_y,
iBuf->dma_h - 1);
#endif
} else {
dma2_cfg_reg |=
DMA_MDDI_DMAOUT_LCD_SEL_SECONDARY;
mddi_ld_param = 1;
#ifdef MDDI_HOST_WINDOW_WORKAROUND
mddi_window_adjust(mfd, iBuf->dma_x,
iBuf->dma_w - 1, iBuf->dma_y,
iBuf->dma_h - 1);
#endif
}
} else {
dma2_cfg_reg |= DMA_MDDI_DMAOUT_LCD_SEL_EXTERNAL;
mddi_ld_param = 2;
}
#ifdef CONFIG_FB_MSM_MDP303
} else if (mfd->panel_info.type == MIPI_CMD_PANEL) {
cmd_mode = TRUE;
dma2_cfg_reg |= DMA_OUT_SEL_DSI_CMD;
#endif
} else {
if (mfd->panel_info.pdest == DISPLAY_1) {
dma2_cfg_reg |= DMA_AHBM_LCD_SEL_PRIMARY;
outp32(MDP_EBI2_LCD0, mfd->data_port_phys);
} else {
dma2_cfg_reg |= DMA_AHBM_LCD_SEL_SECONDARY;
outp32(MDP_EBI2_LCD1, mfd->data_port_phys);
}
}
src = (uint8 *) iBuf->buf;
/* starting input address */
src += iBuf->dma_x * outBpp + iBuf->dma_y * ystride;
mdp_curr_dma2_update_width = iBuf->dma_w;
mdp_curr_dma2_update_height = iBuf->dma_h;
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
#ifdef CONFIG_FB_MSM_MDP22
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0184,
(iBuf->dma_h << 16 | iBuf->dma_w));
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0188, src);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x018C, ystride);
#else
if (cmd_mode)
MDP_OUTP(MDP_BASE + 0x90004,
(mfd->panel_info.yres << 16 | mfd->panel_info.xres));
else
MDP_OUTP(MDP_BASE + 0x90004, (iBuf->dma_h << 16 | iBuf->dma_w));
MDP_OUTP(MDP_BASE + 0x90008, src);
MDP_OUTP(MDP_BASE + 0x9000c, ystride);
#endif
if (mfd->panel_info.bpp == 18) {
mddi_pkt_desc = MDDI_VDO_PACKET_DESC;
dma2_cfg_reg |= DMA_DSTC0G_6BITS | /* 666 18BPP */
DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
} else if (mfd->panel_info.bpp == 24) {
mddi_pkt_desc = MDDI_VDO_PACKET_DESC_24;
dma2_cfg_reg |= DMA_DSTC0G_8BITS | /* 888 24BPP */
DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS;
} else {
mddi_pkt_desc = MDDI_VDO_PACKET_DESC_16;
dma2_cfg_reg |= DMA_DSTC0G_6BITS | /* 565 16BPP */
DMA_DSTC1B_5BITS | DMA_DSTC2R_5BITS;
}
#ifndef CONFIG_FB_MSM_MDP303
if (mddi_dest) {
#ifdef CONFIG_FB_MSM_MDP22
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0194,
(iBuf->dma_y << 16) | iBuf->dma_x);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01a0, mddi_ld_param);
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01a4,
(mddi_pkt_desc << 16) | mddi_vdo_packet_reg);
#else
MDP_OUTP(MDP_BASE + 0x90010, (iBuf->dma_y << 16) | iBuf->dma_x);
MDP_OUTP(MDP_BASE + 0x00090, mddi_ld_param);
MDP_OUTP(MDP_BASE + 0x00094,
(mddi_pkt_desc << 16) | mddi_vdo_packet_reg);
#endif
} else {
/* setting EBI2 LCDC write window */
pdata->set_rect(iBuf->dma_x, iBuf->dma_y, iBuf->dma_w,
iBuf->dma_h);
}
#else
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
/* dma_p = 0, dma_s = 1 */
MDP_OUTP(MDP_BASE + 0xF1000, 0x10);
/* enable dsi trigger on dma_p */
MDP_OUTP(MDP_BASE + 0xF1004, 0x01);
}
#endif
/* dma2 config register */
#ifdef MDP_HW_VSYNC
MDP_OUTP(MDP_BASE + 0x90000, dma2_cfg_reg);
if ((mfd->use_mdp_vsync) &&
(mfd->ibuf.vsync_enable) && (mfd->panel_info.lcd.vsync_enable)) {
uint32 start_y;
if (vsync_start_y_adjust <= iBuf->dma_y)
start_y = iBuf->dma_y - vsync_start_y_adjust;
else
start_y =
(mfd->total_lcd_lines - 1) - (vsync_start_y_adjust -
iBuf->dma_y);
/*
* MDP VSYNC clock must be On by now so, we don't have to
* re-enable it
*/
MDP_OUTP(MDP_BASE + 0x210, start_y);
MDP_OUTP(MDP_BASE + 0x20c, 1); /* enable prim vsync */
} else {
MDP_OUTP(MDP_BASE + 0x20c, 0); /* disable prim vsync */
}
#else
#ifdef CONFIG_FB_MSM_MDP22
MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0180, dma2_cfg_reg);
#else
MDP_OUTP(MDP_BASE + 0x90000, dma2_cfg_reg);
#endif
#endif /* MDP_HW_VSYNC */
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
static int ebi2_lcd_probe(struct platform_device *pdev)
{
struct msm_fb_data_type *mfd;
struct platform_device *mdp_dev = NULL;
struct msm_fb_panel_data *pdata = NULL;
int rc, i;
if (pdev->id == 0) {
for (i = 0; i < pdev->num_resources; i++) {
if (!strncmp(pdev->resource[i].name, "base", 4)) {
ebi2_base = ioremap(pdev->resource[i].start,
pdev->resource[i].end -
pdev->resource[i].start + 1);
if (!ebi2_base) {
printk(KERN_ERR
"ebi2_base ioremap failed!\n");
return -ENOMEM;
}
ebi2_lcd_cfg0 = (void *)(ebi2_base + 0x20);
ebi2_lcd_cfg1 = (void *)(ebi2_base + 0x24);
} else if (!strncmp(pdev->resource[i].name,
"lcd01", 5)) {
lcd01_base = ioremap(pdev->resource[i].start,
pdev->resource[i].end -
pdev->resource[i].start + 1);
if (!lcd01_base) {
printk(KERN_ERR
"lcd01_base ioremap failed!\n");
return -ENOMEM;
}
} else if (!strncmp(pdev->resource[i].name,
"lcd02", 5)) {
lcd02_base = ioremap(pdev->resource[i].start,
pdev->resource[i].end -
pdev->resource[i].start + 1);
if (!lcd02_base) {
printk(KERN_ERR
"lcd02_base ioremap failed!\n");
return -ENOMEM;
}
}
}
ebi2_lcd_resource_initialized = 1;
return 0;
}
if (!ebi2_lcd_resource_initialized)
return -EPERM;
mfd = platform_get_drvdata(pdev);
if (!mfd)
return -ENODEV;
if (mfd->key != MFD_KEY)
return -EINVAL;
if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST)
return -ENOMEM;
if (ebi2_base == NULL)
return -ENOMEM;
mdp_dev = platform_device_alloc("mdp", pdev->id);
if (!mdp_dev)
return -ENOMEM;
mfd->pdev = mdp_dev;
mfd->dest = DISPLAY_LCD;
if (platform_device_add_data
(mdp_dev, pdev->dev.platform_data,
sizeof(struct msm_fb_panel_data))) {
printk(KERN_ERR "ebi2_lcd_probe: platform_device_add_data failed!\n");
platform_device_put(mdp_dev);
return -ENOMEM;
}
pdata = mdp_dev->dev.platform_data;
pdata->on = panel_next_on;
pdata->off = panel_next_off;
pdata->next = pdev;
mfd->panel_info = pdata->panel_info;
if (mfd->panel_info.bpp == 24)
mfd->fb_imgType = MDP_RGB_888;
else
mfd->fb_imgType = MDP_RGB_565;
if (mfd->panel_info.pdest == DISPLAY_1) {
outp32(ebi2_base,
(inp32(ebi2_base) & (~(EBI2_PRIM_LCD_CLR))) |
EBI2_PRIM_LCD_SEL);
outp32(ebi2_lcd_cfg0, mfd->panel_info.wait_cycle);
if (mfd->panel_info.bpp == 18)
outp32(ebi2_lcd_cfg1, 0x01000000);
else
outp32(ebi2_lcd_cfg1, 0x0);
} else {
#ifdef DEBUG_EBI2_LCD
outp32(ebi2_base, (inp32(ebi2_base)&(~(EBI2_SECD_LCD_CLR)))
|EBI2_SECD_LCD_SEL);
#endif
}
if (mfd->panel_info.pdest == DISPLAY_1) {
mfd->cmd_port = lcd01_base;
mfd->data_port =
(void *)((uint32) mfd->cmd_port + EBI2_PRIM_LCD_RS_PIN);
mfd->data_port_phys =
(void *)(LCD_PRIM_BASE_PHYS + EBI2_PRIM_LCD_RS_PIN);
} else {
mfd->cmd_port = lcd01_base;
mfd->data_port =
(void *)((uint32) mfd->cmd_port + EBI2_SECD_LCD_RS_PIN);
mfd->data_port_phys =
(void *)(LCD_SECD_BASE_PHYS + EBI2_SECD_LCD_RS_PIN);
}
platform_set_drvdata(mdp_dev, mfd);
rc = platform_device_add(mdp_dev);
if (rc) {
goto ebi2_lcd_probe_err;
}
pdev_list[pdev_list_cnt++] = pdev;
return 0;
ebi2_lcd_probe_err:
platform_device_put(mdp_dev);
return rc;
}
