void board_init_f(ulong bootflag) { u32 plat_ratio, ddr_ratio; unsigned long bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000; NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); /* Initialize the DDR3 */ sdram_init(); /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. */ relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, CONFIG_SYS_NAND_U_BOOT_RELOC); }
void spl_boot(void) { void (*uboot)(void); /* * Init hardware */ gpio_init(); serial_init(); serial_puts("\n\nMSC Secondary Program Loader\n"); sdram_init(); /* * Load U-Boot image from NAND into RAM */ mmc_load(CFG_MSC_U_BOOT_SIZE, (uchar *)CFG_MSC_U_BOOT_DST); uboot = (void (*)(void))CFG_NAND_U_BOOT_START; serial_puts("Starting U-Boot ...\n"); /* * Flush caches */ flush_cache_all(); /* * Jump to U-Boot image */ (*uboot)(); }
void main(void) { timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); tsadc_init(); /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); timestamp_add_now(TS_BEFORE_INITRAM); sdram_init(get_sdram_config()); timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); cbmem_initialize_empty(); timestamp_add_now(TS_END_ROMSTAGE); run_ramstage(); }
int mymain(void) { // beep off GPBCON = 0x1; // output GPBDAT = 0x0; // Tout = 0; // watchdog timer off WTCON = 0; uart_init(); uart_putchar('a'); sdram_init(); *(int *)TEST = 0x12345678; print_addr(TEST); while (1) { char c; c = uart_getchar(); uart_putchar(c); } while (1); return 0; }
long int initdram (int board_type) { volatile immap_t *im = (immap_t *)CFG_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; /* DDR SDRAM - Main SODIMM */ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) msize = spd_sdram(); #else msize = fixed_sdram(); #endif /* * Initialize SDRAM if it is on local bus. */ sdram_init(); #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. */ ddr_enable_ecc(msize * 1024 * 1024); #endif /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); }
static void main(unsigned long bist) { pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); /* Check all of memory */ #if 0 ram_check(0x00000000, msr.lo); #endif #if 0 static const struct { unsigned long lo, hi; } check_addrs[] = { /* Check 16MB of memory @ 0*/ { 0x00000000, 0x01000000 }, #if TOTAL_CPUS > 1 /* Check 16MB of memory @ 2GB */ { 0x80000000, 0x81000000 }, #endif }; int i; for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { ram_check(check_addrs[i].lo, check_addrs[i].hi); } #endif }
TestDisplay::TestDisplay(WhichDisplay which) : _initStr(NULL), _lcdCfg(NULL), _lcdBoard(P0_27, P0_28), _touch(P0_27, P0_28, P2_25) { switch (which) { case TFT_5: _lcdCfg = new LcdController::Config(LCD_CONFIGURATION_50); _initStr = LCD_INIT_STRING_50; break; case TFT_4_3: _lcdCfg = new LcdController::Config(LCD_CONFIGURATION_43); _initStr = LCD_INIT_STRING_43; break; default: mbed_die(); } if (sdram_init() == 1) { printf("Failed to initialize SDRAM\n"); _framebuffer = 0; } else { _framebuffer = (uint32_t) malloc(_lcdCfg->width * _lcdCfg->height * 2 * 3); // 2 is for 16 bit color, 3 is the number of buffers if (_framebuffer != 0) { memset((uint8_t*)_framebuffer, 0, _lcdCfg->width * _lcdCfg->height * 2 * 3); } } }
static void main(unsigned long bist) { pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); }
static bool sdramiodev_init(struct cyg_devtab_entry *tab) { int stat = sdram_init(); //diag_printf("sdramiodev_init\n"); if ( stat == 0 ) return true; else return false; }
void board_init_f(ulong bootflag) { u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; #ifndef CONFIG_QE ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); #elif defined(CONFIG_P1021RDB) par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); #endif /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); #ifndef CONFIG_QE /* init DDR3 reset signal */ puts("\nDDR & BCM56445 reset... "); __raw_writel(0x02210000, &pgpio->gpdir); __raw_writel(0x00210000, &pgpio->gpodr); __raw_writel(0x00000000, &pgpio->gpdat); udelay(20000); __raw_writel(0x00210000, &pgpio->gpdat); udelay(20000); __raw_writel(0x00000000, &pgpio->gpdir); #elif defined(CONFIG_P1021RDB) /* init DDR3 reset signal CE_PB8 */ out_be32(&par_io[1].cpdir1, 0x00004000); out_be32(&par_io[1].cpodr, 0x00800000); out_be32(&par_io[1].cppar1, 0x00000000); /* reset DDR3 */ out_be32(&par_io[1].cpdat, 0x00800000); udelay(1000); out_be32(&par_io[1].cpdat, 0x00000000); udelay(1000); out_be32(&par_io[1].cpdat, 0x00800000); /* disable the CE_PB8 */ out_be32(&par_io[1].cpdir1, 0x00000000); #endif //sdram_reset(); /* Initialize the DDR3 */ sdram_init(); puts("\nsdram_init ok... "); /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. */ relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, CONFIG_SYS_NAND_U_BOOT_RELOC); }
void board_init_f(ulong dummy) { /* Set global data pointer */ gd = &gdata; /* Setup global info */ #ifndef CONFIG_CMD_BURN gd->arch.gi = &ginfo; #else gd->arch.gi = (struct global_info *)CONFIG_SPL_GINFO_BASE; #endif gpio_init(); #ifndef CONFIG_FPGA /* Init uart first */ enable_uart_clk(); #endif #ifdef CONFIG_SPL_SERIAL_SUPPORT preloader_console_init(); #endif #ifndef CONFIG_FPGA debug("Timer init\n"); timer_init(); #ifdef CONFIG_SPL_REGULATOR_SUPPORT debug("regulator set\n"); spl_regulator_set(); #endif debug("CLK stop\n"); clk_prepare(); debug("PLL init\n"); pll_init(); debug("CLK init\n"); clk_init(); #endif debug("SDRAM init\n"); sdram_init(); debug("SDRAM init ok\n"); #ifdef CONFIG_DDR_TEST ddr_basic_tests(); #endif #ifndef CONFIG_BURNER /* Clear the BSS */ memset(__bss_start, 0, (char *)&__bss_end - __bss_start); debug("board_init_r\n"); board_init_r(NULL, 0); #endif }
static void main(unsigned long bist) { w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); /* ram_check(0, 640 * 1024); */ }
void board_init_f(ulong dummy) { hw_data_init(); early_system_init(); board_early_init_f(); sdram_init(); /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( (void *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); }
phys_size_t initdram (int board_type) { /* * ToDo: Move the asm init routine sdram_init() to this C file, * or even better use some common ppc4xx code available * in cpu/ppc4xx */ sdram_init(); return get_dram_size (); }
int dram_init(void) { #ifndef CONFIG_SKIP_LOWLEVEL_INIT sdram_init(); #endif /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( (void *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); return 0; }
/* * Check if we are executing rtc-only + DDR mode, and resume from it if needed */ static void rtc_only(void) { struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; struct prm_device_inst *prm_device = (struct prm_device_inst *)PRM_DEVICE_INST; u32 scratch1; void (*resume_func)(void); scratch1 = readl(&rtc->scratch1); /* * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only * written to this register when we want to wake up from RTC only * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1: * bits 0-15: RTC_MAGIC_VAL * bits 16-31: board type (needed for sdram_init) */ if ((scratch1 & 0xffff) != RTC_MAGIC_VAL) return; rtc32k_unlock(rtc); /* Clear RTC magic */ writel(0, &rtc->scratch1); /* * Update board type based on value stored on RTC_SCRATCH1, this * is done so that we don't need to read the board type from eeprom * over i2c bus which is expensive */ rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT); /* * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we * are resuming from self-refresh. This avoids an unnecessary re-init * of the DDR. The re-init takes time and we would need to wait for * it to complete before accessing DDR to avoid L3 NOC errors. */ writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl); rtc_only_prcm_init(); sdram_init(); /* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */ writel(0, &prm_device->emif_ctrl); resume_func = (void *)readl(&rtc->scratch0); if (resume_func) resume_func(); }
static void __attribute__((noinline)) romstage(void) { timestamp_init(0); timestamp_add_now(TS_START_ROMSTAGE); console_init(); exception_init(); sdram_init(get_sdram_config()); /* used for MMU and CBMEM setup, in MB */ u32 dram_start_mb = (uintptr_t)_dram/MiB; u32 dram_end_mb = sdram_max_addressable_mb(); u32 dram_size_mb = dram_end_mb - dram_start_mb; configure_l2_cache(); mmu_init(); /* Device memory below DRAM is uncached. */ mmu_config_range(0, dram_start_mb, DCACHE_OFF); /* SRAM is cached. MMU code will round size up to page size. */ mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB), DCACHE_WRITEBACK); /* DRAM is cached. */ mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); /* A window for DMA is uncached. */ mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); /* The space above DRAM is uncached. */ if (dram_end_mb < 4096) mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF); mmu_disable_range(0, 1); dcache_mmu_enable(); /* * A watchdog reset only resets part of the system so it ends up in * a funny state. If that happens, we need to reset the whole machine. */ if (power_reset_status() == POWER_RESET_WATCHDOG) { printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n"); hard_reset(); } /* FIXME: this may require coordination with moving timestamps */ cbmem_initialize_empty(); early_mainboard_init(); run_ramstage(); }
/* do some early init */ void s_init(void) { int in_sdram = 0; #ifdef CONFIG_SPL in_sdram = is_running_in_sdram(); #endif watchdog_init(); sw_gpio_init(); clock_init(); gpio_init(); #ifdef CONFIG_SPL if (!in_sdram) sdram_init(); #endif }
void main(void) { #if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = timestamp_get(); start_romstage_time = timestamp_get(); #endif console_init(); configure_l2ctlr(); tsadc_init(); /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS before_dram_time = timestamp_get(); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time); timestamp_add(TS_BEFORE_INITRAM, before_dram_time); timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif #if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) void *entry = vboot2_load_ramstage(); if (entry != NULL) stage_exit(entry); #endif run_ramstage(); }
PUBLIC void Chip_Init(void) { Chip_Workaround(); if (CHIP_PHY_GetANAChipID() == ANA_CHIP_ID_AA) { set_mem_volt(); set_XOSC32K_config(); } set_chip_clock_freq(); sdram_init(); return; }
void platform_romstage_main(void) { tsadc_init(TSHUT_POL_HIGH); /* Init DVS to conservative values. */ init_dvs_outputs(); prepare_sdmmc(); prepare_usb(); sdram_init(get_sdram_config()); mmu_config_range((void *)0, (uintptr_t)sdram_size_mb() * MiB, CACHED_MEM); mmu_config_range(_dma_coherent, REGION_SIZE(dma_coherent), UNCACHED_MEM); }
void boot(void) { if (warm_reset()) force_emif_self_refresh(); watchdog_init(); mux_init(); enable_uart_clocks(); cons_init(); scale_vcores(); clock_init(); sdram_init(); bzero(__bss_start, __bss_end - __bss_start); timer_init(); storage_init(); }
phys_size_t initdram(int board_type) { long dram_size = 0; puts("Initializing\n"); #if defined(CONFIG_DDR_DLL) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint temp_ddrdll = 0; /* * Work around to stabilize DDR DLL */ temp_ddrdll = gur->ddrdllcr; gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; asm("sync;isync;msync"); } #endif #ifdef CONFIG_SPD_EEPROM dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; #else dram_size = fixed_sdram(); #endif #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. */ ddr_enable_ecc(dram_size); #endif /* * Initialize SDRAM. */ sdram_init(); puts(" DDR: "); return dram_size; }
void romstage(void) { timestamp_add_now(TS_START_ROMSTAGE); console_init(); exception_init(); printk(BIOS_INFO, "T132: romstage here\n"); #if CONFIG_BOOTROM_SDRAM_INIT printk(BIOS_INFO, "T132 romstage: SDRAM init done by BootROM, RAMCODE = %d\n", sdram_get_ram_code()); #else sdram_init(get_sdram_config()); printk(BIOS_INFO, "T132 romstage: sdram_init done\n"); #endif timestamp_add_now(TS_AFTER_INITRAM); /* * Trust Zone needs to be initialized after the DRAM initialization * because carveout registers are programmed during DRAM init. * cbmem_initialize() is dependent on the Trust Zone region * initalization because CBMEM lives right below the Trust Zone which * needs to be properly identified. */ trustzone_region_init(); /* * When romstage is running it's always on the reboot path -- never a * resume path where cbmem recovery is required. Therefore, always * initialize the cbmem area to be empty. */ cbmem_initialize_empty(); ccplex_cpu_prepare(); printk(BIOS_INFO, "T132 romstage: cpu prepare done\n"); ccplex_load_mts(); printk(BIOS_INFO, "T132 romstage: MTS loading done\n"); romstage_mainboard_init(); run_ramstage(); }
int board_early_init_f(void) { /* Enable SDRAM in the EBI mux */ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH); sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); portmux_enable_usart1(PORTMUX_DRIVE_MIN); #if defined(CONFIG_MACB) portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); #endif #if defined(CONFIG_MMC) portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); #endif return 0; }
void main(void) { console_init(); tsadc_init(TSHUT_POL_HIGH); exception_init(); /* Init DVS to conservative values. */ init_dvs_outputs(); prepare_usb(); sdram_init(get_sdram_config()); mmu_config_range((void *)0, (uintptr_t)dram_size, CACHED_MEM); mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); cbmem_initialize_empty(); run_ramstage(); }
long int initdram(int board_type) { long dram_size = 0; extern long spd_sdram (void); volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); #if defined(CONFIG_DDR_DLL) { volatile ccsr_gur_t *gur= &immap->im_gur; uint temp_ddrdll = 0; /* * Work around to stabilize DDR DLL */ temp_ddrdll = gur->ddrdllcr; gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; asm("sync;isync;msync"); } #endif #if defined(CONFIG_SPD_EEPROM) dram_size = spd_sdram (); #else dram_size = fixed_sdram (); #endif #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. */ ddr_enable_ecc(dram_size); #endif /* * Initialize SDRAM. */ sdram_init(); puts(" DDR: "); return dram_size; }
void __bare_init __naked barebox_arm_reset_vector(void) { unsigned long r; arm_cpu_lowlevel_init(); arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12); /* ahb lite ip interface */ writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0); writel(0xdffbfcfb, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1); writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0); writel(0xffffffff, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); if (r > 0xa0000000 && r < 0xc0000000) imx27_barebox_entry(0); /* 399 MHz */ writel(IMX_PLL_PD(0) | IMX_PLL_MFD(51) | IMX_PLL_MFI(7) | IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0); /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ writel(IMX_PLL_PD(1) | IMX_PLL_MFD(12) | IMX_PLL_MFI(9) | IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0); writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART | MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL | MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN | MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) | MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) | MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL | MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL | MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR); sdram_init(); imx27_barebox_boot_nand_external(0); }
phys_size_t initdram(int board_type) { long dram_size = 0; puts("Initializing\n"); #if defined(CONFIG_DDR_DLL) { /* * Work around to stabilize DDR DLL MSYNC_IN. * Errata DDR9 seems to have been fixed. * This is now the workaround for Errata DDR11: * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); gur->ddrdllcr = 0x81000000; asm("sync;isync;msync"); udelay(200); } #endif dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. */ ddr_enable_ecc(dram_size); #endif /* * SDRAM Initialization */ sdram_init(); puts(" DDR: "); return dram_size; }
void nx_hwinit() { enable_clocks(); clock_enable_se(); clock_enable_fuse(1); fuse_disable_program(); mc_enable(); config_oscillators(); _REG(0x70000000, 0x40) = 0; config_gpios(); clock_enable_i2c(I2C_1); clock_enable_i2c(I2C_5); clock_enable(&clock_unk1); clock_enable(&clock_unk2); i2c_init(I2C_1); i2c_init(I2C_5); //Config PMIC (TODO: use max77620.h) i2c_send_byte(I2C_5, 0x3C, 4, 0x40); i2c_send_byte(I2C_5, 0x3C, 0x41, 0x78); i2c_send_byte(I2C_5, 0x3C, 0x43, 0x38); i2c_send_byte(I2C_5, 0x3C, 0x44, 0x3A); i2c_send_byte(I2C_5, 0x3C, 0x45, 0x38); i2c_send_byte(I2C_5, 0x3C, 0x4A, 0xF); i2c_send_byte(I2C_5, 0x3C, 0x4E, 0xC7); i2c_send_byte(I2C_5, 0x3C, 0x4F, 0x4F); i2c_send_byte(I2C_5, 0x3C, 0x50, 0x29); i2c_send_byte(I2C_5, 0x3C, 0x52, 0x1B); i2c_send_byte(I2C_5, 0x3C, 0x16, 42); //42 = (1000 * 1125 - 600000) / 12500 config_pmc_scratch(); CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888 | 0x3333; mc_config_carveout(); sdram_init(); }