Exemplo n.º 1
0
Arquivo: m6809.c Projeto: opicron/mame
void m6809_base_device::check_irq_lines()
{
	if( m_irq_state[M6809_IRQ_LINE] != CLEAR_LINE ||
		m_irq_state[M6809_FIRQ_LINE] != CLEAR_LINE )
		m_int_state &= ~M6809_SYNC; /* clear SYNC flag */
	if( m_irq_state[M6809_FIRQ_LINE]!=CLEAR_LINE && !(CC & CC_IF) )
	{
		/* fast IRQ */
		/* HJB 990225: state already saved by CWAI? */
		if( m_int_state & M6809_CWAI )
		{
			m_int_state &= ~M6809_CWAI;  /* clear CWAI */
			m_extra_cycles += 7;         /* subtract +7 cycles */
		}
		else
		{
			CC &= ~CC_E;                /* save 'short' state */
			PUSHWORD(pPC);
			PUSHBYTE(CC);
			m_extra_cycles += 10;   /* subtract +10 cycles */
		}
		CC |= CC_IF | CC_II;            /* inhibit FIRQ and IRQ */
		PCD=RM16(0xfff6);
		standard_irq_callback(M6809_FIRQ_LINE);
	}
	else
	if( m_irq_state[M6809_IRQ_LINE]!=CLEAR_LINE && !(CC & CC_II) )
	{
		/* standard IRQ */
		/* HJB 990225: state already saved by CWAI? */
		if( m_int_state & M6809_CWAI )
		{
			m_int_state &= ~M6809_CWAI;  /* clear CWAI flag */
			m_extra_cycles += 7;         /* subtract +7 cycles */
		}
		else
		{
			CC |= CC_E;                 /* save entire state */
			PUSHWORD(pPC);
			PUSHWORD(pU);
			PUSHWORD(pY);
			PUSHWORD(pX);
			PUSHBYTE(DP);
			PUSHBYTE(B);
			PUSHBYTE(A);
			PUSHBYTE(CC);
			m_extra_cycles += 19;    /* subtract +19 cycles */
		}
		CC |= CC_II;                    /* inhibit IRQ */
		PCD=RM16(0xfff8);
		standard_irq_callback(M6809_IRQ_LINE);
	}
}
Exemplo n.º 2
0
inline void cosmac_device::dma_output()
{
	m_write_dma((offs_t)R[0], RAM_R(R[0]));

	R[0]++;

	m_icount -= CLOCKS_DMA;

	if (m_dmain)
	{
		m_state = COSMAC_STATE_2_DMA_IN;
	}
	else if (m_dmaout)
	{
		m_state = COSMAC_STATE_2_DMA_OUT;
	}
	else if (IE && m_irq)
	{
		m_state = COSMAC_STATE_3_INT;
	}
	else
	{
		m_state = COSMAC_STATE_0_FETCH;
	}

	standard_irq_callback(COSMAC_INPUT_LINE_DMAOUT);
}
Exemplo n.º 3
0
inline void cosmac_device::dma_input()
{
	RAM_W(R[0], m_read_dma(R[0]));

	R[0]++;

	m_icount -= CLOCKS_DMA;

	if (m_dmain)
	{
		m_state = COSMAC_STATE_2_DMA_IN;
	}
	else if (m_dmaout)
	{
		m_state = COSMAC_STATE_2_DMA_OUT;
	}
	else if (IE && m_irq)
	{
		m_state = COSMAC_STATE_3_INT;
	}
	else if (m_mode == COSMAC_MODE_LOAD)
	{
		m_state = COSMAC_STATE_1_EXECUTE;
	}
	else
	{
		m_state = COSMAC_STATE_0_FETCH;
	}

	standard_irq_callback(COSMAC_INPUT_LINE_DMAIN);
}
Exemplo n.º 4
0
Arquivo: m6805.c Projeto: dinkc64/mame
/* Generate interrupt - m68705 version */
void m68705_device::interrupt()
{
	if ((m_pending_interrupts & ((1 << M6805_IRQ_LINE) | M68705_INT_MASK)) != 0 )
	{
		if ((CC & IFLAG) == 0)
		{
			PUSHWORD(m_pc);
			PUSHBYTE(m_x);
			PUSHBYTE(m_a);
			PUSHBYTE(m_cc);
			SEI;
			standard_irq_callback(0);

			if ((m_pending_interrupts & (1 << M68705_IRQ_LINE)) != 0 )
			{
				m_pending_interrupts &= ~(1 << M68705_IRQ_LINE);
				RM16(0xfffa, &m_pc);
			}
			else if ((m_pending_interrupts & (1 << M68705_INT_TIMER)) != 0)
			{
				m_pending_interrupts &= ~(1 << M68705_INT_TIMER);
				RM16(0xfff8, &m_pc);
			}
		}
		m_icount -= 11;
	}
}
Exemplo n.º 5
0
/* check the IRQ lines for pending interrupts */
void m6800_cpu_device::CHECK_IRQ_LINES()
{
	// TODO: IS3 interrupt

	if (m_nmi_pending)
	{
		if(m_wai_state & M6800_SLP)
			m_wai_state &= ~M6800_SLP;

		m_nmi_pending = FALSE;
		enter_interrupt("M6800 '%s' take NMI\n",0xfffc);
	}
	else
	{
		if( m_irq_state[M6800_IRQ_LINE] != CLEAR_LINE )
		{   /* standard IRQ */
			if(m_wai_state & M6800_SLP)
				m_wai_state &= ~M6800_SLP;

			if( !(CC & 0x10) )
			{
				enter_interrupt("M6800 '%s' take IRQ1\n",0xfff8);
				standard_irq_callback(M6800_IRQ_LINE);
			}
		}
		else
			if( !(CC & 0x10) )
				m6800_check_irq2();
	}
}
Exemplo n.º 6
0
void m68705_device::interrupt()
{
	if (m_pending_interrupts & M68705_INT_MASK)
	{
		if ((CC & IFLAG) == 0)
		{
			pushword(m_pc);
			pushbyte(m_x);
			pushbyte(m_a);
			pushbyte(m_cc);
			SEI;
			standard_irq_callback(0);

			if (BIT(m_pending_interrupts, M68705_IRQ_LINE))
			{
				LOGINT("servicing /INT interrupt\n");
				m_pending_interrupts &= ~(1 << M68705_IRQ_LINE);
				rm16(M68705_VECTOR_INT, m_pc);
			}
			else if (BIT(m_pending_interrupts, M68705_INT_TIMER))
			{
				LOGINT("servicing timer/counter interrupt\n");
				rm16(M68705_VECTOR_TIMER, m_pc);
			}
			else
			{
				throw emu_fatalerror("Unknown pending interrupt");
			}
			m_icount -= 11;
			burn_cycles(11);
		}
	}
}
Exemplo n.º 7
0
void minx_cpu_device::execute_run()
{
	do
	{
		m_curpc = GET_MINX_PC;
		debugger_instruction_hook(this, m_curpc);

		if ( m_interrupt_pending )
		{
			m_halted = 0;
			if ( ! ( m_F & 0xc0 ) && m_U == m_V )
			{
				//logerror("minx_execute(): taking IRQ\n");
				PUSH8( m_V );
				PUSH16( m_PC );
				PUSH8( m_F );

				/* Set Interrupt Branch flag */
				m_F |= 0x80;
				m_V = 0;
				m_PC = rd16( standard_irq_callback( 0 ) << 1 );
				m_icount -= 28;     /* This cycle count is a guess */
			}
		}

		if ( m_halted )
		{
			m_icount -= insnminx_cycles_CE[0xAE];
		}
		else
		{
			execute_one();
		}
	} while ( m_icount > 0 );
}
Exemplo n.º 8
0
/* Generate interrupts */
void m6805_base_device::interrupt()
{
	/* the 6805 latches interrupt requests internally, so we don't clear */
	/* pending_interrupts until the interrupt is taken, no matter what the */
	/* external IRQ pin does. */

	if (BIT(m_pending_interrupts, HD63705_INT_NMI))
	{
		pushword(m_pc);
		pushbyte(m_x);
		pushbyte(m_a);
		pushbyte(m_cc);
		SEI;
		/* no vectors supported, just do the callback to clear irq_state if needed */
		standard_irq_callback(0);

		rm16(0x1ffc, m_pc);
		m_pending_interrupts &= ~(1 << HD63705_INT_NMI);

		m_icount -= 11;
		burn_cycles(11);
	}
	else if ((m_pending_interrupts & ((1 << M6805_IRQ_LINE) | HD63705_INT_MASK)) != 0)
	{
		if ((CC & IFLAG) == 0)
		{
			/* standard IRQ */
			pushword(m_pc);
			pushbyte(m_x);
			pushbyte(m_a);
			pushbyte(m_cc);
			SEI;
			/* no vectors supported, just do the callback to clear irq_state if needed */
			standard_irq_callback(0);

			interrupt_vector();

			m_pending_interrupts &= ~(1 << M6805_IRQ_LINE);

			m_icount -= 11;
			burn_cycles(11);
		}
	}
}
Exemplo n.º 9
0
void ucom4_cpu_device::do_interrupt()
{
	m_icount--;
	push_stack();
	m_pc = 0xf << 2;
	m_int_f = 0;
	m_inte_f = (m_family == NEC_UCOM43) ? 0 : 1;

	standard_irq_callback(0);
}
Exemplo n.º 10
0
void melps4_cpu_device::do_interrupt(int which)
{
	m_inte = 0;
	m_irqflag[which] = false;
	
	m_icount--;
	push_pc();
	m_sms = m_sm;
	m_sm = false;
	m_op = 0; // fake nop
	m_pc = m_int_page << 7 | (which * 2);
	
	standard_irq_callback(which);
}
Exemplo n.º 11
0
Arquivo: v60.cpp Projeto: Fulg/mame
void v60_device::v60_try_irq()
{
	if(m_irq_line == CLEAR_LINE)
		return;
	if((PSW & (1 << 18)) != 0) {
		int vector;
		if(m_irq_line != ASSERT_LINE)
			m_irq_line = CLEAR_LINE;

		vector = standard_irq_callback(0);

		v60_do_irq(vector + 0x40);
	}
}
Exemplo n.º 12
0
void hp_nanoprocessor_device::execute_run()
{
	do {
		// Check for interrupts (interrupt line is always enabled. Masking is done
		// outside of the NP, usually by ANDing the DC7 line with the interrupt
		// request signal)
		if (BIT(m_flags , NANO_I_BIT)) {
			m_reg_ISR = m_reg_PA;
			m_reg_PA = (uint16_t)(standard_irq_callback(0) & 0xff);
			dc_clr(HP_NANO_IE_DC);
			// Vector fetching takes 1 cycle
			m_icount -= 1;
		} else {
			debugger_instruction_hook(this , m_reg_PA);

			uint8_t opcode = fetch();
			execute_one(opcode);
			// All opcodes execute in 2 cycles
			m_icount -= 2;
		}
	} while (m_icount > 0);
}
Exemplo n.º 13
0
void m6800_cpu_device::m6800_check_irq2()
{
	if ((m_tcsr & (TCSR_EICI|TCSR_ICF)) == (TCSR_EICI|TCSR_ICF))
	{
		TAKE_ICI;
		standard_irq_callback(M6801_TIN_LINE);
	}
	else if ((m_tcsr & (TCSR_EOCI|TCSR_OCF)) == (TCSR_EOCI|TCSR_OCF))
	{
		TAKE_OCI;
	}
	else if ((m_tcsr & (TCSR_ETOI|TCSR_TOF)) == (TCSR_ETOI|TCSR_TOF))
	{
		TAKE_TOI;
	}
	else if (((m_trcsr & (M6800_TRCSR_RIE|M6800_TRCSR_RDRF)) == (M6800_TRCSR_RIE|M6800_TRCSR_RDRF)) ||
				((m_trcsr & (M6800_TRCSR_RIE|M6800_TRCSR_ORFE)) == (M6800_TRCSR_RIE|M6800_TRCSR_ORFE)) ||
				((m_trcsr & (M6800_TRCSR_TIE|M6800_TRCSR_TDRE)) == (M6800_TRCSR_TIE|M6800_TRCSR_TDRE)))
	{
		//logerror("M6800 '%s' SCI interrupt\n", tag());
		TAKE_SCI;
	}
}
Exemplo n.º 14
0
inline void cosmac_device::interrupt()
{
	T = (X << 4) | P;
	X = 2;
	P = 1;
	IE = 0;

	m_icount -= CLOCKS_INTERRUPT;

	if (m_dmain)
	{
		m_state = COSMAC_STATE_2_DMA_IN;
	}
	else if (m_dmaout)
	{
		m_state = COSMAC_STATE_2_DMA_OUT;
	}
	else
	{
		m_state = COSMAC_STATE_0_FETCH;
	}

	standard_irq_callback(COSMAC_INPUT_LINE_INT);
}
Exemplo n.º 15
0
void h83008_device::interrupt_taken()
{
	standard_irq_callback(intc->interrupt_taken(taken_irq_vector));
}
Exemplo n.º 16
0
void lc8670_cpu_device::check_irqs()
{
	// update P3 interrupt
	check_p3int();

	if (m_irq_flag && !m_after_reti)
	{
		int irq = 0;
		UINT8 priority = 0;

		// highest priority IRQ
		if (!(REG_IE & 0x01) && (m_irq_flag & 0x02))
		{
			irq = 0x01;
			priority = 2;
		}
		else if (!(REG_IE & 0x02) && (m_irq_flag & 0x04))
		{
			irq = 0x02;
			priority = 2;
		}

		// high priority IRQ
		else if ((REG_IE & 0x80) && ((REG_IP<<3) & m_irq_flag))
		{
			for(int i=3; i<=10; i++)
				if ((m_irq_flag & (REG_IP<<3)) & (1<<i))
				{
					irq = i;
					priority = 1;
					break;
				}
		}

		// low priority IRQ
		else if ((REG_IE & 0x80) && (m_irq_flag & 0x02))
		{
			irq = 0x01;
			priority = 0;
		}
		else if ((REG_IE & 0x80) && (m_irq_flag & 0x04))
		{
			irq = 0x02;
			priority = 0;
		}
		else if (REG_IE & 0x80)
		{
			for(int i=3; i<=10; i++)
				if (m_irq_flag & (1<<i))
				{
					irq = i;
					priority = 0;
					break;
				}
		}

		// IRQ with less priority of current interrupt are not executed until the end of the current interrupt routine
		if (irq != 0 && ((m_irq_lev & (1<<priority)) || (priority == 0 && (m_irq_lev & 0x06)) || (priority == 1 && (m_irq_lev & 0x04))))
		{
			if (LOG_IRQ)    logerror("%s: interrupt %d (Priority=%d, Level=%d) delayed\n", tag(), irq, priority, m_irq_lev);
			irq = 0;
		}

		if (irq != 0)
		{
			if (LOG_IRQ)    logerror("%s: interrupt %d (Priority=%d, Level=%d) executed\n", tag(), irq, priority, m_irq_lev);

			m_irq_lev |= (1<<priority);

			push((m_pc>>0) & 0xff);
			push((m_pc>>8) & 0xff);

			set_pc(s_irq_vectors[irq]);

			REG_PCON &= ~HALT_MODE;     // interrupts resume from HALT state

			// clear the IRQ flag
			m_irq_flag &= ~(1<<irq);

			standard_irq_callback(irq);
		}
	}
Exemplo n.º 17
0
void ucom4_cpu_device::execute_run()
{
	while (m_icount > 0)
	{
		m_icount--;

		// remember previous opcode
		m_prev_op = m_op;

		// handle interrupt - it not accepted during LI($9x) or EI($31), or while skipping
		if (m_int_f && m_inte_f && (m_prev_op & 0xf0) != 0x90 && m_prev_op != 0x31 && !m_skip)
		{
			m_icount--;
			push_stack();
			m_pc = 0xf << 2;
			m_int_f = 0;
			m_inte_f = (m_family == NEC_UCOM43) ? 0 : 1;

			standard_irq_callback(0);
		}

		// fetch next opcode
		debugger_instruction_hook(this, m_pc);
		m_op = m_program->read_byte(m_pc);
		m_bitmask = 1 << (m_op & 0x03);
		increment_pc();
		fetch_arg();

		if (m_skip)
		{
			m_skip = false;
			m_op = 0; // nop
		}

		// handle opcode
		switch (m_op & 0xf0)
		{
			case 0x80: op_ldz(); break;
			case 0x90: op_li(); break;
			case 0xa0: op_jmpcal(); break;
			case 0xb0: op_czp(); break;

			case 0xc0: case 0xd0: case 0xe0: case 0xf0: op_jcp(); break;

			default:
				switch (m_op)
				{
			case 0x00: op_nop(); break;
			case 0x01: op_di(); break;
			case 0x02: op_s(); break;
			case 0x03: op_tit(); break;
			case 0x04: op_tc(); break;
			case 0x05: op_ttm(); break;
			case 0x06: op_daa(); break;
			case 0x07: op_tal(); break;
			case 0x08: op_ad(); break;
			case 0x09: op_ads(); break;
			case 0x0a: op_das(); break;
			case 0x0b: op_clc(); break;
			case 0x0c: op_cm(); break;
			case 0x0d: op_inc(); break;
			case 0x0e: op_op(); break;
			case 0x0f: op_dec(); break;
			case 0x10: op_cma(); break;
			case 0x11: op_cia(); break;
			case 0x12: op_tla(); break;
			case 0x13: op_ded(); break;
			case 0x14: op_stm(); break;
			case 0x15: op_ldi(); break;
			case 0x16: op_cli(); break;
			case 0x17: op_ci(); break;
			case 0x18: op_exl(); break;
			case 0x19: op_adc(); break;
			case 0x1a: op_xc(); break;
			case 0x1b: op_stc(); break;
			case 0x1c: op_illegal(); break;
			case 0x1d: op_inm(); break;
			case 0x1e: op_ocd(); break;
			case 0x1f: op_dem(); break;

			case 0x30: op_rar(); break;
			case 0x31: op_ei(); break;
			case 0x32: op_ip(); break;
			case 0x33: op_ind(); break;

			case 0x40: op_ia(); break;
			case 0x41: op_jpa(); break;
			case 0x42: op_taz(); break;
			case 0x43: op_taw(); break;
			case 0x44: op_oe(); break;
			case 0x45: op_illegal(); break;
			case 0x46: op_tly(); break;
			case 0x47: op_thx(); break;
			case 0x48: op_rt(); break;
			case 0x49: op_rts(); break;
			case 0x4a: op_xaz(); break;
			case 0x4b: op_xaw(); break;
			case 0x4c: op_xls(); break;
			case 0x4d: op_xhr(); break;
			case 0x4e: op_xly(); break;
			case 0x4f: op_xhx(); break;

			default:
				switch (m_op & 0xfc)
				{
			case 0x20: op_fbf(); break;
			case 0x24: op_tab(); break;
			case 0x28: op_xm(); break;
			case 0x2c: op_xmd(); break;

			case 0x34: op_cmb(); break;
			case 0x38: op_lm(); break;
			case 0x3c: op_xmi(); break;

			case 0x50: op_tpb(); break;
			case 0x54: op_tpa(); break;
			case 0x58: op_tmb(); break;
			case 0x5c: op_fbt(); break;
			case 0x60: op_rpb(); break;
			case 0x64: op_reb(); break;
			case 0x68: op_rmb(); break;
			case 0x6c: op_rfb(); break;
			case 0x70: op_spb(); break;
			case 0x74: op_seb(); break;
			case 0x78: op_smb(); break;
			case 0x7c: op_sfb(); break;
				}
				break; // 0xfc

				}
				break; // 0xff

		} // big switch
	}
}