Exemplo n.º 1
0
int sunxi_is_version_A(void)
{
#ifdef CONFIG_ARCH_SUN4I
	if (sw_get_ic_ver() == MAGIC_VER_A)
		return 1;
#endif

	return 0;
}
Exemplo n.º 2
0
int OSAL_sw_get_ic_ver(void)
{
    enum sw_ic_ver ic_ver;
    int ret = 0xA;

    ic_ver = sw_get_ic_ver();
    if(ic_ver == MAGIC_VER_A)
    {
        ret = 0xA;
    }
    else if(ic_ver == MAGIC_VER_B)
    {
        ret = 0xB;
    }
    if(ic_ver == MAGIC_VER_C)
    {
        ret = 0xC;
    }

    return ret;
}
Exemplo n.º 3
0
static int aw_pm_valid(suspend_state_t state)
{
#ifdef CHECK_IC_VERSION
    enum sw_ic_ver version = MAGIC_VER_NULL;
#endif

    PM_DBG("valid\n");
    console_suspend_enabled = 0;

    if(!((state > PM_SUSPEND_ON) && (state < PM_SUSPEND_MAX))){
        PM_DBG("state (%d) invalid!\n", state);
        return 0;
    }

#ifdef CHECK_IC_VERSION
    if(1 == standby_mode){
        version = sw_get_ic_ver();
        if(!(MAGIC_VER_A13B == version || MAGIC_VER_A12B == version || MAGIC_VER_A10SB == version)){
            pr_info("ic version: %d not support super standby. \n", version);
            standby_mode = 0;
        }
    }
#endif

    //if 1 == standby_mode, actually, mean mem corresponding with super standby
    if(PM_SUSPEND_STANDBY == state){
        if(1 == standby_mode){
            standby_type = NORMAL_STANDBY;
        }else{
            standby_type = SUPER_STANDBY;
        }
        printk("standby_mode:%d, standby_type:%d, line:%d\n",standby_mode, standby_type, __LINE__);
    }else if(PM_SUSPEND_MEM == state || PM_SUSPEND_BOOTFAST == state){
        if(1 == standby_mode){
            standby_type = SUPER_STANDBY;
        }else{
            standby_type = NORMAL_STANDBY;
        }
        printk("standby_mode:%d, standby_type:%d, line:%d\n",standby_mode, standby_type, __LINE__);
    }
    
    //allocat space for backup dram data
    if(SUPER_STANDBY == standby_type){
        if((DRAM_BACKUP_SIZE) < ((int)&resume0_bin_end - (int)&resume0_bin_start) ){
            //judge the reserved space for resume0 is enough or not.
            pr_info("Notice: reserved space(%d) for resume is not enough(%d). \n", DRAM_BACKUP_SIZE,((int)&resume0_bin_end - (int)&resume0_bin_start));
            return 0;
        }
        
        memcpy((void *)DRAM_BACKUP_BASE_ADDR, (void *)&resume0_bin_start, (int)&resume0_bin_end - (int)&resume0_bin_start);
        dmac_flush_range((void *)DRAM_BACKUP_BASE_ADDR, (void *)(DRAM_BACKUP_BASE_ADDR + DRAM_BACKUP_SIZE -1) );
    }
        
#ifdef GET_CYCLE_CNT
        // init counters:
        init_perfcounters (1, 0);
#endif

    return 1;

}
Exemplo n.º 4
0
/*
*********************************************************************************************************
*                           clk_init
*
*Description: clock management initialise.
*
*Arguments  : none
*
*Return     : result
*               0,  initialise successed;
*              -1,  initialise failed;
*
*Notes      :
*
*********************************************************************************************************
*/
int clk_init(void)
{
    __s32           i, tmpFreq;
    struct clk      *tmpSclk;
    char            *script_base = (char *)(PAGE_OFFSET + 0x3000000);

    CCU_DBG("aw clock manager init!\n");

    //initialise clock controller unit
    if(AW_CCU_ERR_NONE != aw_ccu_init())
    {
        CCU_ERR("csp ccmu initial failed!\n");
        return -1;
    }

    //clear the data structure
    SysClkCnt = 0;
    memset((void *)&ccu_sys_clk, 0, sizeof(ccu_sys_clk));
    ModClkCnt = 0;
    memset((void *)&ccu_mod_clk, 0, sizeof(ccu_mod_clk));

    //get system clock information
    SysClkCnt = aw_ccu_get_sys_clk_cnt();
    if(SysClkCnt > MAX_SYSTEM_CLK_CNT)
    {
        CCU_ERR("system clock count define (%d) is invalid! actule is:%d\n", MAX_SYSTEM_CLK_CNT, SysClkCnt);
        return -1;
    }
    for(i=0; i<SysClkCnt; i++)
    {
        ccu_sys_clk[i].clk = aw_ccu_get_sys_clk((__aw_ccu_sys_clk_e)i);
        if(ccu_sys_clk[i].clk)
        {
            tmpSclk = &ccu_sys_clk[ccu_sys_clk[i].clk->parent];
            ccu_sys_clk[i].parent = tmpSclk;
            ccu_sys_clk[i].set_clk = &aw_ccu_set_sys_clk;
            ccu_sys_clk[i].get_clk = (__aw_ccu_clk_t * (*)(__s32))&aw_ccu_get_sys_clk;
            ccu_sys_clk[i].hash = ccu_clk_calc_hash(ccu_sys_clk[i].clk->name);
            if(ccu_sys_clk[i].clk->onoff == AW_CCU_CLK_ON)
            {
                tmpSclk->usr_cnt++;
            }
        }
    }

    //get module clock information
    ModClkCnt = aw_ccu_get_mod_clk_cnt();
    if(ModClkCnt > MAX_MODULE_CLK_CNT)
    {
        CCU_ERR("module clock count define (%d) is invalid! actule is:%d\n", MAX_MODULE_CLK_CNT, ModClkCnt);
        return -1;
    }
    for(i=0; i<ModClkCnt; i++)
    {
        ccu_mod_clk[i].clk = aw_ccu_get_mod_clk((__aw_ccu_sys_clk_e)i);
        if(ccu_mod_clk[i].clk)
        {
            tmpSclk = &ccu_sys_clk[ccu_mod_clk[i].clk->parent];
            ccu_mod_clk[i].parent = tmpSclk;
            ccu_mod_clk[i].set_clk = &aw_ccu_set_mod_clk;
            ccu_mod_clk[i].get_clk = (__aw_ccu_clk_t * (*)(__s32))&aw_ccu_get_mod_clk;
            ccu_mod_clk[i].hash = ccu_clk_calc_hash(ccu_mod_clk[i].clk->name);
            if(ccu_mod_clk[i].clk->onoff == AW_CCU_CLK_ON)
            {
                tmpSclk->usr_cnt++;
            }
            if(tmpSclk->child)
            {
                ccu_mod_clk[i].right = tmpSclk->child;
                tmpSclk->child->left = &ccu_mod_clk[i];
            }
            tmpSclk->child = &ccu_mod_clk[i];
        }
    }

    /* enable pll for use, it need be modified to dynamic */
    tmpSclk = &ccu_sys_clk[AW_SYS_CLK_PLL2];
    tmpSclk->clk->onoff = AW_CCU_CLK_ON;
    tmpSclk->set_clk(tmpSclk->clk);

    tmpSclk = &ccu_sys_clk[AW_SYS_CLK_PLL3];
    tmpSclk->clk->onoff = AW_CCU_CLK_ON;
    tmpSclk->set_clk(tmpSclk->clk);

    /* init pll4 frequency */
    if((MAGIC_VER_C == sw_get_ic_ver()) && USE_PLL6M_REPLACE_PLL4)
    {
        tmpSclk = &ccu_sys_clk[AW_SYS_CLK_PLL4];
        tmpSclk->clk->onoff = AW_CCU_CLK_OFF;
        tmpSclk->set_clk(tmpSclk->clk);
    }
    else
    {
        tmpFreq = sw_cfg_get_int(script_base, "target", "pll4_freq");
        if (tmpFreq == -1) {
            /* try to get pll4 frequency failed, set to default value */
            CCU_ERR("try to parse pll4 frequency from script faild!\n");
            tmpFreq = 960;
        } else {
            /* check if the value is valid */
            if ((tmpFreq < 120) || (tmpFreq > 1200)) {
                /* pll4 frequency is invalid, set to default value */
                CCU_ERR("pll4 frequency config is invalid!\n");
                tmpFreq = 960;
            }
            CCU_DBG("pll4 frequency is configed to %dMhz!\n", tmpFreq);
        }
        tmpSclk = &ccu_sys_clk[AW_SYS_CLK_PLL4];
        tmpSclk->clk->rate  = tmpFreq * 1000000;
        tmpSclk->set_clk(tmpSclk->clk);
        tmpSclk->clk->onoff = AW_CCU_CLK_ON;
        tmpSclk->set_clk(tmpSclk->clk);
    }

    /* init pll6 frequency */
    tmpFreq = sw_cfg_get_int(script_base, "target", "pll6_freq");
    if (tmpFreq == -1) {
        /* try to get pll6 frequency failed, set to default value */
        CCU_ERR("try to parse pll6 frequency from script faild!\n");
        tmpFreq = 600;
    } else {
        /* check if the value is valid */
        if ((tmpFreq < 120) || (tmpFreq > 2000)) {
            /* pll6 frequency is invalid, set to default value */
            CCU_ERR("pll6 frequency config is invalid!\n");
            tmpFreq = 600;
        }
        CCU_DBG("pll6 frequency is configed to %dMhz!\n", tmpFreq);
    }
    tmpSclk = &ccu_sys_clk[AW_SYS_CLK_PLL6];
    tmpSclk->clk->rate  = tmpFreq * 1000000;
    tmpSclk->set_clk(tmpSclk->clk);
    tmpSclk->clk->onoff = AW_CCU_CLK_ON;
    tmpSclk->set_clk(tmpSclk->clk);
    tmpSclk = &ccu_sys_clk[AW_SYS_CLK_PLL6M];
    if((tmpFreq/100)*100 == tmpFreq)
    {
        /* set cloce to 100Mhz */
        tmpSclk->clk->rate  = 100 * 1000000;
    }
    else
    {
        /* not divide the clock */
        tmpSclk->clk->rate  = (tmpFreq/6) * 1000000;
    }
    tmpSclk->set_clk(tmpSclk->clk);
    tmpSclk->clk->onoff = AW_CCU_CLK_ON;
    tmpSclk->set_clk(tmpSclk->clk);
    tmpSclk = &ccu_sys_clk[AW_SYS_CLK_PLL62];
    tmpSclk->clk->rate  = (tmpFreq/2) * 1000000;
    tmpSclk->set_clk(tmpSclk->clk);
    tmpSclk->clk->onoff = AW_CCU_CLK_ON;
    tmpSclk->set_clk(tmpSclk->clk);

    tmpSclk = &ccu_sys_clk[AW_SYS_CLK_PLL7];
    tmpSclk->clk->onoff = AW_CCU_CLK_ON;
    tmpSclk->set_clk(tmpSclk->clk);

    tmpFreq = sw_cfg_get_int(script_base, "target", "apb_freq");
    if (tmpFreq == -1) {
        /* try to get apb frequency failed, set to default value */
        CCU_ERR("try to parse apb frequency from script faild!\n");
        tmpFreq = 24;
    } else {
        /* check if the value is valid */
        if ((tmpFreq < 6) || (tmpFreq > 120)) {
            /* apb frequency is invalid, set to default value */
            CCU_ERR("apb frequency config is invalid!\n");
            tmpFreq = 24;
        }
        CCU_DBG("apb frequency is configed to %dMhz!\n", tmpFreq);
    }
    tmpSclk = clk_get(NULL, "apb1");
    if(tmpSclk) {
        struct clk      *tmpClk;
        if(tmpFreq == 24) {
            /* config apb clock source to OSC24M */
            tmpClk = clk_get(NULL, "hosc");
            if(tmpClk) {
                clk_set_parent(tmpSclk, tmpClk);
                clk_set_rate(tmpSclk, tmpFreq*1000000);
            } else {
                CCU_ERR("try to get hosc clock handle failed!\n");
            }
        } else {
            /* config apb clock source to PLL6 */
            tmpClk = clk_get(NULL, "sata_pll_2");
            if(tmpClk) {
                clk_set_rate(tmpSclk, 1000000);
                clk_set_parent(tmpSclk, tmpClk);
                clk_set_rate(tmpSclk, tmpFreq*1000000);
            } else {
                CCU_ERR("try to get hosc clock handle failed!\n");
            }
        }
    } else {
        CCU_ERR("try to get apb1 clock handle failed!\n");
    }

    return 0;
}
Exemplo n.º 5
0
/*
*********************************************************************************************************
*                           mem_clk_exit
*
*Description: ccu exit for platform mem
*
*Arguments  : none
*
*Return     : result,
*
*Notes      :
*
*********************************************************************************************************
*/
__s32 mem_clk_restore(struct clk_state *pclk_state)
{
	/* initialise the CCU io base */
	__ccmu_reg_list_t   *CmuReg = pclk_state->CmuReg;
	
	/*restore clk src and ldo*/
	*(volatile __u32 *)&CmuReg->HoscCtl    = pclk_state->ccu_reg_back[0];  
#ifdef CHECK_RESTORE_STATUS
	printk("*(volatile __u32 *)&CmuReg->HoscCtl = 0x%x, pclk_state->ccu_reg_back[0] = 0x%x. \n", \
		*(volatile __u32 *)&CmuReg->HoscCtl, pclk_state->ccu_reg_back[0]);
#endif

	*(volatile __u32 *)&CmuReg->SysClkDiv  = pclk_state->ccu_reg_back[1];  
#ifdef CHECK_RESTORE_STATUS
	printk("*(volatile __u32 *)&CmuReg->SysClkDiv = 0x%x, pclk_state->ccu_reg_back[1] = 0x%x. \n", \
		*(volatile __u32 *)&CmuReg->SysClkDiv, pclk_state->ccu_reg_back[1]);
#endif

	*(volatile __u32 *)&CmuReg->Apb1ClkDiv = pclk_state->ccu_reg_back[2];
#ifdef CHECK_RESTORE_STATUS
	printk("*(volatile __u32 *)&CmuReg->Apb1ClkDiv = 0x%x, pclk_state->ccu_reg_back[2] = 0x%x. \n", \
		*(volatile __u32 *)&CmuReg->Apb1ClkDiv, pclk_state->ccu_reg_back[2]);
#endif

	/*restore axi, ahb, apb gating*/	
	*(volatile __u32 *)&CmuReg->AxiGate    = pclk_state->ccu_reg_back[10];  
#ifdef CHECK_RESTORE_STATUS
	printk("*(volatile __u32 *)&CmuReg->AxiGate = 0x%x, pclk_state->ccu_reg_back[10] = 0x%x. \n", \
		*(volatile __u32 *)&CmuReg->AxiGate, pclk_state->ccu_reg_back[10]);
#endif

	*(volatile __u32 *)&CmuReg->AhbGate0   = pclk_state->ccu_reg_back[11]; 
#ifdef CHECK_RESTORE_STATUS
	printk("*(volatile __u32 *)&CmuReg->AhbGate0 = 0x%x, pclk_state->ccu_reg_back[11] = 0x%x. \n", \
		*(volatile __u32 *)&CmuReg->AhbGate0, pclk_state->ccu_reg_back[11]);
#endif

	*(volatile __u32 *)&CmuReg->AhbGate1   = pclk_state->ccu_reg_back[12]; 
#ifdef CHECK_RESTORE_STATUS
	printk("*(volatile __u32 *)&CmuReg->AhbGate1 = 0x%x, pclk_state->ccu_reg_back[12] = 0x%x. \n", \
		*(volatile __u32 *)&CmuReg->AhbGate1, pclk_state->ccu_reg_back[12]);
#endif

	*(volatile __u32 *)&CmuReg->Apb0Gate   = pclk_state->ccu_reg_back[13]; 
#ifdef CHECK_RESTORE_STATUS
	printk("*(volatile __u32 *)&CmuReg->Apb0Gate = 0x%x, pclk_state->ccu_reg_back[13] = 0x%x. \n", \
		*(volatile __u32 *)&CmuReg->Apb0Gate, pclk_state->ccu_reg_back[13]);
#endif

	*(volatile __u32 *)&CmuReg->Apb1Gate   = pclk_state->ccu_reg_back[14]; 
#ifdef CHECK_RESTORE_STATUS
	printk("*(volatile __u32 *)&CmuReg->Apb1Gate = 0x%x, pclk_state->ccu_reg_back[14] = 0x%x. \n", \
		*(volatile __u32 *)&CmuReg->Apb1Gate, pclk_state->ccu_reg_back[14]);
#endif

	/* restore pll registers and tuning? latency?*/
	//notice: do not touch pll1 and pll5
	//*(volatile __u32 *)&CmuReg->Pll1Ctl    = pclk_state->ccu_reg_back[3]; 
#ifdef CHECK_RESTORE_STATUS
	printk("*(volatile __u32 *)&CmuReg->Pll1Ctl = 0x%x, pclk_state->ccu_reg_back[3] = 0x%x. \n", \
		*(volatile __u32 *)&CmuReg->Pll1Ctl, pclk_state->ccu_reg_back[3]);
#endif

	*(volatile __u32 *)&CmuReg->Pll2Ctl    = pclk_state->ccu_reg_back[4];
#ifdef CHECK_RESTORE_STATUS
	printk("*(volatile __u32 *)&CmuReg->Pll2Ctl = 0x%x, pclk_state->ccu_reg_back[4] = 0x%x. \n", \
		*(volatile __u32 *)&CmuReg->Pll2Ctl, pclk_state->ccu_reg_back[4]);
#endif

	*(volatile __u32 *)&CmuReg->Pll3Ctl    = pclk_state->ccu_reg_back[5]; 
#ifdef CHECK_RESTORE_STATUS
	printk("*(volatile __u32 *)&CmuReg->Pll3Ctl = 0x%x, pclk_state->ccu_reg_back[5] = 0x%x. \n", \
		*(volatile __u32 *)&CmuReg->Pll3Ctl, pclk_state->ccu_reg_back[5]);
#endif

	*(volatile __u32 *)&CmuReg->Pll4Ctl    = pclk_state->ccu_reg_back[6]; 
#ifdef CHECK_RESTORE_STATUS
	printk("*(volatile __u32 *)&CmuReg->Pll4Ctl = 0x%x, pclk_state->ccu_reg_back[6] = 0x%x. \n", \
		*(volatile __u32 *)&CmuReg->Pll4Ctl, pclk_state->ccu_reg_back[6]);
#endif

	//*(volatile __u32 *)&CmuReg->Pll5Ctl    = pclk_state->ccu_reg_back[7]; 
#ifdef CHECK_RESTORE_STATUS
	printk("*(volatile __u32 *)&CmuReg->Pll5Ctl = 0x%x, pclk_state->ccu_reg_back[7] = 0x%x. \n", \
		*(volatile __u32 *)&CmuReg->Pll5Ctl, pclk_state->ccu_reg_back[7]);
#endif

	*(volatile __u32 *)&CmuReg->Pll6Ctl    = pclk_state->ccu_reg_back[8]; 
#ifdef CHECK_RESTORE_STATUS
	printk("*(volatile __u32 *)&CmuReg->Pll6Ctl = 0x%x, pclk_state->ccu_reg_back[8] = 0x%x. \n", \
		*(volatile __u32 *)&CmuReg->Pll6Ctl, pclk_state->ccu_reg_back[8]);
#endif

	*(volatile __u32 *)&CmuReg->Pll7Ctl    = pclk_state->ccu_reg_back[9]; 
#ifdef CHECK_RESTORE_STATUS
	printk("*(volatile __u32 *)&CmuReg->Pll7Ctl = 0x%x, pclk_state->ccu_reg_back[9] = 0x%x. \n", \
		*(volatile __u32 *)&CmuReg->Pll7Ctl, pclk_state->ccu_reg_back[9]);
#endif

	//is this neccessary?
	 mdelay(2);
	 
	/* config the CCU to default status */
	//needed?
#if 0
	if(MAGIC_VER_C == sw_get_ic_ver()) {
		/* switch PLL4 to PLL6 */
		#if(USE_PLL6M_REPLACE_PLL4)
		CmuReg->VeClk.PllSwitch = 1;
		#else
		CmuReg->VeClk.PllSwitch = 0;
		#endif
	}
#endif
	
	return 0;
}