void __init ux500_init_irq(void)
{
void __iomem *dist_base;
void __iomem *cpu_base;
gic_arch_extn.irq_set_wake = ux500_gic_irq_set_wake;
if (cpu_is_u5500()) {
dist_base = __io_address(U5500_GIC_DIST_BASE);
cpu_base = __io_address(U5500_GIC_CPU_BASE);
} else if (cpu_is_u8500() || cpu_is_u9540()) {
dist_base = __io_address(U8500_GIC_DIST_BASE);
cpu_base = __io_address(U8500_GIC_CPU_BASE);
} else
ux500_unknown_soc();
gic_init(0, 29, dist_base, cpu_base);
/*
* On WD reboot gic is in some cases decoupled.
* This will make sure that the GIC is correctly configured.
*/
ux500_pm_gic_recouple();
/*
* Init clocks here so that they are available for system timer
* initialization.
*/
prcmu_early_init();
/* backwards compatible */
if (!arm_pm_restart)
arm_pm_restart = ux500_restart;
clk_init();
}
static void __init wakeup_secondary(void)
{
void __iomem *backupram;
if (cpu_is_u8500_family() || cpu_is_ux540_family())
backupram = __io_address(U8500_BACKUPRAM0_BASE);
else
ux500_unknown_soc();
/*
* write the address of secondary startup into the backup ram register
* at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
* backup ram register at offset 0x1FF0, which is what boot rom code
* is waiting for. This would wake up the secondary core from WFE
*/
#define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
__raw_writel(virt_to_phys(u8500_secondary_startup),
backupram + UX500_CPU1_JUMPADDR_OFFSET);
#define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
__raw_writel(0xA1FEED01,
backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
/* make sure write buffer is drained */
mb();
}
void __init ux500_init_irq(void)
{
void __iomem *dist_base;
void __iomem *cpu_base;
if (cpu_is_u5500()) {
dist_base = __io_address(U5500_GIC_DIST_BASE);
cpu_base = __io_address(U5500_GIC_CPU_BASE);
} else if (cpu_is_u8500()) {
dist_base = __io_address(U8500_GIC_DIST_BASE);
cpu_base = __io_address(U8500_GIC_CPU_BASE);
} else
ux500_unknown_soc();
#ifdef CONFIG_OF
if (of_have_populated_dt())
of_irq_init(ux500_dt_irq_match);
else
#endif
gic_init(0, 29, dist_base, cpu_base);
if (cpu_is_u5500())
db5500_prcmu_early_init();
if (cpu_is_u8500())
db8500_prcmu_early_init();
clk_init();
}
static int __init ux500_l2x0_init(void)
{
uint32_t aux_val = 0x3e000000;
if (cpu_is_u5500())
l2x0_base = __io_address(U5500_L2CC_BASE);
else if (cpu_is_u8500() || cpu_is_u9540())
l2x0_base = __io_address(U8500_L2CC_BASE);
else
ux500_unknown_soc();
/* u9540's L2 has 128KB way size */
if (cpu_is_u9540())
aux_val |=
(0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); /* 128KB way size */
else
aux_val |=
(0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); /* 64KB way size */
/* 8 way associativity, force WA */
l2x0_init(l2x0_base, aux_val, 0xc0000fff);
/* Override invalidate function */
outer_cache.disable = ux500_l2x0_disable;
outer_cache.inv_all = ux500_l2x0_inv_all;
return 0;
}
static void __init ux500_timer_init(void)
{
void __iomem *prcmu_timer_base;
if (cpu_is_u5500()) {
mtu_base = __io_address(U5500_MTU0_BASE);
prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
} else if (cpu_is_u8500()) {
mtu_base = __io_address(U8500_MTU0_BASE);
prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
} else {
ux500_unknown_soc();
}
/*
* Here we register the timerblocks active in the system.
* Localtimers (twd) is started when both cpu is up and running.
* MTU register a clocksource, clockevent and sched_clock.
* Since the MTU is located in the VAPE power domain
* it will be cleared in sleep which makes it unsuitable.
* We however need it as a timer tick (clockevent)
* during boot to calibrate delay until twd is started.
* RTC-RTT have problems as timer tick during boot since it is
* depending on delay which is not yet calibrated. RTC-RTT is in the
* always-on powerdomain and is used as clockevent instead of twd when
* sleeping.
* The PRCMU timer 4(3 for DB5500) register a clocksource and
* sched_clock with higher rating then MTU since is always-on.
*
*/
nmdk_timer_init();
clksrc_dbx500_prcmu_init(prcmu_timer_base);
ux500_twd_init();
}
void __init ux500_timer_init(void)
{
void __iomem *prcmu_timer_base;
void __iomem *tmp_base;
struct device_node *np;
if (cpu_is_u8500_family() || cpu_is_ux540_family())
prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
else
ux500_unknown_soc();
np = of_find_matching_node(NULL, prcmu_timer_of_match);
if (!np)
goto dt_fail;
tmp_base = of_iomap(np, 0);
if (!tmp_base)
goto dt_fail;
prcmu_timer_base = tmp_base;
dt_fail:
clksrc_dbx500_prcmu_init(prcmu_timer_base);
clocksource_of_init();
}
void __init ux500_init_irq(void)
{
void __iomem *dist_base;
void __iomem *cpu_base;
if (cpu_is_u5500()) {
dist_base = __io_address(U5500_GIC_DIST_BASE);
cpu_base = __io_address(U5500_GIC_CPU_BASE);
} else if (cpu_is_u8500()) {
dist_base = __io_address(U8500_GIC_DIST_BASE);
cpu_base = __io_address(U8500_GIC_CPU_BASE);
} else
ux500_unknown_soc();
gic_init(0, 29, dist_base, cpu_base);
/*
* Init clocks here so that they are available for system timer
* initialization.
*/
if (cpu_is_u5500())
db5500_prcmu_early_init();
if (cpu_is_u8500())
prcmu_early_init();
clk_init();
}
static void __iomem *scu_base_addr(void)
{
if (cpu_is_u8500_family() || cpu_is_ux540_family())
return __io_address(U8500_SCU_BASE);
else
ux500_unknown_soc();
return NULL;
}
void __init ux500_timer_init(void)
{
void __iomem *mtu_timer_base;
void __iomem *prcmu_timer_base;
void __iomem *tmp_base;
struct device_node *np;
if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
mtu_timer_base = __io_address(U8500_MTU0_BASE);
prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
} else {
ux500_unknown_soc();
}
/* TODO: Once MTU has been DT:ed place code above into else. */
if (of_have_populated_dt()) {
#ifdef CONFIG_OF
np = of_find_matching_node(NULL, prcmu_timer_of_match);
if (!np)
#endif
goto dt_fail;
tmp_base = of_iomap(np, 0);
if (!tmp_base)
goto dt_fail;
prcmu_timer_base = tmp_base;
}
dt_fail:
/* Doing it the old fashioned way. */
/*
* Here we register the timerblocks active in the system.
* Localtimers (twd) is started when both cpu is up and running.
* MTU register a clocksource, clockevent and sched_clock.
* Since the MTU is located in the VAPE power domain
* it will be cleared in sleep which makes it unsuitable.
* We however need it as a timer tick (clockevent)
* during boot to calibrate delay until twd is started.
* RTC-RTT have problems as timer tick during boot since it is
* depending on delay which is not yet calibrated. RTC-RTT is in the
* always-on powerdomain and is used as clockevent instead of twd when
* sleeping.
* The PRCMU timer 4 register a clocksource and
* sched_clock with higher rating then MTU since is always-on.
*
*/
if (!of_have_populated_dt())
nmdk_timer_init(mtu_timer_base, IRQ_MTU0);
clksrc_dbx500_prcmu_init(prcmu_timer_base);
ux500_twd_init();
}
void __init mtu_timer_init(void)
{
unsigned long rate;
struct clk *clk0;
clk0 = clk_get_sys("mtu0", NULL);
BUG_ON(IS_ERR(clk0));
rate = clk_get_rate(clk0);
clk_enable(clk0);
/*
* Set scale and timer for sched_clock
*/
setup_sched_clock(rate);
u8500_cycle = (rate + HZ/2) / HZ;
/* Save global pointer to mtu, used by functions above */
if (cpu_is_u5500()) {
mtu0_base = ioremap(U5500_MTU0_BASE, SZ_4K);
} else if (cpu_is_u8500()) {
mtu0_base = ioremap(U8500_MTU0_BASE, SZ_4K);
} else {
ux500_unknown_soc();
}
/* Restart clock source */
mtu_clocksource_reset();
/* Now the scheduling clock is ready */
u8500_clksrc.read = u8500_read_timer;
u8500_clksrc.mult = clocksource_hz2mult(rate, u8500_clksrc.shift);
clocksource_register(&u8500_clksrc);
/* Register irq and clockevents */
/* We can sleep for max 10s (actually max is longer) */
clockevents_calc_mult_shift(&u8500_mtu_clkevt, rate, 10);
u8500_mtu_clkevt.max_delta_ns = clockevent_delta2ns(0xffffffff,
&u8500_mtu_clkevt);
u8500_mtu_clkevt.min_delta_ns = clockevent_delta2ns(0xff,
&u8500_mtu_clkevt);
setup_irq(IRQ_MTU0, &u8500_timer_irq);
clockevents_register_device(&u8500_mtu_clkevt);
#ifdef ARCH_HAS_READ_CURRENT_TIMER
set_delay_fn(mtu_timer_delay_loop);
#endif
}
static int __init prefetch_ctrl_init(void)
{
int err;
int origin_err;
/* Selects trustzone application needed for the job. */
struct tee_uuid static_uuid = {
L2X0_UUID_TEE_TA_START_LOW,
L2X0_UUID_TEE_TA_START_MID,
L2X0_UUID_TEE_TA_START_HIGH,
L2X0_UUID_TEE_TA_START_CLOCKSEQ,
};
/* Get PL310 base address. It will be used as readonly. */
if (cpu_is_u5500())
l2x0_base = __io_address(U5500_L2CC_BASE);
else if (cpu_is_u8500() || cpu_is_u9540())
l2x0_base = __io_address(U8500_L2CC_BASE);
else
ux500_unknown_soc();
err = teec_initialize_context(NULL, &context);
if (err) {
pr_err("l2x0-prefetch: unable to initialize tee context,"
" err = %d\n", err);
err = -EINVAL;
goto error0;
}
err = teec_open_session(&context, &session, &static_uuid,
TEEC_LOGIN_PUBLIC, NULL, NULL, &origin_err);
if (err) {
pr_err("l2x0-prefetch: unable to open tee session,"
" tee error = %d, origin error = %d\n",
err, origin_err);
err = -EINVAL;
goto error1;
}
outer_cache.prefetch_enable = prefetch_enable;
outer_cache.prefetch_disable = prefetch_disable;
pr_info("l2x0-prefetch: initialized.\n");
return 0;
error1:
(void)teec_finalize_context(&context);
error0:
return err;
}
static int ux500_l2x0_init(void)
{
if (cpu_is_u5500())
l2x0_base = __io_address(U5500_L2CC_BASE);
else if (cpu_is_u8500())
l2x0_base = __io_address(U8500_L2CC_BASE);
else
ux500_unknown_soc();
/* 64KB way size, 8 way associativity, force WA */
l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
/* Override invalidate function */
outer_cache.disable = ux500_l2x0_disable;
outer_cache.inv_all = ux500_l2x0_inv_all;
return 0;
}
/*
* FIXME: Should we set up the GPIO domain here?
*
* The problem is that we cannot put the interrupt resources into the platform
* device until the irqdomain has been added. Right now, we set the GIC interrupt
* domain from init_irq(), then load the gpio driver from
* core_initcall(nmk_gpio_init) and add the platform devices from
* arch_initcall(customize_machine).
*
* This feels fragile because it depends on the gpio device getting probed
* _before_ any device uses the gpio interrupts.
*/
void __init ux500_init_irq(void)
{
void __iomem *dist_base;
void __iomem *cpu_base;
gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
dist_base = __io_address(U8500_GIC_DIST_BASE);
cpu_base = __io_address(U8500_GIC_CPU_BASE);
} else
ux500_unknown_soc();
#ifdef CONFIG_OF
if (of_have_populated_dt())
irqchip_init();
else
#endif
gic_init(0, 29, dist_base, cpu_base);
/*
* Init clocks here so that they are available for system timer
* initialization.
*/
if (cpu_is_u8500_family()) {
prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
U8500_CLKRST6_BASE);
} else if (cpu_is_u9540()) {
prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
U8500_CLKRST6_BASE);
} else if (cpu_is_u8540()) {
prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
u8540_clk_init();
}
}
static int __init ux500_l2x0_init(void)
{
u32 aux_val = 0x3e000000;
if (cpu_is_u8500_family() || cpu_is_ux540_family())
l2x0_base = __io_address(U8500_L2CC_BASE);
else
ux500_unknown_soc();
/* Unlock before init */
ux500_l2x0_unlock();
/* DBx540's L2 has 128KB way size */
if (cpu_is_ux540_family())
/* 128KB way size */
aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
else
/* 64KB way size */
aux_val |= (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
/* 64KB way size, 8 way associativity, force WA */
if (of_have_populated_dt())
l2x0_of_init(aux_val, 0xc0000fff);
else
l2x0_init(l2x0_base, aux_val, 0xc0000fff);
/*
* We can't disable l2 as we are in non secure mode, currently
* this seems be called only during kexec path. So let's
* override outer.disable with nasty assignment until we have
* some SMI service available.
*/
outer_cache.disable = NULL;
return 0;
}
void __init ux500_init_irq(void)
{
void __iomem *dist_base;
if (cpu_is_u5500()) {
gic_cpu_base_addr = __io_address(U5500_GIC_CPU_BASE);
dist_base = __io_address(U5500_GIC_DIST_BASE);
} else if (cpu_is_u8500()) {
gic_cpu_base_addr = __io_address(U8500_GIC_CPU_BASE);
dist_base = __io_address(U8500_GIC_DIST_BASE);
} else
ux500_unknown_soc();
gic_dist_init(0, dist_base, 29);
gic_cpu_init(0, gic_cpu_base_addr);
/*
* Init clocks here so that they are available for system timer
* initialization.
*/
prcmu_early_init();
arm_pm_restart = ux500_restart;
clk_init();
}
