Exemplo n.º 1
0
static arm_timer_state *arm_timer_init(uint32_t freq)
{
    arm_timer_state *s;
    QEMUBH *bh;

    s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
    s->freq = freq;
    s->control = TIMER_CTRL_IE;

    bh = qemu_bh_new(arm_timer_tick, s);
    s->timer = ptimer_init(bh);
    vmstate_register(NULL, -1, &vmstate_arm_timer, s);
    return s;
}
Exemplo n.º 2
0
static int at91_spi_init(SysBusDevice *dev)
{
    SPIState *s = FROM_SYSBUS(typeof(*s), dev);
    int spi_regs;

    s->pdc_state = at91_pdc_init(s, pdc_start_transfer, pdc_state_changed);
    sysbus_init_irq(dev, &s->irq);
    spi_regs = cpu_register_io_memory(at91_spi_readfn, at91_spi_writefn, s, DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, SPI_SIZE, spi_regs);
    qemu_register_reset(at91_spi_reset, s);

    vmstate_register(&dev->qdev, -1, &vmstate_at91sam9_spi, s);
	return 0;
}
Exemplo n.º 3
0
static int bcm2835_power_init(SysBusDevice *dev)
{
    bcm2835_power_state *s = FROM_SYSBUS(bcm2835_power_state, dev);
    
    s->pending = 0;
    
    sysbus_init_irq(dev, &s->mbox_irq);
    memory_region_init_io(&s->iomem, &bcm2835_power_ops, s, 
        "bcm2835_power", 0x10);
    sysbus_init_mmio(dev, &s->iomem);
    vmstate_register(&dev->qdev, -1, &vmstate_bcm2835_power, s);

    return 0;
}
Exemplo n.º 4
0
/* Returns an array 5 ouput slots.  */
void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode)
{
    gamepad_state *s;
    int i;

    s = (gamepad_state *)g_malloc0(sizeof (gamepad_state));
    s->buttons = (gamepad_button *)g_malloc0(n * sizeof (gamepad_button));
    for (i = 0; i < n; i++) {
        s->buttons[i].irq = irq[i];
        s->buttons[i].keycode = keycode[i];
    }
    s->num_buttons = n;
    qemu_add_kbd_event_handler(stellaris_gamepad_put_key, s);
    vmstate_register(NULL, -1, &vmstate_stellaris_gamepad, s);
}
Exemplo n.º 5
0
static int ox820_sysctrl_scratchword_init(SysBusDevice *dev)
{
    ox820_sysctrl_scratchword_state *s = FROM_SYSBUS(ox820_sysctrl_scratchword_state, dev);

    memory_region_init_io(&s->iomem, &ox820_sysctrl_scratchword_ops, s, "ox820-sysctrl-scratchword", 0x10);
    sysbus_init_mmio(dev, &s->iomem);

    s->scratchword[0] = 0;
    s->scratchword[1] = 0;
    s->scratchword[2] = 0;
    s->scratchword[3] = 0;

    vmstate_register(&dev->qdev, -1, &vmstate_ox820_sysctrl_scratchword, s);
    return 0;
}
Exemplo n.º 6
0
static int pl022_init(SysBusDevice *dev)
{
    pl022_state *s = FROM_SYSBUS(pl022_state, dev);
    int iomemtype;

    iomemtype = cpu_register_io_memory(pl022_readfn,
                                       pl022_writefn, s,
                                       DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    sysbus_init_irq(dev, &s->irq);
    s->ssi = ssi_create_bus(&dev->qdev, "ssi");
    pl022_reset(s);
    vmstate_register(&dev->qdev, -1, &vmstate_pl022, s);
    return 0;
}
Exemplo n.º 7
0
PITState *kvm_pit_init(int base, qemu_irq irq)
{
    PITState *pit = &pit_state;
    PITChannelState *s;

    s = &pit->channels[0];
    s->irq_timer = qemu_new_timer(vm_clock, dummy_timer, s);
    vmstate_pit.pre_save = kvm_pit_pre_save;
    vmstate_pit.post_load = kvm_pit_post_load;
    vmstate_register(base, &vmstate_pit, pit);
    qemu_register_reset(pit_reset, pit);
    pit_reset(pit);

    return pit;
}
Exemplo n.º 8
0
/* via ide func */
static void vt82c686b_ide_realize(PCIDevice *dev, Error **errp)
{
    PCIIDEState *d = PCI_IDE(dev);
    uint8_t *pci_conf = dev->config;

    pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
    pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);

    qemu_register_reset(via_reset, d);
    bmdma_setup_bar(d);
    pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);

    vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);

    vt82c686b_init_ports(d);
}
Exemplo n.º 9
0
static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
{
    PCIIDEState *d = PCI_IDE(dev);
    uint8_t *pci_conf = dev->config;

    pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode

    qemu_register_reset(piix3_reset, d);

    bmdma_setup_bar(d);
    pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);

    vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);

    pci_piix_init_ports(d);
}
Exemplo n.º 10
0
static int sp804_init(SysBusDevice *dev)
{
    sp804_state *s = FROM_SYSBUS(sp804_state, dev);
    qemu_irq *qi;

    qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
    sysbus_init_irq(dev, &s->irq);
    s->timer[0] = arm_timer_init(s->freq0);
    s->timer[1] = arm_timer_init(s->freq1);
    s->timer[0]->irq = qi[0];
    s->timer[1]->irq = qi[1];
    memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
    sysbus_init_mmio(dev, &s->iomem);
    vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
    return 0;
}
Exemplo n.º 11
0
PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
        qemu_irq irq)
{
    int iomemtype;
    PXA2xxKeyPadState *s;

    s = (PXA2xxKeyPadState *) qemu_mallocz(sizeof(PXA2xxKeyPadState));
    s->irq = irq;

    iomemtype = cpu_register_io_memory(pxa2xx_keypad_readfn,
                    pxa2xx_keypad_writefn, s, DEVICE_NATIVE_ENDIAN);
    cpu_register_physical_memory(base, 0x00100000, iomemtype);

    vmstate_register(NULL, 0, &vmstate_pxa2xx_keypad, s);

    return s;
}
Exemplo n.º 12
0
static int pci_piix_ide_initfn(PCIIDEState *d)
{
    uint8_t *pci_conf = d->dev.config;

    pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
    pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);

    qemu_register_reset(piix3_reset, d);

    pci_register_bar(&d->dev, 4, 0x10, PCI_BASE_ADDRESS_SPACE_IO, bmdma_map);

    vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);

    pci_piix_init_ports(d);

    return 0;
}
Exemplo n.º 13
0
PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem,
                                      target_phys_addr_t base,
                                      qemu_irq irq)
{
    PXA2xxKeyPadState *s;

    s = (PXA2xxKeyPadState *) g_malloc0(sizeof(PXA2xxKeyPadState));
    s->irq = irq;

    memory_region_init_io(&s->iomem, &pxa2xx_keypad_ops, s,
                          "pxa2xx-keypad", 0x00100000);
    memory_region_add_subregion(sysmem, base, &s->iomem);

    vmstate_register(NULL, 0, &vmstate_pxa2xx_keypad, s);

    return s;
}
Exemplo n.º 14
0
void virt_acpi_setup(VirtGuestInfo *guest_info)
{
    AcpiBuildTables tables;
    AcpiBuildState *build_state;

    if (!guest_info->fw_cfg) {
        trace_virt_acpi_setup();
        return;
    }

    if (!acpi_enabled) {
        trace_virt_acpi_setup();
        return;
    }

    build_state = g_malloc0(sizeof *build_state);
    build_state->guest_info = guest_info;

    acpi_build_tables_init(&tables);
    virt_acpi_build(build_state->guest_info, &tables);

    /* Now expose it all to Guest */
    build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
                                               ACPI_BUILD_TABLE_FILE,
                                               ACPI_BUILD_TABLE_MAX_SIZE);
    assert(build_state->table_mr != NULL);

    build_state->linker_mr =
        acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
                          "etc/table-loader", 0);

    fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
                    tables.tcpalog->data, acpi_data_len(tables.tcpalog));

    build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
                                              ACPI_BUILD_RSDP_FILE, 0);

    qemu_register_reset(virt_acpi_build_reset, build_state);
    virt_acpi_build_reset(build_state);
    vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);

    /* Cleanup tables but don't free the memory: we track it
     * in build_state.
     */
    acpi_build_tables_cleanup(&tables, false);
}
Exemplo n.º 15
0
static int sp804_init(SysBusDevice *sbd)
{
    DeviceState *dev = DEVICE(sbd);
    SP804State *s = SP804(dev);
    qemu_irq *qi;

    qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
    sysbus_init_irq(sbd, &s->irq);
    s->timer[0] = arm_timer_init(s->freq0);
    s->timer[1] = arm_timer_init(s->freq1);
    s->timer[0]->irq = qi[0];
    s->timer[1]->irq = qi[1];
    memory_region_init_io(&s->iomem, OBJECT(s), &sp804_ops, s,
                          "sp804", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    vmstate_register(dev, -1, &vmstate_sp804, s);
    return 0;
}
Exemplo n.º 16
0
static int sp804_init(SysBusDevice *dev)
{
    sp804_state *s = FROM_SYSBUS(sp804_state, dev);
    qemu_irq *qi;

    qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
    sysbus_init_irq(dev, &s->irq);
    /* ??? The timers are actually configurable between 32kHz and 1MHz, but
       we don't implement that.  */
    s->timer[0] = arm_timer_init(1000000);
    s->timer[1] = arm_timer_init(1000000);
    s->timer[0]->irq = qi[0];
    s->timer[1]->irq = qi[1];
    memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
    sysbus_init_mmio_region(dev, &s->iomem);
    vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
    return 0;
}
Exemplo n.º 17
0
static int stm32l_sys_init(uint32_t base, qemu_irq irq,
                           stm32_board_info * board)
{
    int iomemtype;
    ssys_state *s;

    s = (ssys_state *)g_malloc0(sizeof(ssys_state));
    s->irq = irq;
    s->board = board;

    iomemtype = cpu_register_io_memory(ssys_readfn,
                                       ssys_writefn, s,
                                       DEVICE_NATIVE_ENDIAN);
    cpu_register_physical_memory(base, 0x00001000, iomemtype);
    ssys_reset(s);
    vmstate_register(NULL, -1, &vmstate_stm32_sys, s);
    return 0;
}
Exemplo n.º 18
0
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
                   MemoryRegion *region, ram_addr_t size,
                   hwaddr mask)
{
    KBDState *s = g_malloc0(sizeof(KBDState));

    s->irq_kbd = kbd_irq;
    s->irq_mouse = mouse_irq;
    s->mask = mask;

    vmstate_register(NULL, 0, &vmstate_kbd, s);

    memory_region_init_io(region, NULL, &i8042_mmio_ops, s, "i8042", size);

    s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
    s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
    qemu_register_reset(kbd_reset, s);
}
Exemplo n.º 19
0
void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
                    qemu_irq irq, int shift,
                    DriveInfo *hd0, DriveInfo *hd1)
{
    MMIOState *s = qemu_mallocz(sizeof(MMIOState));
    int mem1, mem2;

    ide_init2_with_non_qdev_drives(&s->bus, hd0, hd1, irq);

    s->shift = shift;

    mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s);
    mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s);
    cpu_register_physical_memory(membase, 16 << shift, mem1);
    cpu_register_physical_memory(membase2, 2 << shift, mem2);
    vmstate_register(NULL, 0, &vmstate_ide_mmio, s);
    qemu_register_reset(mmio_ide_reset, s);
}
Exemplo n.º 20
0
Arquivo: piix.c Projeto: 0bliv10n/s2e
static int pci_piix_ide_initfn(PCIDevice *dev)
{
    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
    uint8_t *pci_conf = d->dev.config;

    pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode

    qemu_register_reset(piix3_reset, d);

    bmdma_setup_bar(d);
    pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);

    vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);

    pci_piix_init_ports(d);

    return 0;
}
Exemplo n.º 21
0
/* via ide func */
static int vt82c686b_ide_initfn(PCIDevice *dev)
{
    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
    uint8_t *pci_conf = d->dev.config;

    pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
    pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);

    qemu_register_reset(via_reset, d);
    bmdma_setup_bar(d);
    pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);

    vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d);

    vt82c686b_init_ports(d);

    return 0;
}
Exemplo n.º 22
0
void *vmmouse_init(void *m)
{
    VMMouseState *s = NULL;

    DPRINTF("vmmouse_init\n");

    s = qemu_mallocz(sizeof(VMMouseState));

    s->status = 0xffff;
    s->ps2_mouse = m;
    s->queue_size = VMMOUSE_QUEUE_SIZE;

    vmport_register(VMMOUSE_STATUS, vmmouse_ioport_read, s);
    vmport_register(VMMOUSE_COMMAND, vmmouse_ioport_read, s);
    vmport_register(VMMOUSE_DATA, vmmouse_ioport_read, s);
    vmstate_register(0, &vmstate_vmmouse, s);

    return s;
}
Exemplo n.º 23
0
static int sp804_init(SysBusDevice *dev)
{
    sp804_state *s = FROM_SYSBUS(sp804_state, dev);
    qemu_irq *qi;

    qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
    sysbus_init_irq(dev, &s->irq);
    /* The timers are configurable between 32kHz and 1MHz
     * defaulting to 1MHz but overrideable as individual properties */
    s->timer[0] = arm_timer_init(s->freq0);
    s->timer[1] = arm_timer_init(s->freq1);

    s->timer[0]->irq = qi[0];
    s->timer[1]->irq = qi[1];
    memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
    sysbus_init_mmio(dev, &s->iomem);
    vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
    return 0;
}
Exemplo n.º 24
0
static int stm32_led_init(SysBusDevice *dev, const char* id) {
    stm32_led_state *s = FROM_SYSBUS(stm32_led_state, dev);
    
    
    //Initialisation des pins d'entrées
    qdev_init_gpio_in(&dev->qdev, stm32_led_recvirq, 1);

    //Initialiser le chardev
    s->chr = qdev_init_chardev(&dev->qdev);
    s->chr = qemu_chr_find(id);
    if (s->chr) {
        qemu_chr_add_handlers(s->chr, stm32_can_receive, stm32_receive, stm32_event, s);
    }
    
    stm32_led_reset(s);
    vmstate_register(&dev->qdev, -1, &vmstate_stm32_led, s);

    return 0;
}
Exemplo n.º 25
0
static int at91_pio_init(SysBusDevice *dev)
{
    PIOState *s = FROM_SYSBUS(typeof (*s), dev);
    int pio_regs;

    sysbus_init_irq(dev, &s->parent_irq);
    qdev_init_gpio_in(&dev->qdev, at91_pio_set_pin, PIO_PINS * 3);
    qdev_init_gpio_out(&dev->qdev, s->out, PIO_PINS * 3);

    pio_regs = cpu_register_io_memory(at91_pio_readfn, at91_pio_writefn, s, DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, PIO_SIZE, pio_regs);

    at91_pio_reset(s);
    qemu_register_reset(at91_pio_reset, s);
    //register_savevm(&dev->qdev, "at91_pio", -1, 1, at91_pio_save, at91_pio_load, s);
	
    vmstate_register(&dev->qdev, -1, &vmstate_at91sam9_pio, s);
	return 0;
}
Exemplo n.º 26
0
static int pc98_ide_initfn(ISADevice *dev)
{
    PC98IDEState *s = DO_UPCAST(PC98IDEState, dev, dev);
    int i;

    ide_bus_new(&s->bus[0], &s->dev.qdev, 0);
    ide_bus_new(&s->bus[1], &s->dev.qdev, 1);

    isa_init_irq(dev, &s->irq, s->isairq);
    ide_init2(&s->bus[0], s->irq);
    ide_init2(&s->bus[1], s->irq);

    register_ioport_write(0xf0, 1, 1, pc98_ide_cpu_shutdown, s);
    register_ioport_read(0xf0, 1, 1, pc98_ide_connection_read, s);
    isa_init_ioport(dev, 0xf0);
    register_ioport_write(0x430, 1, 1, pc98_ide_bank_write, s);
    register_ioport_read(0x430, 1, 1, pc98_ide_bank_read, s);
    isa_init_ioport(dev, 0x430);
    register_ioport_write(0x432, 1, 1, pc98_ide_bank_write, s);
    register_ioport_read(0x432, 1, 1, pc98_ide_bank_read, s);
    isa_init_ioport(dev, 0x432);
    for (i = 0; i < 8; i++) {
        register_ioport_write(0x640 + (i << 1), 1, 1, pc98_ide_ioport_write, s);
        register_ioport_read(0x640 + (i << 1), 1, 1, pc98_ide_ioport_read, s);
        isa_init_ioport(dev, 0x640 + (i << 1));
    }
    register_ioport_write(0x640, 2, 2, pc98_ide_data_writew, s);
    register_ioport_read(0x640, 2, 2, pc98_ide_data_readw, s);
    /*isa_init_ioport_range(dev, 0x640, 2);*/
    register_ioport_write(0x640, 4, 4, pc98_ide_data_writel, s);
    register_ioport_read(0x640, 4, 4, pc98_ide_data_readl, s);
    /*isa_init_ioport_range(dev, 0x640, 4);*/
    register_ioport_write(0x74c, 1, 1, pc98_ide_digital_write, s);
    register_ioport_read(0x74c, 1, 1, pc98_ide_status_read, s);
    isa_init_ioport(dev, 0x74c);
    register_ioport_read(0x74e, 1, 1, pc98_ide_digital_read, s);
    isa_init_ioport(dev, 0x74e);

    vmstate_register(&dev->qdev, 0, &vmstate_ide_pc98, s);
    pc98_ide_reset(&dev->qdev);

    return 0;
};
Exemplo n.º 27
0
static int ox820_rps_irq_init(SysBusDevice *dev)
{
    ox820_rps_irq_state *s = FROM_SYSBUS(ox820_rps_irq_state, dev);

    memory_region_init_io(&s->iomem, &ox820_rps_irq_ops, s, "ox820-rps-irq", 0x200);
    sysbus_init_mmio(dev, &s->iomem);
    qdev_init_gpio_in(&dev->qdev, ox820_rps_irq_set_irq, 32);
    sysbus_init_irq(dev, &s->irq);
    sysbus_init_irq(dev, &s->fiq);

    s->int_raw_source = 0;
    s->int_enabled = 0;
    s->fiq_enabled = 0;
    s->fiq_select = 0;
    s->irq_state = 2;
    s->fiq_state = 2;
    vmstate_register(&dev->qdev, -1, &vmstate_ox820_rps_irq, s);
    return 0;
}
Exemplo n.º 28
0
void *vmmouse_init(void *m)
{
    VMMouseState *s = NULL;

    DPRINTF("vmmouse_init\n");

    s = qemu_mallocz(sizeof(VMMouseState));

    s->ps2_mouse = m;
    vmmouse_reset(s);

    vmport_register(VMMOUSE_STATUS, vmmouse_ioport_read, s);
    vmport_register(VMMOUSE_COMMAND, vmmouse_ioport_read, s);
    vmport_register(VMMOUSE_DATA, vmmouse_ioport_read, s);
    vmstate_register(NULL, 0, &vmstate_vmmouse, s);
    qemu_register_reset(vmmouse_reset, s);

    return s;
}
Exemplo n.º 29
0
static int stm32_button_init(SysBusDevice *dev, const char* id) {
    stm32_button_state *s = FROM_SYSBUS(stm32_button_state, dev);
    
    //Initialisation de la pin de sortie
    //Initialisation of the output pin
    qdev_init_gpio_out(&dev->qdev, &s->gpio_out, 1);
    
    //Initialisation du Chardev
    s->chr = qdev_init_chardev(&dev->qdev);
    s->chr = qemu_chr_find(id);
    if (s->chr) {
        qemu_chr_add_handlers(s->chr, stm32_can_receive, stm32_receive, stm32_event, s);
    }
    
    stm32_button_reset(s);
    vmstate_register(&dev->qdev, -1, &vmstate_stm32_button, s);
 
    return 0;
}
Exemplo n.º 30
0
/* CMD646 PCI IDE controller */
static int pci_cmd646_ide_initfn(PCIDevice *dev)
{
    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
    uint8_t *pci_conf = d->dev.config;
    qemu_irq *irq;
    int i;

    pci_conf[PCI_CLASS_PROG] = 0x8f;

    pci_conf[0x51] = 0x04; // enable IDE0
    if (d->secondary) {
        /* XXX: if not enabled, really disable the seconday IDE controller */
        pci_conf[0x51] |= 0x08; /* enable IDE1 */
    }

    setup_cmd646_bar(d, 0);
    setup_cmd646_bar(d, 1);
    pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data);
    pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd);
    pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data);
    pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd);
    bmdma_setup_bar(d);
    pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);

    /* TODO: RST# value should be 0 */
    pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1

    irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
    for (i = 0; i < 2; i++) {
        ide_bus_new(&d->bus[i], &d->dev.qdev, i);
        ide_init2(&d->bus[i], irq[i]);

        bmdma_init(&d->bus[i], &d->bmdma[i], d);
        d->bmdma[i].bus = &d->bus[i];
        qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
                                         &d->bmdma[i].dma);
    }

    vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d);
    qemu_register_reset(cmd646_reset, d);
    return 0;
}