GitHub - KenyStev/Factorial: Factorial FPGA (Diseño Logico Digital)

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commits
_ngo		_ngo
_xmsgs		_xmsgs
iseconfig		iseconfig
isim		isim
planAhead_run_1		planAhead_run_1
xlnx_auto_0_xdb		xlnx_auto_0_xdb
xst/work		xst/work
.lso		.lso
D_register.v		D_register.v
D_register_summary.html		D_register_summary.html
FSM_CL.prj		FSM_CL.prj
FSM_CL.stx		FSM_CL.stx
FSM_CL.v		FSM_CL.v
FSM_CL.xst		FSM_CL.xst
FSM_CL_summary.html		FSM_CL_summary.html
FSM_LOGICA.prj		FSM_LOGICA.prj
FSM_LOGICA.stx		FSM_LOGICA.stx
FSM_LOGICA.v		FSM_LOGICA.v
FSM_LOGICA.xst		FSM_LOGICA.xst
Factorial.gise		Factorial.gise
Factorial.xise		Factorial.xise
FactorialMapeo.ucf		FactorialMapeo.ucf
MUX.v		MUX.v
Main.bld		Main.bld
Main.cmd_log		Main.cmd_log
Main.lso		Main.lso
Main.ncd		Main.ncd
Main.ngc		Main.ngc
Main.ngd		Main.ngd
Main.ngr		Main.ngr
Main.pad		Main.pad
Main.par		Main.par
Main.pcf		Main.pcf
Main.prj		Main.prj
Main.ptwx		Main.ptwx
Main.stx		Main.stx
Main.syr		Main.syr
Main.twr		Main.twr
Main.twx		Main.twx
Main.unroutes		Main.unroutes
Main.ut		Main.ut
Main.v		Main.v
Main.xpi		Main.xpi
Main.xst		Main.xst
Main_bitgen.xwbt		Main_bitgen.xwbt
Main_envsettings.html		Main_envsettings.html
Main_guide.ncd		Main_guide.ncd
Main_isim_beh.exe		Main_isim_beh.exe
Main_map.map		Main_map.map
Main_map.mrp		Main_map.mrp
Main_map.ncd		Main_map.ncd
Main_map.ngm		Main_map.ngm
Main_map.xrpt		Main_map.xrpt
Main_ngdbuild.xrpt		Main_ngdbuild.xrpt
Main_pad.csv		Main_pad.csv
Main_pad.txt		Main_pad.txt
Main_par.xrpt		Main_par.xrpt
Main_summary.html		Main_summary.html
Main_summary.xml		Main_summary.xml
Main_usage.xml		Main_usage.xml
Main_xst.xrpt		Main_xst.xrpt
MapeoFactorial.ucf		MapeoFactorial.ucf
fact_tb.v		fact_tb.v
fact_tb_beh.prj		fact_tb_beh.prj
fact_tb_isim_beh.exe		fact_tb_isim_beh.exe
fact_tb_isim_beh.wdb		fact_tb_isim_beh.wdb
fact_tb_summary.html		fact_tb_summary.html
factorial.v		factorial.v
fuse.log		fuse.log
fuse.xmsgs		fuse.xmsgs
fuseRelaunch.cmd		fuseRelaunch.cmd
isim.cmd		isim.cmd
isim.log		isim.log
main.bgn		main.bgn
main.bit		main.bit
main.drc		main.drc
mapeo.ucf		mapeo.ucf
pa.fromNetlist.tcl		pa.fromNetlist.tcl
planAhead.ngc2edif.log		planAhead.ngc2edif.log
planAhead_pid2124.debug		planAhead_pid2124.debug
usage_statistics_webtalk.html		usage_statistics_webtalk.html
webtalk.log		webtalk.log
webtalk_pn.xml		webtalk_pn.xml
xilinxsim.ini		xilinxsim.ini

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Factorial FPGA (Diseño Logico Digital)

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