##8-Way Set Associative Cache

Verilog Implementation of 8-Way Set Associative Cache

Submitted as a course project for CSF342 Computer Architecture, BITS Pilani K.K. Birla Goa Campus.

###Note I have uploaded this github repo of project only for the curious minds. Since it is likely that some students might stumble upon it while googling their assignments, please use it only for reference purposes and do not copy the code for any kind of assignments.

I will shortly update the detailed working of an 8-way set associative cache on the wiki, till then you can refer to this link: UCSD 8-Way Set Associative Cache

###Design

Calculation of Address bits

Cache Size: 128KB Address bits: 32 Cache Block Size: 64 bytes

Therefore, last 7 bits of address bits are used for byte selection within a block.

No. of blocks = Cache Size/Block Size No. of blocks = 128KB/64B = 2048

This is an 8-way set associative cache. Hence we calculate index bits in address as follows:

Indices = No. of blocks/n (where n is associativity) Indices = 2048/8 = 256 Now, 2^8 = 256, hence we reserve 8 bits from address for indexing.

Finally we get the distribution of address bits as follows: Tag bits: 18 Index bits: 8 Byte select: 6

###File Description All the files with .v extension contain the source code of the project. Rest of the files have been generated by compiling the project in Xilinx ISE.

1. adder.v: 1 bit adder
2. AGtB.v: Takes inputs A and B. Outputs 1 if A>B else 0
3. ALU.v: Implementation of ALU
4. comparator1bit.v: Checks equality of single bit inputs. Outputs 1 for equal inputs, else 0
5. comparator25bit.v: Checks equality of 25 bit inputs. Outputs 1 for equal inputs, else 0
6. comparator3bit.v: Checks equality of 3 bit inputs. Outputs 1 for equal inputs, else 0
7. CtrlCkt.v: Cache control circuit
8. DataWord.v: 32 bit register implementation
9. decoder1to2.v: 1 bit input, 2 bit output to select 1 of the 2 output bits
10. decoder3to8.v: 3 bit input, 8 bit output to select 1 of the 8 output bits
11. decoder4to16.v: 4 bit input, 16 bit output to select 1 of the 16 output bits
12. decoder4to16.v: 5 bit input, 32 bit output to select 1 of the 32 output bits
13. D_ff_instr.v: D flip flop with negedge trigger for instruction
14. D_ff.v: D flip flop implementation with negedge trigger
15. dirtyDM: To mark dirty data memory in cache
16. DMtag.v: Data Memory tag in cache
17. Encoder8to3.v: 8 bit input such that only 1 bit can be high. Encodes that into 3 bit binary output.
18. FIFO.v: FIFO queue implemenation
19. InstrWord.v: Register to store 32 bit instruction in memory.
20. lineCounter.v: Counter logic for replacement of cache contents
21. lineDM.v: Data Memory
22. lineIM.v: Instruction Memory
23. mux16to1_32bits.v: 16 lines of 32 bit inputs. 4 bits select line which is muxed to select an input that is routed to 32 bit output.
24. mux2to1_32bits.v: 2 lines of 32 bit inputs. 1 bit select line which is muxed to select an input that is routed to 32 bit output.
25. mux2to1_5bits.v: 2 lines of 5 bit inputs. 1 bit select line which is muxed to select an input that is routed to 5 bit output.
26. mux2to1_8bits.v: 2 lines of 8 bit inputs. 1 bit select line which is muxed to select an input that is routed to 8 bit output.
27. mux32to1.v: 32 lines of 32 bit inputs. 5 bits select line which is muxed to select an input that is routed to 32 bit output.
28. mux8to1_3bits.v: 8 lines of 3 bit inputs. 3 bits select line which is muxed to select an input that is routed to 3 bit output.
29. mux8to1_64B.v: 8 lines of 3 bit inputs. 3 bits select line which is muxed to select an input that is routed to 3 bit output.
30. prio_Enc.v: Priority Encoder for 8 bit inputs
31. register32bit.v: 32 bit register from D flip flops
32. setDM.v: Set of Data Memory
33. setIM.v: Set of Instruction Memory
34. sExt.v: Sign extends the 10 bit input to 32 bit output.
35. shifter.v: left shifts 25 bit input
36. singleCycle.v: Writes data to memory in single cycle
37. tagIM.v: tag register for Instruction Memory
38. testbench.v: testbench to read and write from cache and test inputs
39. topDM.v Top level DM
40. topIM.v: Top level IM
41. validDM.v: Validity bit of Data Memory as single bit register
42. validIM.v: Validity bit of Instruction Memory as single bit register
43. zExt_5to32.v: Zero extend 5 bit to 32 bit number.
44. zExt.v: Zero extend 10 bit to 32 bit number.