GitHub - bert/SmartSim: Design and simulate digital logic circuits of varying complexity.

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SmartSim

SmartSim is digital logic circuit design and simulation package.
Some of SmartSim's features include:
	* Designing circuits using your own custom components.
	* Simulating circuits interactively, with the ability to explore
	  inside custom components.
	* Creating logic timing diagrams from simulations.
	* Create circuits with loadable and saveable RAM/ROM.
	* Exporting your design or timing diagram to PNG, PDF, and SVG.

SmartSim website:

	http://www.smartsim.org.uk/
	
Contact Maintainer:
	
	ashleynewson@smartsim.org.uk