History

1st October 03:17
Edited cache_sim.c file to suit the grendel's 64 bit architecture. Initially the code was running on 32 bit architecture. The 64 bit architecture was causing the index field to get too long because there was no truncation at 32 bits. The issues was resolved by masking bits using a simple AND gate and testing the code with all Validation outputs and extra runs.

1st October 01:48
Edited Makefile to include 'make clean' which removes object files and final excutable.

1st October 00:44
Code working for all given traces including Extra ones :).

29th September 06:05
Code Working for L1,L1+L2,L1+VC combinations. Validation Runs 0,1,2,4,6 matching except L1+VC Miss Rate. Need to understand how to calculate that.

27th September 03:49
Code working for L1+L2 combination. Validation Runs 0,2,4,6 matching except L2 Miss Rate. The validation output shows the read miss rate instead of the total miss rate comprising of both reads and writes.

27th September 03:38
Code working for L1+L2 combintation. Validation Runs 2,6 matching except L2 Miss Rate. The validation output shows the read miss rate instead of the total miss rate comprising of both reads and writes.

26th September 20:31
Code working wel for Validation Run 4. Showing matching simulation statistics as well. Coded the LRU sequenced output. Now need t start with L2.

26th September 19:05
Code working for Validation Run 4 where we have a direct mapped L1 cache. Need to still get proper formatted output with statistics below.

26th September 12:32
Initial Repository for Cache Simulator: Includes README, cache_sim.c, Makefile. Have coded create_cache, delete_cache functions.