GitHub - krmannix/multicycle-cpu: This is a Multicycle CPU design coded in Verilog Hardware Description Language

krmannix / multicycle-cpu Public

This is a Multicycle CPU design coded in Verilog Hardware Description Language

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
_xmsgs		_xmsgs
iseconfig		iseconfig
isim		isim
ALU.v		ALU.v
ALUControl.v		ALUControl.v
ALUReg.v		ALUReg.v
BranchLogic.v		BranchLogic.v
BreakUpInstr.v		BreakUpInstr.v
Controller.v		Controller.v
DFF.v		DFF.v
DMem.v		DMem.v
IMem.v		IMem.v
IMem_isim_beh.exe		IMem_isim_beh.exe
IMem_stx_beh.prj		IMem_stx_beh.prj
InstructionRegister.v		InstructionRegister.v
MemBlock.v		MemBlock.v
MemoryDataRegister.v		MemoryDataRegister.v
OneBitMux.v		OneBitMux.v
ProgramCounter.v		ProgramCounter.v
ProgramCounter_2.v		ProgramCounter_2.v
Project_Ver2.gise		Project_Ver2.gise
Project_Ver2.xise		Project_Ver2.xise
README.md		README.md
RegFileOutAluInReg.v		RegFileOutAluInReg.v
SignExtendBlock.v		SignExtendBlock.v
TestTop_1.v		TestTop_1.v
TestTop_1_beh.prj		TestTop_1_beh.prj
TestTop_1_isim_beh.exe		TestTop_1_isim_beh.exe
TestTop_1_isim_beh.wdb		TestTop_1_isim_beh.wdb
TestTop_1_stx_beh.prj		TestTop_1_stx_beh.prj
TestTop_1_summary.html		TestTop_1_summary.html
Test_Top2.v		Test_Top2.v
Top.v		Top.v
TwoBitMux.v		TwoBitMux.v
ZeroExtendBlock.v		ZeroExtendBlock.v
add_one.v		add_one.v
fuse.log		fuse.log
fuse.xmsgs		fuse.xmsgs
fuseRelaunch.cmd		fuseRelaunch.cmd
isim.cmd		isim.cmd
isim.log		isim.log
n_bit_mux.v		n_bit_mux.v
nbit_demux.v		nbit_demux.v
nbit_register_file.v		nbit_register_file.v
nbit_register_file2.v		nbit_register_file2.v
nbit_register_file_new.v		nbit_register_file_new.v
new_nbit_register_file.v		new_nbit_register_file.v
xilinxsim.ini		xilinxsim.ini