This project was my first foray into Vivado and the ZyBo development environment for my CPE-439 Realtime embedded systems class at Cal Poly in Spring of 2015. The goal of this project was to set up a software controlled audio (or other signal) DSP architecture for realtime audio effects, equalization, etc. Due to time constraints in the class, this is only a minimal implementation, although I may come back to this project in the future.

The project implements a simple FIR echo filter on audio coming in the line-in input on the ZyBo. The audio codec on the dev board is configured via i2c via software running in FreeRTOS on one of the ARM cores. This configuration takes place through a generated interface driver that uses i2c hardware in the FPGA fabric over the AXI bus.

The audio codec is configured to capture and play stereo 24-bit 48kHz audio via an i2s interface to the FPGA. A simple i2s encoder and decoder pass the samples as parallel 32-bit signed integers to the DSP hardware, which currently consists of a FIFO queue and adder to produce a simple echo effect. The result works quite well and the delay of 8192 samples is nearly imperceptible. The filter has linear phase.

• Ideally the FIFO queue would exist in the ZyBo's much larger DDR RAM rather than in the FPGA fabric, allowing much longer and more complex filters.
• Currently the actual filter difference equation is fixed (and very trivial). A series of muxes could be controlled by software allowing the ZyBo's adders and multipliers to be selected to change the filter function (even in realtime).
• The filter is not implemented using the ZyBo's ~80 DSP cores as they only support up to 24-bit inputs which requires conversion of the 32-bit signed samples currently coming in.\
• Implement audio recording/playback in software.
• Encode/decode audio for storage either in software or hardware.
• Web interface for filter control.

Overall this project served as a great introduction to the Zynq development environment as well as Verilog (I had previously only used VHDL). It was a lot of fun and finally getting ungarbled audio out of the board after many hours of troubleshooting was extremely satisfying. I can't wait to dive into the use of HDMI on this dev board for some other realtime project ideas I have.

• The i2c controller verilog in this repository is not actually used in the project, instead the i2c controller automatically generated by Vivado is used as it is much more easily controlled from software.
• Lots of cleanup is needed as the Vivado IP import/export process is very much overkill for small open source projects, and does not make for a very clean project structure.

This project is free to use and distribute in source and binary forms subject to the licenses of contained derivative works which are available in their respective files.