#README
##1 Introduction
This package provide a set of program to synthesis decoder automatically from encoder. The set of program is in vp/ and other/ directories.
All related paper can be found in https://github.com/shengyushen/dualsyn_paper
##2 Pre-requirement
To use these program, some other linux programs are need:
1 synopsy design compiler: it is used to compile complex verilog source code into relative simpler form, such that our verilog parser can process it. If you dont have design compiler, then we also provide intermediate file dc_synres.v generated by design compiler, such that you can try our programes. 2 gnu develope environment : it include gcc and glibc and so on. it is used to compile our program. 3 Ocaml develop environement: it is used to compile our program.
##3 Usage:
###3.1 adding new path setting into PATH environment source ~/compsyn/scr/setup.scr
###3.2 building our programs d ~/compsyn/ source scr/makeall.scr
###3.3 to try our testbenchs, please go into every sub-dir of ~/compsyn/test/ and there will be a run dir, cd into it, and some options avialable to you
ICCAD'09 and TCAD'10: Incomplete appraoch to check existence of
decoder + ALLSAT
make naive
TCAD'11 : Halting approach based on loop like detection + interpolant
based characterization
make halting
ICCAD'11 : Inferring assertion, this option has been further developed
to include multiple decoder discovering in following TCAD12 option
TCAD'12 : Inferring assertion, and discovering multiple decoder.There
are 5 directories in ~/compsyn/test/:
pcie_noass
scrambler_noass
t2ether_noass
xfi_noass xgxs_noass
NOTICE : PCIE, XGXS and XFI contains some private code that can't
be shared, so only dc_synres.v is provided to replace source code.
Please DONT run "make distclean", which will clean this intermediate
file.
Each of these directories contains a benchmark without assertions.
For example, to infer assertion and generate decoders for
pcie_noass, just run following commands :
cd pcie_noass/run
make infer_multidec_not_charfirst_nowall_cnt
If these commands produce only a resulting_dual_cnf_0.v file, then
only 1 decoder exists. if they produce resulting_dual_cnf_0.v
and resulting_dual_cnf_1.v, then each of them contains a decoder.
to test resulting_dual_cnf_0.v with simulator, just run :
source ../scr/sim.scr 0
similarly, to test resulting_dual_cnf_1.v with simulator, just run :
source ../scr/sim.scr 1
Simulation result will show the value of signal "correct", if
it is always 1, then the generated decoder match exactly the
functionality of its encoder.
TODAES'14 : handling flow control mechanism
there are three dir in ~/compsyn/test/ pcie_relational
t2ether_relational xgxs_relational
These are encoders with flow control mechanism, to run these
benchmark
make relational
it will generate the decoder with flow control mechanism
TODAES'14 revision 1 : handling flow control mechanism faster with
incremental SAT
make relational_plr_inc
newer version : converting minisat interface to support multiple
sat solver at the same time, also dont need deisgn compiler after
generating decoder's verilog code that can directly read by ABC
make multisat