/*
* mt65xx_mon_log: Get the current log from hardware monitors.
* Return a index to the curret log entry in the log buffer.
*/
unsigned int mt65xx_mon_log(void)
{
const unsigned int cur = mt6575_mon_log_buff_index++;
mt6575_mon_log_buff_index %= MON_LOG_BUFF_LEN;
if (mt6575_mon_log_buff) {
mt6575_mon_log_buff[cur].cpu_cyc = armV7_perf_mon_get_cyc_cnt();
mt6575_mon_log_buff[cur].cpu_cnt0 = armV7_perf_mon_get_event_counter(0);
mt6575_mon_log_buff[cur].cpu_cnt1 = armV7_perf_mon_get_event_counter(1);
mt6575_mon_log_buff[cur].cpu_cnt2 = armV7_perf_mon_get_event_counter(2);
mt6575_mon_log_buff[cur].cpu_cnt3 = armV7_perf_mon_get_event_counter(3);
mt6575_mon_log_buff[cur].cpu_cnt4 = armV7_perf_mon_get_event_counter(4);
mt6575_mon_log_buff[cur].cpu_cnt5 = armV7_perf_mon_get_event_counter(5);
mt6575_mon_log_buff[cur].l2c_cnt0 = readl(PL310_BASE + L2X0_EVENT_CNT0_VAL);
mt6575_mon_log_buff[cur].l2c_cnt1 = readl(PL310_BASE + L2X0_EVENT_CNT1_VAL);
mt6575_mon_log_buff[cur].BM_BCNT = BM_GetBusCycCount();
mt6575_mon_log_buff[cur].BM_TACT = BM_GetTransAllCount();
mt6575_mon_log_buff[cur].BM_TSCT = BM_GetTransCount(1);
mt6575_mon_log_buff[cur].BM_WACT = BM_GetWordAllCount();
mt6575_mon_log_buff[cur].BM_WSCT = BM_GetWordCount(1);
mt6575_mon_log_buff[cur].BM_BACT = BM_GetBandwidthWordCount();
mt6575_mon_log_buff[cur].BM_BSCT = BM_GetOverheadWordCount();
mt6575_mon_log_buff[cur].BM_TSCT2 = BM_GetTransCount(2);
mt6575_mon_log_buff[cur].BM_WSCT2 = BM_GetWordCount(2);
mt6575_mon_log_buff[cur].BM_TSCT3 = BM_GetTransCount(3);
mt6575_mon_log_buff[cur].BM_WSCT3 = BM_GetWordCount(3);
mt6575_mon_log_buff[cur].BM_WSCT4 = BM_GetWordCount(4);
mt6575_mon_log_buff[cur].BM_TPCT1 = BM_GetTransTypeCount(1);
mt6575_mon_log_buff[cur].DRAMC_PageHit = DRAMC_GetPageHitCount(DRAMC_ALL);
mt6575_mon_log_buff[cur].DRAMC_PageMiss = DRAMC_GetPageMissCount(DRAMC_ALL);
mt6575_mon_log_buff[cur].DRAMC_Interbank = DRAMC_GetInterbankCount(DRAMC_ALL);
mt6575_mon_log_buff[cur].DRAMC_Idle = DRAMC_GetIdleCount();
}
return cur;
}
/*
* mt65xx_mon_log: Get the current log from hardware monitors.
* Return a index to the curret log entry in the log buffer.
*/
unsigned int mt65xx_mon_log(void* log_buff)
{
struct mt65xx_mon_log* mon_buff;
unsigned int cur;
struct pmu_data *pmu_data = & p_pmu->perf_data;
p_pmu->read_counter();
if( register_mode == MODE_MANUAL_USER || register_mode == MODE_MANUAL_KERNEL){
cur = mt6577_mon_log_buff_index++;
mon_buff = &mt6577_mon_log_buff[cur];
mt6577_mon_log_buff_index %= MON_LOG_BUFF_LEN;
} else {
cur = mt6577_kernel_ring_buff_index++;
mon_buff = (struct mt65xx_mon_log*)log_buff;
}
if (mon_buff) {
mon_buff->cpu_cyc = pmu_data->cnt_val[0][6];
mon_buff->cpu_cnt0 = pmu_data->cnt_val[0][0];
mon_buff->cpu_cnt1 = pmu_data->cnt_val[0][1];
mon_buff->cpu_cnt2 = pmu_data->cnt_val[0][2];
mon_buff->cpu_cnt3 = pmu_data->cnt_val[0][3];
mon_buff->cpu_cnt4 = pmu_data->cnt_val[0][4];
mon_buff->cpu_cnt5 = pmu_data->cnt_val[0][5];
#ifdef CONFIG_SMP
mon_buff->cpu1_cyc = pmu_data->cnt_val[1][6];
mon_buff->cpu1_cnt0 = pmu_data->cnt_val[1][0];
mon_buff->cpu1_cnt1 = pmu_data->cnt_val[1][1];
mon_buff->cpu1_cnt2 = pmu_data->cnt_val[1][2];
mon_buff->cpu1_cnt3 = pmu_data->cnt_val[1][3];
mon_buff->cpu1_cnt4 = pmu_data->cnt_val[1][4];
mon_buff->cpu1_cnt5 = pmu_data->cnt_val[1][5];
#endif
mon_buff->l2c_cnt0 = readl(PL310_BASE + L2X0_EVENT_CNT0_VAL);
mon_buff->l2c_cnt1 = readl(PL310_BASE + L2X0_EVENT_CNT1_VAL);
mon_buff->BM_BCNT = BM_GetBusCycCount();
mon_buff->BM_TACT = BM_GetTransAllCount();
mon_buff->BM_TSCT = BM_GetTransCount(1);
mon_buff->BM_WACT = BM_GetWordAllCount();
mon_buff->BM_WSCT = BM_GetWordCount(1);
mon_buff->BM_BACT = BM_GetBandwidthWordCount();
mon_buff->BM_BSCT = BM_GetOverheadWordCount();
mon_buff->BM_TSCT2 = BM_GetTransCount(2);
mon_buff->BM_WSCT2 = BM_GetWordCount(2);
mon_buff->BM_TSCT3 = BM_GetTransCount(3);
mon_buff->BM_WSCT3 = BM_GetWordCount(3);
mon_buff->BM_WSCT4 = BM_GetWordCount(4);
mon_buff->BM_TPCT1 = BM_GetTransTypeCount(1);
mon_buff->DRAMC_PageHit = DRAMC_GetPageHitCount(DRAMC_ALL);
mon_buff->DRAMC_PageMiss = DRAMC_GetPageMissCount(DRAMC_ALL);
mon_buff->DRAMC_Interbank = DRAMC_GetInterbankCount(DRAMC_ALL);
mon_buff->DRAMC_Idle = DRAMC_GetIdleCount();
}
memset(pmu_data->cnt_val[0], 0, sizeof(struct pmu_data));
return cur;
}
