cystatus EEPROM_Write(const uint8 srcBuf[], const uint8 eepromPtr[], uint32 byteCount) #endif /* (!CY_PSOC3) */ { uint8 writeBuffer[CY_FLASH_SIZEOF_ROW]; uint32 arrayId; uint32 rowId; uint32 dstIndex; uint32 srcIndex; cystatus rc; uint32 eeOffset; uint32 byteOffset; #if (!CY_PSOC4) #if (CYDEV_ECC_ENABLE == 0) uint8 rowBuffer[CY_FLASH_SIZEOF_ROW + CY_FLASH_SIZEOF_ECC_ROW]; #endif /* CYDEV_ECC_ENABLE == 0) */ #endif /* (!CY_PSOC4) */ eeOffset = (uint32)eepromPtr; #if (CY_PSOC3) eeOffset &= EEPROM_CODE_ADDR_MASK; #endif /* (CY_PSOC3) */ /* Make sure, that eepromPtr[] points to ROM */ #if (CY_PSOC3) if (((uint32)eepromPtr >= EEPROM_CODE_ADDR_OFFSET) && (((uint32)eepromPtr + byteCount) <= EEPROM_CODE_ADDR_END)) #else if (((uint32)eepromPtr + byteCount) < EEPROM_FLASH_END_ADDR) #endif /* (CY_PSOC3) */ { #if (!CY_PSOC4) (void)CySetTemp(); #if(CYDEV_ECC_ENABLE == 0) (void)CySetFlashEEBuffer(rowBuffer); #endif #endif /* (!CY_PSOC4) */ arrayId = eeOffset / CY_FLASH_SIZEOF_ARRAY; rowId = (eeOffset / CY_FLASH_SIZEOF_ROW) % EEPROM_ROWS_IN_ARRAY; byteOffset = (CY_FLASH_SIZEOF_ARRAY * arrayId) + (CY_FLASH_SIZEOF_ROW * rowId); srcIndex = 0u; rc = CYRET_SUCCESS; while ((srcIndex < byteCount) && (CYRET_SUCCESS == rc)) { /* Copy data to the write buffer either from the source buffer or from the flash */ for (dstIndex = 0u; dstIndex < CY_FLASH_SIZEOF_ROW; dstIndex++) { if ((byteOffset >= eeOffset) && (srcIndex < byteCount)) { writeBuffer[dstIndex] = srcBuf[srcIndex]; srcIndex++; } else { writeBuffer[dstIndex] = CY_GET_XTND_REG8(CYDEV_FLASH_BASE + byteOffset); } byteOffset++; } /* Write flash row */ #if (CY_PSOC4) rc = CySysFlashWriteRow(rowId, writeBuffer); #else rc = CyWriteRowData((uint8)arrayId, (uint16)rowId, writeBuffer); #endif /* (CY_PSOC4) */ /* Go to the next row */ rowId++; #if (CY_FLASH_NUMBER_ARRAYS > 1) if (rowId >= EEPROM_ROWS_IN_ARRAY) { arrayId++; rowId = 0u; } #endif /* (CY_FLASH_NUMBER_ARRAYS > 1) */ } /* Flush both Cache and PHUB prefetch buffer */ #if (CY_PSOC5) CyFlushCache(); #elif (CY_PSOC3) CY_FLASH_CONTROL_REG |= 6u; #endif /* (CY_PSOC5) */ } else { rc = CYRET_BAD_PARAM; } /* Mask return codes from flash, if they are not supported */ if ((CYRET_SUCCESS != rc) && (CYRET_BAD_PARAM != rc)) { rc = CYRET_UNKNOWN; } return (rc); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F3038u, /* Base address: 0x400F3000 Count: 56 */ 0x400F3138u, /* Base address: 0x400F3100 Count: 56 */ 0x400F3222u, /* Base address: 0x400F3200 Count: 34 */ 0x400F3344u, /* Base address: 0x400F3300 Count: 68 */ 0x400F400Bu, /* Base address: 0x400F4000 Count: 11 */ 0x400F410Fu, /* Base address: 0x400F4100 Count: 15 */ 0x400F420Eu, /* Base address: 0x400F4200 Count: 14 */ 0x400F4313u, /* Base address: 0x400F4300 Count: 19 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x00u, 0x01u}, {0x03u, 0x0Fu}, {0x04u, 0x01u}, {0x05u, 0x0Fu}, {0x09u, 0x0Fu}, {0x0Au, 0x01u}, {0x0Du, 0x02u}, {0x0Eu, 0x01u}, {0x0Fu, 0x01u}, {0x11u, 0x08u}, {0x12u, 0x01u}, {0x13u, 0x01u}, {0x15u, 0x04u}, {0x16u, 0x01u}, {0x17u, 0x01u}, {0x18u, 0x01u}, {0x19u, 0x0Fu}, {0x1Cu, 0x01u}, {0x1Du, 0x0Fu}, {0x22u, 0x01u}, {0x23u, 0x0Fu}, {0x24u, 0x01u}, {0x25u, 0x0Fu}, {0x2Au, 0x01u}, {0x2Bu, 0x0Fu}, {0x2Eu, 0x01u}, {0x2Fu, 0x0Fu}, {0x32u, 0x01u}, {0x35u, 0x01u}, {0x37u, 0x0Eu}, {0x38u, 0x08u}, {0x39u, 0xA0u}, {0x3Eu, 0x04u}, {0x3Fu, 0x50u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Fu, 0x01u}, {0x84u, 0x01u}, {0x85u, 0x08u}, {0x89u, 0x04u}, {0x98u, 0x02u}, {0x99u, 0x01u}, {0xACu, 0x04u}, {0xADu, 0x02u}, {0xB0u, 0x02u}, {0xB1u, 0x04u}, {0xB2u, 0x04u}, {0xB3u, 0x02u}, {0xB4u, 0x01u}, {0xB5u, 0x08u}, {0xB7u, 0x01u}, {0xD8u, 0x0Bu}, {0xD9u, 0x0Bu}, {0xDBu, 0x04u}, {0xDCu, 0x99u}, {0xDFu, 0x01u}, {0x02u, 0x89u}, {0x03u, 0x20u}, {0x05u, 0x08u}, {0x08u, 0x99u}, {0x0Eu, 0x08u}, {0x10u, 0x40u}, {0x12u, 0x02u}, {0x13u, 0x28u}, {0x17u, 0x80u}, {0x19u, 0x04u}, {0x1Eu, 0xA0u}, {0x1Fu, 0x20u}, {0x22u, 0x50u}, {0x24u, 0x84u}, {0x26u, 0x0Au}, {0x27u, 0x09u}, {0x28u, 0x68u}, {0x2Au, 0x80u}, {0x2Bu, 0x24u}, {0x2Du, 0x40u}, {0x30u, 0x91u}, {0x31u, 0x10u}, {0x32u, 0x88u}, {0x33u, 0x01u}, {0x35u, 0x20u}, {0x38u, 0x86u}, {0x3Au, 0x51u}, {0x3Bu, 0x08u}, {0x3Du, 0x20u}, {0x3Eu, 0x04u}, {0x5Du, 0x01u}, {0x5Eu, 0xA0u}, {0x5Fu, 0x04u}, {0x64u, 0x20u}, {0x66u, 0x42u}, {0x67u, 0x08u}, {0x7Fu, 0x80u}, {0x82u, 0x04u}, {0x83u, 0x80u}, {0x84u, 0x01u}, {0x85u, 0x01u}, {0x86u, 0x08u}, {0x87u, 0x04u}, {0x88u, 0x04u}, {0x8Cu, 0x0Cu}, {0x8Eu, 0x02u}, {0x8Fu, 0x04u}, {0xC0u, 0x2Fu}, {0xC2u, 0x4Fu}, {0xC4u, 0x8Fu}, {0xCAu, 0x1Fu}, {0xCCu, 0x2Fu}, {0xCEu, 0x6Fu}, {0xD6u, 0xF0u}, {0xD8u, 0xF0u}, {0xDEu, 0x80u}, {0x01u, 0x08u}, {0x02u, 0x01u}, {0x04u, 0x02u}, {0x05u, 0x04u}, {0x08u, 0x01u}, {0x0Cu, 0x04u}, {0x0Du, 0x02u}, {0x14u, 0x08u}, {0x1Cu, 0x01u}, {0x22u, 0x01u}, {0x29u, 0x01u}, {0x2Au, 0x01u}, {0x30u, 0x02u}, {0x31u, 0x01u}, {0x32u, 0x04u}, {0x33u, 0x04u}, {0x34u, 0x08u}, {0x35u, 0x08u}, {0x36u, 0x01u}, {0x37u, 0x02u}, {0x3Eu, 0x40u}, {0x58u, 0x0Bu}, {0x59u, 0x0Bu}, {0x5Bu, 0x04u}, {0x5Cu, 0x99u}, {0x5Fu, 0x01u}, {0x9Cu, 0x01u}, {0xA4u, 0x02u}, {0xB2u, 0x01u}, {0xB4u, 0x02u}, {0xD8u, 0x0Bu}, {0xDBu, 0x04u}, {0xDCu, 0x09u}, {0xDFu, 0x01u}, {0x04u, 0x4Au}, {0x05u, 0x10u}, {0x06u, 0x40u}, {0x0Au, 0x01u}, {0x0Cu, 0x80u}, {0x0Du, 0x80u}, {0x0Fu, 0x10u}, {0x10u, 0x20u}, {0x14u, 0x40u}, {0x17u, 0x20u}, {0x19u, 0x20u}, {0x1Bu, 0x04u}, {0x1Eu, 0xA4u}, {0x1Fu, 0x80u}, {0x25u, 0x28u}, {0x26u, 0x01u}, {0x27u, 0x02u}, {0x2Cu, 0x08u}, {0x3Cu, 0x08u}, {0x3Eu, 0x40u}, {0x3Fu, 0x02u}, {0x45u, 0x28u}, {0x46u, 0x28u}, {0x58u, 0x01u}, {0x59u, 0x04u}, {0x5Au, 0xA0u}, {0x5Bu, 0x02u}, {0x5Du, 0x20u}, {0x5Eu, 0x86u}, {0x64u, 0x01u}, {0x66u, 0x2Au}, {0x7Bu, 0x80u}, {0x7Fu, 0x80u}, {0x80u, 0x80u}, {0x86u, 0x92u}, {0x87u, 0x20u}, {0x88u, 0x40u}, {0x89u, 0x80u}, {0x8Au, 0x50u}, {0x8Du, 0x10u}, {0x90u, 0x48u}, {0x92u, 0xE1u}, {0x93u, 0x10u}, {0x94u, 0x02u}, {0x99u, 0x04u}, {0x9Cu, 0xC0u}, {0x9Du, 0x10u}, {0x9Eu, 0x90u}, {0x9Fu, 0x20u}, {0xA0u, 0x2Cu}, {0xA3u, 0x01u}, {0xA4u, 0x80u}, {0xA7u, 0x84u}, {0xA9u, 0x70u}, {0xADu, 0x08u}, {0xAEu, 0x05u}, {0xB0u, 0x20u}, {0xB3u, 0x11u}, {0xB4u, 0x40u}, {0xB6u, 0x40u}, {0xC0u, 0xF0u}, {0xC2u, 0xA1u}, {0xC4u, 0x54u}, {0xCAu, 0x20u}, {0xCEu, 0xD0u}, {0xD6u, 0xFEu}, {0xD8u, 0xF0u}, {0xDEu, 0x81u}, {0x03u, 0x88u}, {0x05u, 0x10u}, {0x07u, 0x20u}, {0x0Au, 0x18u}, {0x0Cu, 0x80u}, {0x0Du, 0x08u}, {0x83u, 0xA0u}, {0xC0u, 0xF0u}, {0xC2u, 0xF0u}, {0xE0u, 0x80u}, {0xE4u, 0x20u}, {0x02u, 0x10u}, {0x05u, 0x04u}, {0x81u, 0x04u}, {0x86u, 0x10u}, {0xA9u, 0x10u}, {0xAAu, 0x10u}, {0xABu, 0x08u}, {0xACu, 0x80u}, {0xADu, 0x08u}, {0xAEu, 0x04u}, {0xC0u, 0x30u}, {0xE0u, 0x40u}, {0xE4u, 0x80u}, {0xE8u, 0xD0u}, {0xECu, 0xB0u}, {0x00u, 0x20u}, {0x02u, 0x20u}, {0x06u, 0x80u}, {0x07u, 0x04u}, {0x08u, 0x20u}, {0x09u, 0x04u}, {0x0Fu, 0x48u}, {0x8Bu, 0x40u}, {0x8Eu, 0x20u}, {0x8Fu, 0x04u}, {0xC0u, 0x0Fu}, {0xC2u, 0x0Fu}, {0xE2u, 0x0Cu}, {0xE6u, 0x08u}, {0x01u, 0x08u}, {0x06u, 0x80u}, {0x08u, 0x20u}, {0x0Bu, 0x20u}, {0x0Eu, 0x01u}, {0x88u, 0x20u}, {0x8Au, 0x81u}, {0x8Bu, 0x10u}, {0x8Du, 0x08u}, {0xB0u, 0x30u}, {0xB2u, 0x80u}, {0xB5u, 0x04u}, {0xB7u, 0x04u}, {0xC0u, 0x0Cu}, {0xC2u, 0x0Bu}, {0xE2u, 0x07u}, {0xE6u, 0x05u}, {0xEAu, 0x03u}, {0xEEu, 0x07u}, {0x02u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x0000FFFFu); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x55550000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0x24050000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG4), 0x55550000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG4), 0x51050000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x000000FFu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00249249u); /* IOPINS0_1 Starting address: CYDEV_PRT1_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000044u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x0008ED89u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_INTCFG), 0x00001000u); /* IOPINS0_2 Starting address: CYDEV_PRT2_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_DR), 0x000000FFu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00249249u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x00000020u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00261D89u); /* IOPINS0_4 Starting address: CYDEV_PRT4_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x0000000Du); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000D8Eu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x0000000Du); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F3004u, /* Base address: 0x400F3000 Count: 4 */ 0x400F3101u, /* Base address: 0x400F3100 Count: 1 */ 0x400F3301u, /* Base address: 0x400F3300 Count: 1 */ 0x400F4203u, /* Base address: 0x400F4200 Count: 3 */ 0x400F4306u, /* Base address: 0x400F4300 Count: 6 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x38u, 0x80u}, {0x3Eu, 0x40u}, {0x58u, 0x04u}, {0x5Fu, 0x01u}, {0x18u, 0x01u}, {0xB4u, 0x01u}, {0x6Cu, 0x40u}, {0x70u, 0x08u}, {0xDCu, 0x03u}, {0x61u, 0x02u}, {0xA1u, 0x02u}, {0xB4u, 0x48u}, {0xB5u, 0x02u}, {0xD8u, 0x02u}, {0xECu, 0x08u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EEEEu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000099u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x20000000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_PRT0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT0_BASE), 0x000000FFu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC2), 0x000000FFu); /* IOPINS0_1 Starting address: CYDEV_PRT1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT1_BASE), 0x0000000Fu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00180000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC2), 0x0000000Fu); /* IOPINS0_3 Starting address: CYDEV_PRT3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT3_BASE), 0x00000003u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000DA4u); /* IOPINS0_4 Starting address: CYDEV_PRT4_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT4_BASE), 0x00000006u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000031u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x00000006u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; /* Enable the clock in the interrupt controller for the routed interrupts */ CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u); { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F3204u, /* Base address: 0x400F3200 Count: 4 */ 0x400F3305u, /* Base address: 0x400F3300 Count: 5 */ 0x400F400Bu, /* Base address: 0x400F4000 Count: 11 */ 0x400F4108u, /* Base address: 0x400F4100 Count: 8 */ 0x400F4204u, /* Base address: 0x400F4200 Count: 4 */ 0x400F430Fu, /* Base address: 0x400F4300 Count: 15 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x38u, 0x80u}, {0x3Eu, 0x40u}, {0x58u, 0x04u}, {0x5Fu, 0x01u}, {0x1Fu, 0x80u}, {0x83u, 0x80u}, {0xE4u, 0x04u}, {0xE6u, 0x21u}, {0xEAu, 0x20u}, {0x0Fu, 0x80u}, {0x2Fu, 0x80u}, {0x5Bu, 0x01u}, {0x6Fu, 0x80u}, {0x77u, 0x40u}, {0x78u, 0x80u}, {0xC2u, 0x20u}, {0xCAu, 0x80u}, {0xD6u, 0x40u}, {0xDCu, 0xC0u}, {0xDEu, 0x20u}, {0x4Fu, 0x80u}, {0x83u, 0x40u}, {0x8Bu, 0x01u}, {0x9Fu, 0x41u}, {0xA3u, 0x40u}, {0xB0u, 0x80u}, {0xD2u, 0x20u}, {0xE6u, 0x80u}, {0x6Eu, 0x02u}, {0x75u, 0x10u}, {0x7Au, 0x01u}, {0xDCu, 0x03u}, {0x1Cu, 0x80u}, {0x29u, 0x04u}, {0x2Fu, 0x10u}, {0x67u, 0x02u}, {0x81u, 0x14u}, {0x83u, 0x01u}, {0x88u, 0x40u}, {0x97u, 0x20u}, {0x9Du, 0x10u}, {0xB3u, 0x10u}, {0xC6u, 0x04u}, {0xCAu, 0x03u}, {0xD6u, 0x01u}, {0xE6u, 0x04u}, {0xEAu, 0x04u}, {0x02u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x03000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00000808u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000090u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x0A000000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0x0A080000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG4), 0x00200000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x10000000u); /* TCPWM_CNT0 Starting address: CYDEV_TCPWM_CNT0_TR_CTRL0 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT0_TR_CTRL0), 0x000FFF10u); /* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x00000038u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x0000005Fu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00D8A000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_INTCFG), 0x00000200u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC2), 0x0000000Fu); /* IOPINS0_1 Starting address: CYDEV_PRT1_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x000000CDu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x0000918Eu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_INTCFG), 0x00000008u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC2), 0x000000C8u); /* IOPINS0_2 Starting address: CYDEV_PRT2_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_DR), 0x000000C3u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00000C40u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_INTCFG), 0x00000020u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC2), 0x000000C3u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u); /* IOPINS0_4 Starting address: CYDEV_PRT4_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x00000006u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000030u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x00000006u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; /* Enable the clock in the interrupt controller for the routed interrupts */ CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u); { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F0001u, /* Base address: 0x400F0000 Count: 1 */ 0x400F3052u, /* Base address: 0x400F3000 Count: 82 */ 0x400F3125u, /* Base address: 0x400F3100 Count: 37 */ 0x400F3244u, /* Base address: 0x400F3200 Count: 68 */ 0x400F3333u, /* Base address: 0x400F3300 Count: 51 */ 0x400F4009u, /* Base address: 0x400F4000 Count: 9 */ 0x400F410Du, /* Base address: 0x400F4100 Count: 13 */ 0x400F4204u, /* Base address: 0x400F4200 Count: 4 */ 0x400F430Eu, /* Base address: 0x400F4300 Count: 14 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x83u, 0x6Fu}, {0x04u, 0x0Cu}, {0x06u, 0x30u}, {0x08u, 0x28u}, {0x0Au, 0x14u}, {0x0Cu, 0x01u}, {0x14u, 0x14u}, {0x15u, 0x96u}, {0x16u, 0x28u}, {0x17u, 0x69u}, {0x19u, 0x0Fu}, {0x1Au, 0x03u}, {0x1Bu, 0xF0u}, {0x25u, 0x33u}, {0x27u, 0xCCu}, {0x28u, 0x0Cu}, {0x29u, 0x55u}, {0x2Au, 0x70u}, {0x2Bu, 0xAAu}, {0x30u, 0x02u}, {0x32u, 0x40u}, {0x33u, 0xFFu}, {0x34u, 0x3Cu}, {0x35u, 0xFFu}, {0x36u, 0x01u}, {0x3Eu, 0x40u}, {0x40u, 0x10u}, {0x41u, 0x02u}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, {0x4Bu, 0xFFu}, {0x4Du, 0xA0u}, {0x4Fu, 0x01u}, {0x50u, 0x18u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Au, 0x04u}, {0x5Fu, 0x01u}, {0x60u, 0x40u}, {0x62u, 0x80u}, {0x64u, 0x40u}, {0x65u, 0x40u}, {0x66u, 0x80u}, {0x68u, 0x40u}, {0x6Au, 0x80u}, {0x6Cu, 0x40u}, {0x6Du, 0x20u}, {0x6Eu, 0x80u}, {0x82u, 0x01u}, {0x86u, 0x02u}, {0x8Au, 0x04u}, {0x96u, 0x08u}, {0x9Au, 0x10u}, {0xA4u, 0x09u}, {0xA6u, 0x06u}, {0xACu, 0x05u}, {0xAEu, 0x0Au}, {0xB0u, 0x0Fu}, {0xB4u, 0x10u}, {0xBEu, 0x01u}, {0xC0u, 0x50u}, {0xC1u, 0x06u}, {0xC9u, 0xFFu}, {0xCAu, 0xFFu}, {0xCBu, 0xFFu}, {0xCDu, 0xAFu}, {0xCEu, 0x07u}, {0xCFu, 0x01u}, {0xD0u, 0x18u}, {0xD8u, 0x04u}, {0xDAu, 0x04u}, {0xDBu, 0x04u}, {0xDFu, 0x01u}, {0xE0u, 0x40u}, {0xE2u, 0x80u}, {0xE4u, 0x40u}, {0xE5u, 0x40u}, {0xE6u, 0x80u}, {0xE8u, 0x40u}, {0xEAu, 0x80u}, {0xECu, 0x40u}, {0xEDu, 0x20u}, {0xEEu, 0x80u}, {0x00u, 0x48u}, {0x03u, 0x08u}, {0x05u, 0x2Au}, {0x09u, 0x20u}, {0x0Au, 0x10u}, {0x0Cu, 0x10u}, {0x0Du, 0x04u}, {0x12u, 0x08u}, {0x15u, 0x40u}, {0x17u, 0x04u}, {0x18u, 0x45u}, {0x19u, 0x04u}, {0x1Au, 0x1Au}, {0x1Bu, 0x20u}, {0x1Cu, 0x88u}, {0x1Du, 0x10u}, {0x21u, 0x28u}, {0x29u, 0x04u}, {0x2Bu, 0x08u}, {0x31u, 0x10u}, {0x32u, 0x08u}, {0x40u, 0x05u}, {0x4Eu, 0x05u}, {0x6Du, 0x40u}, {0x6Fu, 0x04u}, {0x81u, 0x08u}, {0x86u, 0x08u}, {0x89u, 0x04u}, {0xC0u, 0x77u}, {0xC2u, 0x66u}, {0xC4u, 0xA2u}, {0xCAu, 0x06u}, {0xCCu, 0x06u}, {0xD0u, 0x0Cu}, {0xD2u, 0x30u}, {0xE2u, 0x08u}, {0xE4u, 0x80u}, {0x39u, 0x02u}, {0x40u, 0x50u}, {0x41u, 0x06u}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, {0x4Bu, 0xFFu}, {0x4Du, 0xAFu}, {0x4Eu, 0x07u}, {0x4Fu, 0x01u}, {0x50u, 0x18u}, {0x59u, 0x04u}, {0x5Au, 0x04u}, {0x5Cu, 0x80u}, {0x5Fu, 0x21u}, {0x60u, 0x40u}, {0x62u, 0x80u}, {0x64u, 0x40u}, {0x65u, 0x40u}, {0x66u, 0x80u}, {0x68u, 0x40u}, {0x6Au, 0x80u}, {0x6Cu, 0x40u}, {0x6Du, 0x20u}, {0x6Eu, 0x80u}, {0x8Cu, 0x01u}, {0x8Fu, 0x03u}, {0x94u, 0x04u}, {0x95u, 0x01u}, {0xA2u, 0x0Cu}, {0xA6u, 0x03u}, {0xB0u, 0x02u}, {0xB2u, 0x08u}, {0xB3u, 0x02u}, {0xB4u, 0x04u}, {0xB6u, 0x01u}, {0xB7u, 0x01u}, {0xBEu, 0x50u}, {0xBFu, 0x40u}, {0xC0u, 0x10u}, {0xC1u, 0x02u}, {0xC5u, 0x35u}, {0xC6u, 0xC2u}, {0xC7u, 0x0Eu}, {0xC8u, 0x1Fu}, {0xC9u, 0xFFu}, {0xCAu, 0xFFu}, {0xCBu, 0xFFu}, {0xCDu, 0xAFu}, {0xCEu, 0x07u}, {0xCFu, 0x01u}, {0xD0u, 0x18u}, {0xD4u, 0x0Fu}, {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDAu, 0x04u}, {0xDBu, 0x04u}, {0xDFu, 0x01u}, {0xE0u, 0x40u}, {0xE2u, 0x80u}, {0xE4u, 0x40u}, {0xE5u, 0x40u}, {0xE6u, 0x80u}, {0xE8u, 0x40u}, {0xEAu, 0x80u}, {0xECu, 0x40u}, {0xEDu, 0x20u}, {0xEEu, 0x80u}, {0x00u, 0x40u}, {0x0Au, 0x10u}, {0x10u, 0xA0u}, {0x18u, 0x40u}, {0x19u, 0x40u}, {0x1Au, 0x14u}, {0x22u, 0x08u}, {0x23u, 0x02u}, {0x27u, 0x80u}, {0x32u, 0x08u}, {0x38u, 0x80u}, {0x40u, 0x01u}, {0x43u, 0x20u}, {0x48u, 0xA0u}, {0x4Eu, 0x05u}, {0x50u, 0x40u}, {0x51u, 0x08u}, {0x52u, 0x10u}, {0x59u, 0x40u}, {0x5Au, 0x04u}, {0x5Bu, 0x22u}, {0x61u, 0x08u}, {0x62u, 0x12u}, {0x7Eu, 0x20u}, {0x80u, 0x40u}, {0x81u, 0x28u}, {0x83u, 0x20u}, {0x84u, 0x40u}, {0x8Au, 0x02u}, {0x8Du, 0x02u}, {0x8Eu, 0x20u}, {0x8Fu, 0x80u}, {0x90u, 0x01u}, {0x92u, 0x0Au}, {0x9Du, 0x2Au}, {0xA0u, 0x40u}, {0xA3u, 0x20u}, {0xB0u, 0x10u}, {0xB3u, 0x08u}, {0xC0u, 0x01u}, {0xC2u, 0x04u}, {0xC4u, 0x0Cu}, {0xCCu, 0x02u}, {0xCEu, 0x08u}, {0xD0u, 0x0Cu}, {0xD2u, 0x30u}, {0xD6u, 0x0Fu}, {0xD8u, 0x07u}, {0xDEu, 0x40u}, {0xE0u, 0x40u}, {0xE6u, 0x20u}, {0x0Bu, 0x10u}, {0x5Fu, 0x20u}, {0x6Bu, 0x01u}, {0x83u, 0x20u}, {0x8Bu, 0x10u}, {0xC2u, 0x10u}, {0xD6u, 0x20u}, {0xDAu, 0x40u}, {0xE2u, 0x80u}, {0x03u, 0x88u}, {0x05u, 0x10u}, {0x4Au, 0x02u}, {0x81u, 0x10u}, {0x83u, 0x08u}, {0x86u, 0x02u}, {0x8Bu, 0x01u}, {0x8Fu, 0x80u}, {0x9Fu, 0x01u}, {0xC0u, 0xD0u}, {0xD2u, 0x10u}, {0xE2u, 0x40u}, {0xE4u, 0xA0u}, {0x0Bu, 0x80u}, {0x0Du, 0x01u}, {0x87u, 0x40u}, {0xC2u, 0x0Cu}, {0x09u, 0x01u}, {0x1Cu, 0x10u}, {0x30u, 0x08u}, {0x60u, 0x10u}, {0x8Cu, 0x08u}, {0x8Du, 0x01u}, {0xB1u, 0x01u}, {0xC2u, 0x08u}, {0xC6u, 0x04u}, {0xCCu, 0x02u}, {0xD8u, 0x02u}, {0xE2u, 0x08u}, {0xE4u, 0x08u}, {0xEAu, 0x04u}, {0x10u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00000030u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x000000E0u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0002EE00u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x0000000Eu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL7), 0x000000EEu); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x02000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x000C0000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0x00A20000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x02000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG12), 0x00000200u); /* TCPWM_CNT0 Starting address: CYDEV_TCPWM_CNT0_TR_CTRL0 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT0_TR_CTRL0), 0x000EEE1Eu); /* INT_SELECT Starting address: CYDEV_CPUSS_INT_SEL */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INT_SEL), 0x00000001u); /* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000001u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT0_BASE), 0x00000002u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00001DB6u); /* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000082u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x00000266u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC2), 0x00000080u); /* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT2_BASE), 0x0000000Fu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00009000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC2), 0x0000000Fu); /* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x00000031u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00032D86u); /* IOPINS0_4 Starting address: CYDEV_GPIO_PRT4_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT4_BASE), 0x00000001u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT4_PC), 0x00000004u); /* IOPINS0_5 Starting address: CYDEV_GPIO_PRT5_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT5_PC), 0x00030C00u); /* IOPINS0_7 Starting address: CYDEV_GPIO_PRT7_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT7_BASE), 0x00000003u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT7_PC), 0x00000024u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F0001u, /* Base address: 0x400F0000 Count: 1 */ 0x400F3010u, /* Base address: 0x400F3000 Count: 16 */ 0x400F3136u, /* Base address: 0x400F3100 Count: 54 */ 0x400F3248u, /* Base address: 0x400F3200 Count: 72 */ 0x400F3344u, /* Base address: 0x400F3300 Count: 68 */ 0x400F4202u, /* Base address: 0x400F4200 Count: 2 */ 0x400F430Au, /* Base address: 0x400F4300 Count: 10 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x81u, 0x0Fu}, {0x00u, 0x01u}, {0x02u, 0x02u}, {0x10u, 0x04u}, {0x17u, 0x01u}, {0x18u, 0x06u}, {0x19u, 0x01u}, {0x1Au, 0x01u}, {0x23u, 0x01u}, {0x2Cu, 0x04u}, {0x30u, 0x07u}, {0x37u, 0x01u}, {0x3Au, 0x02u}, {0x3Fu, 0x40u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Fu, 0x01u}, {0x03u, 0x40u}, {0x04u, 0x80u}, {0x05u, 0x04u}, {0x06u, 0x84u}, {0x08u, 0x10u}, {0x0Au, 0x40u}, {0x0Cu, 0x10u}, {0x0Eu, 0x92u}, {0x10u, 0x02u}, {0x16u, 0x20u}, {0x17u, 0x19u}, {0x18u, 0x80u}, {0x19u, 0x02u}, {0x1Au, 0x40u}, {0x1Bu, 0x01u}, {0x1Eu, 0x80u}, {0x22u, 0x40u}, {0x26u, 0x80u}, {0x27u, 0x08u}, {0x29u, 0x02u}, {0x2Bu, 0x40u}, {0x2Du, 0x02u}, {0x2Eu, 0x20u}, {0x2Fu, 0x01u}, {0x30u, 0x10u}, {0x31u, 0x14u}, {0x35u, 0x14u}, {0x37u, 0x01u}, {0x3Cu, 0x80u}, {0x3Du, 0x01u}, {0x3Eu, 0x14u}, {0x44u, 0x98u}, {0x47u, 0x40u}, {0x4Du, 0x08u}, {0x4Fu, 0x80u}, {0x54u, 0x82u}, {0x56u, 0x54u}, {0x62u, 0x80u}, {0x63u, 0x01u}, {0x67u, 0x03u}, {0x6Cu, 0x20u}, {0x6Du, 0x41u}, {0x6Eu, 0x16u}, {0x6Fu, 0x11u}, {0x74u, 0x40u}, {0xC0u, 0xF8u}, {0xC2u, 0xFAu}, {0xC4u, 0x71u}, {0xCAu, 0xB1u}, {0xCCu, 0xE6u}, {0xCEu, 0xF0u}, {0xD0u, 0xF0u}, {0xD2u, 0x10u}, {0xD8u, 0x10u}, {0x00u, 0x1Au}, {0x01u, 0x02u}, {0x03u, 0x08u}, {0x04u, 0x13u}, {0x05u, 0x1Du}, {0x06u, 0x04u}, {0x08u, 0x01u}, {0x09u, 0x1Du}, {0x0Au, 0x18u}, {0x0Cu, 0x18u}, {0x0Du, 0x1Du}, {0x0Eu, 0x02u}, {0x10u, 0x02u}, {0x11u, 0x0Du}, {0x13u, 0x10u}, {0x14u, 0x02u}, {0x16u, 0x18u}, {0x19u, 0x02u}, {0x1Bu, 0x04u}, {0x1Cu, 0x1Cu}, {0x1Du, 0x02u}, {0x1Eu, 0x03u}, {0x1Fu, 0x0Du}, {0x20u, 0x1Au}, {0x23u, 0x10u}, {0x24u, 0x18u}, {0x28u, 0x18u}, {0x29u, 0x01u}, {0x2Au, 0x02u}, {0x2Bu, 0x02u}, {0x2Du, 0x1Du}, {0x31u, 0x0Fu}, {0x32u, 0x13u}, {0x34u, 0x0Fu}, {0x35u, 0x10u}, {0x3Au, 0x20u}, {0x3Bu, 0x02u}, {0x3Fu, 0x10u}, {0x54u, 0x40u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, {0x5Fu, 0x01u}, {0x80u, 0x08u}, {0x82u, 0x06u}, {0x84u, 0x08u}, {0x86u, 0x06u}, {0x8Au, 0x04u}, {0x8Eu, 0x01u}, {0x90u, 0x01u}, {0x91u, 0x0Eu}, {0x94u, 0x01u}, {0x95u, 0x03u}, {0x97u, 0x04u}, {0x98u, 0x0Au}, {0x99u, 0x05u}, {0x9Bu, 0x0Au}, {0xA0u, 0x01u}, {0xA4u, 0x01u}, {0xADu, 0x04u}, {0xAFu, 0x09u}, {0xB0u, 0x01u}, {0xB1u, 0x0Fu}, {0xB2u, 0x06u}, {0xB6u, 0x08u}, {0xB9u, 0x02u}, {0xBEu, 0x41u}, {0xD4u, 0x09u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDFu, 0x01u}, {0x00u, 0x08u}, {0x01u, 0x42u}, {0x03u, 0x09u}, {0x05u, 0x14u}, {0x06u, 0x80u}, {0x07u, 0x01u}, {0x0Au, 0x50u}, {0x0Bu, 0x08u}, {0x0Cu, 0x02u}, {0x0Du, 0x01u}, {0x0Eu, 0x10u}, {0x0Fu, 0x02u}, {0x10u, 0x20u}, {0x11u, 0x01u}, {0x15u, 0x01u}, {0x17u, 0x18u}, {0x18u, 0x40u}, {0x19u, 0x41u}, {0x1Bu, 0x08u}, {0x1Cu, 0x08u}, {0x1Du, 0x14u}, {0x1Fu, 0x04u}, {0x21u, 0x02u}, {0x25u, 0x20u}, {0x27u, 0x40u}, {0x2Bu, 0x01u}, {0x2Cu, 0x80u}, {0x2Fu, 0x05u}, {0x31u, 0x16u}, {0x35u, 0x10u}, {0x37u, 0x41u}, {0x39u, 0x01u}, {0x3Bu, 0x02u}, {0x3Cu, 0x80u}, {0x3Eu, 0xD4u}, {0x3Fu, 0x02u}, {0x40u, 0xC0u}, {0x45u, 0x20u}, {0x46u, 0x08u}, {0x59u, 0x29u}, {0x5Au, 0x80u}, {0x61u, 0x40u}, {0x66u, 0x58u}, {0x85u, 0x21u}, {0x8Bu, 0x08u}, {0x91u, 0x41u}, {0x92u, 0x94u}, {0x99u, 0x0Au}, {0x9Au, 0x50u}, {0x9Bu, 0x18u}, {0x9Cu, 0x80u}, {0x9Du, 0x14u}, {0x9Eu, 0x80u}, {0xA0u, 0xE2u}, {0xA3u, 0x01u}, {0xAEu, 0x40u}, {0xB4u, 0x08u}, {0xB5u, 0x04u}, {0xB7u, 0x40u}, {0xC0u, 0xFFu}, {0xC2u, 0xBEu}, {0xC4u, 0x7Cu}, {0xCAu, 0xB8u}, {0xCCu, 0xB7u}, {0xCEu, 0xF0u}, {0xD6u, 0x0Fu}, {0xD8u, 0x78u}, {0xECu, 0x02u}, {0x08u, 0x20u}, {0xC2u, 0x02u}, {0x5Eu, 0x80u}, {0x64u, 0x10u}, {0x8Au, 0x40u}, {0x98u, 0x10u}, {0xACu, 0x10u}, {0xB4u, 0x20u}, {0xD6u, 0x04u}, {0xD8u, 0x01u}, {0xE0u, 0x04u}, {0xEAu, 0x02u}, {0x10u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; CYPACKED typedef struct { void CYFAR *dest; const void CYCODE *src; uint16 size; } CYPACKED_ATTR cfg_memcpy_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 128u}, {(void CYFAR *)(CYDEV_UDB_P0_ROUTE_BASE), 768u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; /* UDB_0_1_1_CONFIG Address: CYDEV_UDB_P0_U1_BASE Size (bytes): 128 */ static const uint8 CYCODE BS_UDB_0_1_1_CONFIG_VAL[] = { 0x04u, 0x40u, 0x00u, 0x00u, 0x07u, 0x40u, 0x38u, 0x00u, 0x60u, 0x00u, 0x00u, 0x40u, 0x56u, 0x40u, 0x09u, 0x00u, 0x01u, 0x40u, 0x00u, 0x00u, 0x00u, 0x03u, 0x04u, 0x3Cu, 0x0Au, 0x15u, 0x10u, 0x6Au, 0x04u, 0x00u, 0x00u, 0x00u, 0x04u, 0x79u, 0x00u, 0x06u, 0x04u, 0x00u, 0x00u, 0x00u, 0x04u, 0x10u, 0x00u, 0x60u, 0x00u, 0x02u, 0x00u, 0x0Du, 0x7Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x70u, 0x00u, 0x0Fu, 0x02u, 0x00u, 0x00u, 0xA0u, 0x00u, 0x00u, 0x00u, 0x00u, 0x35u, 0x01u, 0x40u, 0x00u, 0x02u, 0x0Eu, 0xFDu, 0xCBu, 0x3Du, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ {(void CYFAR *)(CYDEV_UDB_P0_U1_BASE), BS_UDB_0_1_1_CONFIG_VAL, 128u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (uint32)(ms->size)); } /* Copy device configuration data into registers */ for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) { const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i]; void * CYDATA destPtr = mc->dest; const void CYCODE * CYDATA srcPtr = mc->src; uint16 CYDATA numBytes = mc->size; CYCONFIGCPYCODE(destPtr, srcPtr, numBytes); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00EE0000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0300EE03u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000099u); /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000030u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00024000u); /* IOPINS0_2 Starting address: CYDEV_PRT2_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00040000u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x00000041u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00186D86u); /* IOPINS0_4 Starting address: CYDEV_PRT4_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x00000002u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000031u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x00000002u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG4), 0x20000000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x30030000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x06u); } /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F3030u, /* Base address: 0x400F3000 Count: 48 */ 0x400F3126u, /* Base address: 0x400F3100 Count: 38 */ 0x400F3244u, /* Base address: 0x400F3200 Count: 68 */ 0x400F333Au, /* Base address: 0x400F3300 Count: 58 */ 0x400F4006u, /* Base address: 0x400F4000 Count: 6 */ 0x400F410Du, /* Base address: 0x400F4100 Count: 13 */ 0x400F4208u, /* Base address: 0x400F4200 Count: 8 */ 0x400F431Fu, /* Base address: 0x400F4300 Count: 31 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x12u, 0x01u}, {0x13u, 0x01u}, {0x22u, 0x02u}, {0x2Cu, 0x01u}, {0x2Fu, 0x01u}, {0x30u, 0x02u}, {0x33u, 0x01u}, {0x34u, 0x01u}, {0x3Eu, 0x10u}, {0x3Fu, 0x04u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, {0x5Fu, 0x01u}, {0x80u, 0x08u}, {0x84u, 0x02u}, {0x86u, 0x04u}, {0x88u, 0x04u}, {0x8Au, 0x02u}, {0x8Bu, 0x01u}, {0x8Cu, 0x04u}, {0x8Eu, 0x02u}, {0x8Fu, 0x04u}, {0x90u, 0x04u}, {0x92u, 0x02u}, {0x97u, 0x02u}, {0x98u, 0x04u}, {0x9Au, 0x02u}, {0x9Bu, 0x04u}, {0x9Cu, 0x04u}, {0x9Eu, 0x02u}, {0xA2u, 0x01u}, {0xA3u, 0x08u}, {0xAAu, 0x08u}, {0xB0u, 0x08u}, {0xB1u, 0x04u}, {0xB2u, 0x01u}, {0xB3u, 0x08u}, {0xB4u, 0x06u}, {0xB5u, 0x01u}, {0xB7u, 0x02u}, {0xBAu, 0x20u}, {0xBEu, 0x01u}, {0xBFu, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDFu, 0x01u}, {0x04u, 0x06u}, {0x05u, 0x20u}, {0x07u, 0x01u}, {0x08u, 0x02u}, {0x0Eu, 0x08u}, {0x0Fu, 0x82u}, {0x10u, 0x02u}, {0x11u, 0x02u}, {0x17u, 0x22u}, {0x18u, 0x08u}, {0x19u, 0x02u}, {0x1Bu, 0x01u}, {0x1Cu, 0x04u}, {0x1Eu, 0x50u}, {0x20u, 0x10u}, {0x26u, 0x04u}, {0x27u, 0x45u}, {0x28u, 0x02u}, {0x2Du, 0x02u}, {0x30u, 0x02u}, {0x36u, 0x04u}, {0x37u, 0x20u}, {0x3Du, 0x40u}, {0x3Eu, 0x10u}, {0x68u, 0x02u}, {0x6Cu, 0x01u}, {0x6Du, 0x40u}, {0x80u, 0x10u}, {0x82u, 0x40u}, {0x8Fu, 0x20u}, {0xC0u, 0xF0u}, {0xC2u, 0xD8u}, {0xC4u, 0x59u}, {0xCAu, 0x88u}, {0xCCu, 0x61u}, {0xCEu, 0x30u}, {0xE0u, 0x04u}, {0xE4u, 0x01u}, {0x00u, 0x04u}, {0x02u, 0x08u}, {0x08u, 0x04u}, {0x09u, 0x02u}, {0x0Au, 0x08u}, {0x0Bu, 0x05u}, {0x0Cu, 0x08u}, {0x0Eu, 0x04u}, {0x0Fu, 0x10u}, {0x13u, 0x08u}, {0x14u, 0x04u}, {0x15u, 0x01u}, {0x16u, 0x08u}, {0x17u, 0x02u}, {0x19u, 0x02u}, {0x1Au, 0x10u}, {0x1Bu, 0x01u}, {0x1Eu, 0x02u}, {0x20u, 0x04u}, {0x22u, 0x08u}, {0x25u, 0x02u}, {0x27u, 0x01u}, {0x28u, 0x04u}, {0x29u, 0x02u}, {0x2Au, 0x09u}, {0x2Bu, 0x01u}, {0x2Du, 0x02u}, {0x2Fu, 0x01u}, {0x30u, 0x01u}, {0x31u, 0x10u}, {0x32u, 0x10u}, {0x33u, 0x04u}, {0x34u, 0x02u}, {0x35u, 0x03u}, {0x36u, 0x0Cu}, {0x37u, 0x08u}, {0x3Au, 0x80u}, {0x3Bu, 0x20u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Fu, 0x01u}, {0x80u, 0x01u}, {0x82u, 0x02u}, {0x84u, 0x02u}, {0x86u, 0x01u}, {0x88u, 0x01u}, {0x8Au, 0x0Au}, {0x8Fu, 0x01u}, {0x96u, 0x04u}, {0x9Cu, 0x01u}, {0x9Eu, 0x12u}, {0xA3u, 0x04u}, {0xA8u, 0x01u}, {0xAAu, 0x02u}, {0xACu, 0x01u}, {0xAEu, 0x02u}, {0xB0u, 0x08u}, {0xB1u, 0x02u}, {0xB2u, 0x10u}, {0xB3u, 0x04u}, {0xB4u, 0x03u}, {0xB6u, 0x04u}, {0xB7u, 0x01u}, {0xBAu, 0x20u}, {0xBFu, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDFu, 0x01u}, {0x01u, 0x02u}, {0x03u, 0x28u}, {0x05u, 0x41u}, {0x07u, 0x04u}, {0x09u, 0x88u}, {0x0Eu, 0x19u}, {0x11u, 0x40u}, {0x13u, 0x10u}, {0x16u, 0x08u}, {0x17u, 0x02u}, {0x19u, 0x82u}, {0x1Au, 0x01u}, {0x1Bu, 0x28u}, {0x1Cu, 0x01u}, {0x1Du, 0x49u}, {0x1Fu, 0x14u}, {0x21u, 0x80u}, {0x22u, 0x02u}, {0x23u, 0x10u}, {0x25u, 0x01u}, {0x26u, 0x04u}, {0x27u, 0x2Au}, {0x29u, 0x02u}, {0x2Du, 0x80u}, {0x2Fu, 0x14u}, {0x35u, 0x01u}, {0x37u, 0x28u}, {0x39u, 0x40u}, {0x3Du, 0x20u}, {0x3Fu, 0x80u}, {0x80u, 0x04u}, {0x81u, 0x50u}, {0x83u, 0x40u}, {0x86u, 0x08u}, {0x87u, 0x08u}, {0x88u, 0x02u}, {0x8Au, 0x02u}, {0x8Bu, 0x20u}, {0x8Cu, 0x05u}, {0x90u, 0x0Cu}, {0x92u, 0x10u}, {0x9Bu, 0x04u}, {0x9Cu, 0x02u}, {0x9Fu, 0x02u}, {0xA5u, 0x01u}, {0xA7u, 0x40u}, {0xA9u, 0x21u}, {0xB7u, 0x40u}, {0xC0u, 0xDEu}, {0xC2u, 0xE5u}, {0xC4u, 0x53u}, {0xCAu, 0x71u}, {0xCCu, 0xE0u}, {0xCEu, 0x38u}, {0xE0u, 0x08u}, {0xE4u, 0x01u}, {0xE6u, 0x20u}, {0xEAu, 0x10u}, {0x50u, 0x06u}, {0x55u, 0x02u}, {0x80u, 0x02u}, {0xD4u, 0xA0u}, {0xD6u, 0x20u}, {0xE2u, 0x20u}, {0x0Au, 0x40u}, {0x0Bu, 0x02u}, {0x0Du, 0x88u}, {0x81u, 0x08u}, {0x82u, 0x40u}, {0x83u, 0x01u}, {0x85u, 0x80u}, {0x89u, 0x02u}, {0xA5u, 0x02u}, {0xB4u, 0x04u}, {0xC2u, 0xF0u}, {0xE0u, 0xA0u}, {0xE4u, 0x60u}, {0x59u, 0x04u}, {0x65u, 0x20u}, {0x81u, 0x20u}, {0x82u, 0x01u}, {0x8Eu, 0x10u}, {0xD6u, 0x02u}, {0xD8u, 0x01u}, {0xE6u, 0x08u}, {0x1Au, 0x10u}, {0x1Cu, 0x08u}, {0x57u, 0x08u}, {0x59u, 0x20u}, {0x66u, 0x81u}, {0x68u, 0x08u}, {0x6Du, 0x08u}, {0x73u, 0x10u}, {0x7Bu, 0x80u}, {0x81u, 0x04u}, {0x83u, 0x08u}, {0x87u, 0x10u}, {0x88u, 0x04u}, {0x8Au, 0x80u}, {0x8Bu, 0x80u}, {0x8Cu, 0x08u}, {0x8Du, 0x04u}, {0x96u, 0x10u}, {0x99u, 0x20u}, {0x9Au, 0x01u}, {0x9Du, 0x04u}, {0xC6u, 0x09u}, {0xD4u, 0x03u}, {0xD6u, 0x01u}, {0xD8u, 0x01u}, {0xDAu, 0x03u}, {0xDCu, 0x01u}, {0xDEu, 0x02u}, {0xE0u, 0x01u}, {0xE2u, 0x04u}, {0xE4u, 0x0Eu}, {0x10u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00000333u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x33000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x3000EE33u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000099u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x00C80000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0xAA000000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG8), 0xC5000000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0xC1090000u); /* TCPWM_CNT1 Starting address: CYDEV_TCPWM_CNT1_TR_CTRL0 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT1_TR_CTRL0), 0x00060030u); /* TCPWM_CNT2 Starting address: CYDEV_TCPWM_CNT2_TR_CTRL0 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT2_TR_CTRL0), 0x00020080u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_PRT0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT0_BASE), 0x0000000Fu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x000001B6u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC2), 0x00000008u); /* IOPINS0_1 Starting address: CYDEV_PRT1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT1_BASE), 0x000000F6u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00492000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC2), 0x00000006u); /* IOPINS0_2 Starting address: CYDEV_PRT2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT2_BASE), 0x000000D0u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00DB6000u); /* IOPINS0_3 Starting address: CYDEV_PRT3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT3_BASE), 0x000000B3u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00DB0DB6u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC2), 0x00000010u); /* IOPINS0_4 Starting address: CYDEV_PRT4_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT4_BASE), 0x00000002u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000031u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x00000002u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: CyBLE_Nvram_Write ******************************************************************************** * * Summary: * This API writes the data to the NVRAM store. It will check the appropriate * alignment of a start address and also perform an address range check based * on the length before performing the write operation. * * Parameters: * const uint8 *buffer: Pointer to the buffer containing the data to be stored. * const uint8 *varFlash: Pointer to the array or variable in the flash. * uint16 length: the length of the data in bytes. * * Return: * CYRET_SUCCESS a successful write * CYRET_BAD_PARAM A request to write outside the flash boundary. * CYRET_UNKNOWN Other errors in writing the flash * * Side Effects: * This API will automatically modify the clock settings for the device. * Writing to flash requires changes to be done to the IMO (set to 48 MHz) * and HFCLK (source set to IMO) settings. The configuration is restored before * returning. This will impact the operation of most of the hardware in the * device. * *******************************************************************************/ cystatus CyBLE_Nvram_Write (const uint8 buffer[], const uint8 varFlash[], uint16 length) { uint8 writeBuffer[CY_FLASH_SIZEOF_ROW]; uint32 rowId; uint32 dstIndex; uint32 srcIndex = 0u; cystatus rc = CYRET_SUCCESS; uint32 eeOffset; uint32 byteOffset; uint32 rowsNotEqual; eeOffset = (uint32)varFlash; /* Make sure, that varFlash[] points to ROM */ if ((eeOffset + length) < CYBLE_HAL_FLASH_END_ADDR) { rowId = eeOffset / CY_FLASH_SIZEOF_ROW; byteOffset = CY_FLASH_SIZEOF_ROW * rowId; while ((srcIndex < length) && (CYRET_SUCCESS == rc)) { rowsNotEqual = 0u; /* Copy data to the write buffer either from the source buffer or from the flash */ for (dstIndex = 0u; dstIndex < CY_FLASH_SIZEOF_ROW; dstIndex++) { if ((byteOffset >= eeOffset) && (srcIndex < length)) { /* Detect that row programming is required */ if(writeBuffer[dstIndex] != buffer[srcIndex]) { writeBuffer[dstIndex] = buffer[srcIndex]; rowsNotEqual = 1u; } srcIndex++; } else { writeBuffer[dstIndex] = CY_GET_XTND_REG8(CYDEV_FLASH_BASE + byteOffset); } byteOffset++; } if(rowsNotEqual != 0u) { /* Write flash row */ rc = CySysFlashWriteRow(rowId, writeBuffer); } /* Go to the next row */ rowId++; } } else { rc = CYRET_BAD_PARAM; } /* Mask return codes from flash, if they are not supported */ if ((CYRET_SUCCESS != rc) && (CYRET_BAD_PARAM != rc)) { rc = CYRET_UNKNOWN; } return (rc); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_LL_DSM_CTRL), 0x00000000u); /* Enable the clock in the interrupt controller for the routed interrupts */ CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u); { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F4104u, /* Base address: 0x400F4100 Count: 4 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x2Fu, 0x08u}, {0x6Fu, 0x08u}, {0xCAu, 0x20u}, {0xDAu, 0x80u}, {0x02u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0xEE000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00990000u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG4), 0x80000000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); /* INT_SELECT Starting address: CYDEV_CPUSS_INT_SEL */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INT_SEL), 0x00000002u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00D80000u); /* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000020u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x00031000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC2), 0x00000020u); /* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT2_BASE), 0x000000C0u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00580000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_INTR_CFG), 0x00008000u); /* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x00000047u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00180000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC2), 0x00000007u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_LL_DSM_CTRL), 0x00000000u); { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F0001u, /* Base address: 0x400F0000 Count: 1 */ 0x400F322Eu, /* Base address: 0x400F3200 Count: 46 */ 0x400F3323u, /* Base address: 0x400F3300 Count: 35 */ 0x400F4107u, /* Base address: 0x400F4100 Count: 7 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x82u, 0x0Fu}, {0x03u, 0x03u}, {0x07u, 0x0Cu}, {0x0Au, 0x08u}, {0x11u, 0x02u}, {0x16u, 0x0Du}, {0x19u, 0x08u}, {0x1Eu, 0x04u}, {0x22u, 0x01u}, {0x2Eu, 0x02u}, {0x30u, 0x04u}, {0x31u, 0x02u}, {0x32u, 0x02u}, {0x33u, 0x08u}, {0x34u, 0x01u}, {0x35u, 0x04u}, {0x36u, 0x08u}, {0x37u, 0x01u}, {0x3Eu, 0x10u}, {0x40u, 0x30u}, {0x41u, 0x05u}, {0x45u, 0xD0u}, {0x46u, 0x02u}, {0x47u, 0x15u}, {0x48u, 0x36u}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, {0x4Bu, 0xFFu}, {0x4Du, 0xA0u}, {0x4Fu, 0x04u}, {0x50u, 0x18u}, {0x52u, 0x80u}, {0x54u, 0x07u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Au, 0x04u}, {0x5Bu, 0x04u}, {0x5Fu, 0x01u}, {0x60u, 0x40u}, {0x62u, 0xC0u}, {0x64u, 0x40u}, {0x65u, 0x40u}, {0x66u, 0xC0u}, {0x68u, 0xC0u}, {0x6Au, 0xC0u}, {0x6Cu, 0xC0u}, {0x6Eu, 0xC0u}, {0x06u, 0x04u}, {0x0Du, 0x08u}, {0x0Fu, 0x02u}, {0x16u, 0x80u}, {0x17u, 0x40u}, {0x1Du, 0x08u}, {0x1Eu, 0x08u}, {0x1Fu, 0x81u}, {0x24u, 0x40u}, {0x26u, 0x20u}, {0x27u, 0x22u}, {0x36u, 0x20u}, {0x37u, 0x02u}, {0x3Du, 0x08u}, {0x3Fu, 0x02u}, {0x45u, 0x08u}, {0x4Fu, 0x81u}, {0x55u, 0x04u}, {0x56u, 0x84u}, {0x57u, 0x41u}, {0x5Cu, 0x40u}, {0x5Eu, 0x08u}, {0x5Fu, 0x21u}, {0x77u, 0x40u}, {0x83u, 0x80u}, {0x8Fu, 0x01u}, {0xC0u, 0x40u}, {0xC2u, 0xA0u}, {0xC4u, 0x90u}, {0xCCu, 0xA0u}, {0xCEu, 0xC0u}, {0xD0u, 0x40u}, {0xD2u, 0x10u}, {0xD6u, 0xF0u}, {0xE2u, 0x40u}, {0x59u, 0x10u}, {0x63u, 0x08u}, {0x81u, 0x10u}, {0x8Fu, 0x04u}, {0xD4u, 0x80u}, {0xD8u, 0x40u}, {0xE6u, 0x20u}, {0x10u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x03990300u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x00EE0000u); /* FORCED_HSIOM Starting address: CYDEV_HSIOM_PORT_SEL0 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL0), 0x00000000u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x20200000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG4), 0xA0A00000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00C36DB6u); /* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000064u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x00DB1DB6u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC2), 0x00000020u); /* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00C30000u); /* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x00000030u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00264240u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F0001u, /* Base address: 0x400F0000 Count: 1 */ 0x400F325Eu, /* Base address: 0x400F3200 Count: 94 */ 0x400F3338u, /* Base address: 0x400F3300 Count: 56 */ 0x400F4103u, /* Base address: 0x400F4100 Count: 3 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x83u, 0x0Fu}, {0x02u, 0x06u}, {0x03u, 0x08u}, {0x05u, 0x03u}, {0x07u, 0x44u}, {0x0Eu, 0x03u}, {0x0Fu, 0x55u}, {0x12u, 0x01u}, {0x19u, 0x73u}, {0x1Au, 0x02u}, {0x1Bu, 0x0Cu}, {0x1Cu, 0x06u}, {0x1Eu, 0x01u}, {0x21u, 0x73u}, {0x23u, 0x04u}, {0x2Au, 0x05u}, {0x2Du, 0x2Au}, {0x2Fu, 0x44u}, {0x31u, 0x30u}, {0x33u, 0x0Fu}, {0x36u, 0x07u}, {0x37u, 0x40u}, {0x39u, 0x02u}, {0x3Au, 0x80u}, {0x3Bu, 0x08u}, {0x3Fu, 0x41u}, {0x40u, 0x01u}, {0x46u, 0x40u}, {0x49u, 0xFFu}, {0x4Au, 0x07u}, {0x4Bu, 0xFFu}, {0x4Cu, 0x40u}, {0x4Du, 0x20u}, {0x4Eu, 0xF0u}, {0x4Fu, 0x05u}, {0x50u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Au, 0x04u}, {0x5Fu, 0x01u}, {0x60u, 0x40u}, {0x61u, 0xA8u}, {0x62u, 0x40u}, {0x63u, 0x20u}, {0x80u, 0x41u}, {0x81u, 0x09u}, {0x82u, 0x0Eu}, {0x83u, 0x10u}, {0x85u, 0x14u}, {0x89u, 0x10u}, {0x8Eu, 0x0Cu}, {0x90u, 0x20u}, {0x93u, 0x03u}, {0x94u, 0x41u}, {0x95u, 0x10u}, {0x96u, 0x06u}, {0x97u, 0x0Cu}, {0x9Cu, 0x80u}, {0x9Du, 0x1Cu}, {0x9Eu, 0x03u}, {0x9Fu, 0x02u}, {0xA1u, 0x0Cu}, {0xA3u, 0x11u}, {0xA6u, 0x08u}, {0xA8u, 0x0Cu}, {0xAAu, 0x43u}, {0xACu, 0x10u}, {0xB0u, 0x0Fu}, {0xB1u, 0x1Fu}, {0xB2u, 0x10u}, {0xB4u, 0x20u}, {0xB6u, 0xC0u}, {0xB8u, 0x80u}, {0xBAu, 0x02u}, {0xBEu, 0x14u}, {0xC0u, 0x34u}, {0xC1u, 0x01u}, {0xC5u, 0xECu}, {0xC7u, 0x0Bu}, {0xC8u, 0x13u}, {0xC9u, 0xFFu}, {0xCAu, 0xFFu}, {0xCBu, 0xFFu}, {0xCEu, 0xF0u}, {0xCFu, 0x44u}, {0xD0u, 0x0Cu}, {0xD4u, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDAu, 0x04u}, {0xDBu, 0x04u}, {0xDFu, 0x01u}, {0xE6u, 0xC0u}, {0xEAu, 0x40u}, {0xEBu, 0x02u}, {0x01u, 0x80u}, {0x03u, 0x80u}, {0x04u, 0x01u}, {0x05u, 0x40u}, {0x09u, 0x4Au}, {0x0Cu, 0x20u}, {0x0Fu, 0x82u}, {0x10u, 0x21u}, {0x12u, 0x08u}, {0x17u, 0x20u}, {0x18u, 0x01u}, {0x19u, 0x84u}, {0x1Au, 0xC0u}, {0x1Bu, 0x21u}, {0x1Du, 0x40u}, {0x1Fu, 0x80u}, {0x21u, 0x02u}, {0x25u, 0x08u}, {0x27u, 0xA1u}, {0x2Bu, 0x80u}, {0x2Eu, 0x40u}, {0x2Fu, 0x80u}, {0x31u, 0x0Au}, {0x32u, 0x40u}, {0x37u, 0x20u}, {0x38u, 0x09u}, {0x3Au, 0x10u}, {0x3Cu, 0x01u}, {0x3Fu, 0x84u}, {0x41u, 0x08u}, {0x42u, 0x80u}, {0x43u, 0x80u}, {0x44u, 0x40u}, {0x47u, 0x81u}, {0x49u, 0x01u}, {0x4Bu, 0x04u}, {0x50u, 0x04u}, {0x54u, 0x20u}, {0x55u, 0x40u}, {0x56u, 0x90u}, {0x57u, 0x40u}, {0x58u, 0x41u}, {0x59u, 0x25u}, {0x65u, 0x20u}, {0x67u, 0x04u}, {0x8Eu, 0x48u}, {0x8Fu, 0x20u}, {0xC0u, 0x99u}, {0xC2u, 0xDDu}, {0xC4u, 0x47u}, {0xCAu, 0x91u}, {0xCCu, 0x2Bu}, {0xCEu, 0xD7u}, {0xD0u, 0x1Bu}, {0xD6u, 0x0Fu}, {0xE2u, 0x40u}, {0x63u, 0x08u}, {0x8Fu, 0x04u}, {0xD8u, 0x40u}, {0x01u, 0x01u}, {0x10u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x30000000u); /* FORCED_HSIOM Starting address: CYDEV_HSIOM_PORT_SEL3 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x00000000u); /* IOPINS0_3 Starting address: CYDEV_PRT3_PC */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x80000000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_1 Starting address: CYDEV_PRT1_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000080u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00C00000u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; { CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (uint32)(ms->size)); } /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00000006u); /* IOPINS0_2 Starting address: CYDEV_PRT2_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_DR), 0x00000020u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00000006u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC2), 0x00000020u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x06u); } /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
void cyfitter_cfg(void) { #ifdef CYGlobalIntDisable /* Disable interrupts by default. Let user enable if/when they want. */ CYGlobalIntDisable #endif /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x00u : 0x01u)); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Set Flash Cycles based on newly configured 24.00MHz Bus Clock. */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x80u : 0x81u)); /* Disable DMA channels so they can be configured for chip initialization */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_PHUB_CH0_BASIC_CFG), 0x00u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_PHUB_CH1_BASIC_CFG), 0x00u); /* Enable analog pulldown switches */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_ANAIF_CFG_MISC_CR0), 0x01u); /* Enable/Disable Debug functionality based on settings from System DWR */ CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DBG_DBE, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DBG_DBE) | 0x01u)); { typedef struct { void CYFAR *address; uint16 size; } CYPACKED cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYREG_I2C_XCFG), 20u}, {(void CYFAR *)(CYREG_PRT0_DR), 16u}, {(void CYFAR *)(CYREG_PRT4_DR), 48u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT0_BASE), 7u); CYCONFIGCPY8((void CYFAR *)(CYDEV_PRTDSI_PRT1_BASE), (const void CYFAR *)(BS_IOPORT_1_VAL), 7u); CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT2_BASE), 7u); CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT3_BASE), 7u); CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT4_BASE), 7u); CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT5_BASE), 7u); CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT6_BASE), 7u); CYCONFIGCPY8((void CYFAR *)(CYDEV_PRTDSI_PRT12_BASE), (const void CYFAR *)(BS_IOPORT_7_VAL), 6u); CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT15_BASE), 7u); /* Enable digital routing */ CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u); CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u); CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ CYCONFIGCPY8((void CYFAR *)(CYREG_PRT12_DR), (const void CYFAR *)(BS_IOPINS0_7_VAL), 10u); CYCONFIGCPY((void CYFAR *)(CYREG_PRT15_DR), (const void CYFAR *)(BS_IOPINS0_8_VAL), 10u); CYCONFIGCPY((void CYFAR *)(CYREG_PRT1_DR), (const void CYFAR *)(BS_IOPINS0_1_VAL), 10u); CYCONFIGCPY((void CYFAR *)(CYREG_PRT2_DR), (const void CYFAR *)(BS_IOPINS0_2_VAL), 10u); CYCONFIGCPY((void CYFAR *)(CYREG_PRT3_DR), (const void CYFAR *)(BS_IOPINS0_3_VAL), 10u); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); /* Configure alternate active mode */ CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 12u); CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_STBY_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_STBY_CFG0) & (uint8)~0x02u); /* Disable CPU */ }
/******************************************************************************* * Function Name: CySpcLoadRowFull ****************************************************************************//** * Loads a row of data into the row latch of a Flash/EEPROM array. * * The only data that are going to be changed should be passed. The function * will handle unmodified data preservation based on DWR settings and input * parameters. * * \param uint8 array: * Id of the array. * * \param uint16 row: * Flash row number to be loaded. * * \param uint8* buffer: * Data to be loaded to the row latch * * \param uint8 size: * The number of data bytes that the SPC expects to be written. Depends on the * type of the array and, if the array is Flash, whether ECC is being enabled * or not. There are following values: flash row latch size with ECC enabled, * flash row latch size with ECC disabled and EEPROM row latch size. * * \return * CYRET_STARTED * CYRET_CANCELED * CYRET_LOCKED * *******************************************************************************/ cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\ { cystatus status = CYRET_STARTED; uint16 i; #if (CYDEV_ECC_ENABLE == 0) uint32 offset; #endif /* (CYDEV_ECC_ENABLE == 0) */ /* Make sure the SPC is ready to accept command */ if(CY_SPC_IDLE) { CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW); CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW; /* Make sure the command was accepted */ if(CY_SPC_BUSY) { CY_SPC_CPU_DATA_REG = array; /******************************************************************* * If "Enable Error Correcting Code (ECC)" and "Store Configuration * Data in ECC" DWR options are disabled, ECC section is available * for user data. *******************************************************************/ #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) /******************************************************************* * If size parameter equals size of the ECC row and selected array * identification corresponds to the flash array (but not to EEPROM * array) then data are going to be written to the ECC section. * In this case flash data must be preserved. The flash data copied * from flash data section to the SPC data register. *******************************************************************/ if ((size == CYDEV_ECC_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID)) { offset = CYDEV_FLS_BASE + ((uint32) array * CYDEV_FLS_SECTOR_SIZE) + ((uint32) row * CYDEV_FLS_ROW_SIZE ); for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++) { CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); } } #endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ for(i = 0u; i < size; i++) { CY_SPC_CPU_DATA_REG = buffer[i]; } /******************************************************************* * If "Enable Error Correcting Code (ECC)" DWR option is disabled, * ECC section can be used for storing device configuration data * ("Store Configuration Data in ECC" DWR option is enabled) or for * storing user data in the ECC section ("Store Configuration Data in * ECC" DWR option is enabled). In both cases, the data in the ECC * section must be preserved if flash data is written. *******************************************************************/ #if (CYDEV_ECC_ENABLE == 0) /******************************************************************* * If size parameter equals size of the flash row and selected array * identification corresponds to the flash array (but not to EEPROM * array) then data are going to be written to the flash data * section. In this case, ECC section data must be preserved. * The ECC section data copied from ECC section to the SPC data * register. *******************************************************************/ if ((size == CYDEV_FLS_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID)) { offset = CYDEV_ECC_BASE + ((uint32) array * CYDEV_ECC_SECTOR_SIZE) + ((uint32) row * CYDEV_ECC_ROW_SIZE ); for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++) { CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); } } #else if(0u != row) { /* To remove unreferenced local variable warning */ } #endif /* (CYDEV_ECC_ENABLE == 0) */ } else { status = CYRET_CANCELED; } } else { status = CYRET_LOCKED; } return(status); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; /* Enable the clock in the interrupt controller for the routed interrupts */ CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u); { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F0001u, /* Base address: 0x400F0000 Count: 1 */ 0x400F3232u, /* Base address: 0x400F3200 Count: 50 */ 0x400F3323u, /* Base address: 0x400F3300 Count: 35 */ 0x400F4006u, /* Base address: 0x400F4000 Count: 6 */ 0x400F410Du, /* Base address: 0x400F4100 Count: 13 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x82u, 0x0Fu}, {0x0Au, 0x04u}, {0x0Bu, 0x0Eu}, {0x0Cu, 0x01u}, {0x1Au, 0x07u}, {0x1Du, 0x08u}, {0x27u, 0x03u}, {0x2Eu, 0x08u}, {0x2Fu, 0x01u}, {0x30u, 0x02u}, {0x31u, 0x08u}, {0x32u, 0x01u}, {0x33u, 0x02u}, {0x34u, 0x08u}, {0x35u, 0x01u}, {0x36u, 0x04u}, {0x37u, 0x04u}, {0x3Fu, 0x10u}, {0x40u, 0x20u}, {0x41u, 0x05u}, {0x45u, 0xD5u}, {0x46u, 0x12u}, {0x48u, 0x0Fu}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, {0x4Bu, 0xFFu}, {0x4Du, 0xA0u}, {0x4Fu, 0x04u}, {0x50u, 0x18u}, {0x52u, 0x80u}, {0x54u, 0x07u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Au, 0x04u}, {0x5Bu, 0x04u}, {0x5Cu, 0x99u}, {0x5Du, 0x99u}, {0x5Fu, 0x01u}, {0x60u, 0x40u}, {0x62u, 0xC0u}, {0x64u, 0x40u}, {0x65u, 0x40u}, {0x66u, 0xC0u}, {0x68u, 0xC0u}, {0x6Au, 0xC0u}, {0x6Cu, 0xC0u}, {0x6Eu, 0xC0u}, {0xB0u, 0x01u}, {0xBEu, 0x01u}, {0xD8u, 0x04u}, {0xDFu, 0x01u}, {0x04u, 0x40u}, {0x05u, 0x10u}, {0x0Fu, 0x08u}, {0x17u, 0x40u}, {0x1Bu, 0x01u}, {0x1Cu, 0x40u}, {0x1Du, 0x70u}, {0x1Eu, 0x20u}, {0x1Fu, 0x20u}, {0x26u, 0x80u}, {0x27u, 0xA8u}, {0x2Eu, 0x80u}, {0x2Fu, 0x20u}, {0x36u, 0x80u}, {0x3Fu, 0x20u}, {0x45u, 0x20u}, {0x4Fu, 0x89u}, {0x56u, 0x80u}, {0x57u, 0x50u}, {0x5Eu, 0x20u}, {0x5Fu, 0x89u}, {0x77u, 0x40u}, {0x83u, 0x20u}, {0x85u, 0x40u}, {0x8Bu, 0x01u}, {0xC0u, 0xC0u}, {0xC2u, 0x40u}, {0xC4u, 0x80u}, {0xCAu, 0x50u}, {0xCCu, 0x10u}, {0xCEu, 0x20u}, {0xD0u, 0x20u}, {0xD2u, 0x10u}, {0xD6u, 0xF0u}, {0xE2u, 0x80u}, {0x41u, 0x20u}, {0x43u, 0x20u}, {0x57u, 0x80u}, {0x6Fu, 0x20u}, {0xD4u, 0x40u}, {0xDAu, 0x80u}, {0x21u, 0x20u}, {0x5Cu, 0x01u}, {0x64u, 0x08u}, {0x80u, 0x01u}, {0x84u, 0x08u}, {0x8Bu, 0x80u}, {0xA5u, 0x20u}, {0xA7u, 0x80u}, {0xC8u, 0x10u}, {0xD6u, 0x80u}, {0xD8u, 0x80u}, {0xE2u, 0x80u}, {0xE6u, 0x10u}, {0x02u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x30030000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x000000EEu); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x00010000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x43000000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG4), 0x00020000u); /* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x00000001u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_PRT0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT0_BASE), 0x00000021u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00031000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC2), 0x00000021u); /* IOPINS0_1 Starting address: CYDEV_PRT1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT1_BASE), 0x00000090u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00C06000u); /* IOPINS0_2 Starting address: CYDEV_PRT2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT2_BASE), 0x00000080u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x001B6DB6u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC2), 0x00000080u); /* IOPINS0_3 Starting address: CYDEV_PRT3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT3_BASE), 0x00000001u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x001B0D82u); /* IOPINS0_4 Starting address: CYDEV_PRT4_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT4_BASE), 0x00000003u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x02000024u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; /* Enable the clock in the interrupt controller for the routed interrupts */ CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u); { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F0001u, /* Base address: 0x400F0000 Count: 1 */ 0x400F3032u, /* Base address: 0x400F3000 Count: 50 */ 0x400F3117u, /* Base address: 0x400F3100 Count: 23 */ 0x400F3233u, /* Base address: 0x400F3200 Count: 51 */ 0x400F331Au, /* Base address: 0x400F3300 Count: 26 */ 0x400F4010u, /* Base address: 0x400F4000 Count: 16 */ 0x400F410Cu, /* Base address: 0x400F4100 Count: 12 */ 0x400F4208u, /* Base address: 0x400F4200 Count: 8 */ 0x400F4308u, /* Base address: 0x400F4300 Count: 8 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x83u, 0x0Du}, {0x40u, 0x24u}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, {0x4Bu, 0xFFu}, {0x4Fu, 0x01u}, {0x50u, 0x18u}, {0x5Au, 0x04u}, {0x5Bu, 0x04u}, {0x5Du, 0x09u}, {0x5Fu, 0x01u}, {0x60u, 0x40u}, {0x62u, 0x40u}, {0x64u, 0x40u}, {0x65u, 0x40u}, {0x66u, 0x80u}, {0x68u, 0x80u}, {0x6Au, 0x80u}, {0x6Cu, 0x80u}, {0x6Eu, 0x80u}, {0x82u, 0x02u}, {0x8Eu, 0x08u}, {0x98u, 0x02u}, {0x9Au, 0x04u}, {0x9Cu, 0x01u}, {0xB0u, 0x04u}, {0xB2u, 0x02u}, {0xB4u, 0x08u}, {0xB6u, 0x01u}, {0xBEu, 0x40u}, {0xC0u, 0x25u}, {0xC9u, 0xFFu}, {0xCAu, 0xFFu}, {0xCBu, 0xFFu}, {0xCDu, 0x83u}, {0xCEu, 0x03u}, {0xCFu, 0x01u}, {0xD0u, 0x18u}, {0xD8u, 0x04u}, {0xDAu, 0x04u}, {0xDDu, 0x09u}, {0xDFu, 0x01u}, {0xE0u, 0x40u}, {0xE2u, 0x40u}, {0xE4u, 0x40u}, {0xE5u, 0x40u}, {0xE6u, 0x80u}, {0xE8u, 0x80u}, {0xEAu, 0x80u}, {0xECu, 0x80u}, {0xEEu, 0x80u}, {0x05u, 0x01u}, {0x07u, 0x02u}, {0x0Eu, 0x04u}, {0x0Fu, 0x01u}, {0x1Du, 0x01u}, {0x1Eu, 0x04u}, {0x1Fu, 0x88u}, {0x41u, 0x01u}, {0x42u, 0x08u}, {0x46u, 0x08u}, {0x4Eu, 0x02u}, {0x69u, 0x80u}, {0x6Au, 0x20u}, {0x6Bu, 0x90u}, {0x70u, 0x90u}, {0x81u, 0x40u}, {0x83u, 0x18u}, {0x8Cu, 0x10u}, {0x8Eu, 0x10u}, {0xC0u, 0x90u}, {0xC2u, 0xC0u}, {0xD0u, 0x25u}, {0xD2u, 0x10u}, {0x40u, 0x24u}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, {0x4Bu, 0xFFu}, {0x4Du, 0x83u}, {0x4Eu, 0x03u}, {0x4Fu, 0x01u}, {0x50u, 0x18u}, {0x5Au, 0x04u}, {0x5Du, 0x09u}, {0x5Fu, 0x01u}, {0x60u, 0x40u}, {0x62u, 0x40u}, {0x64u, 0x40u}, {0x65u, 0x40u}, {0x66u, 0x80u}, {0x68u, 0x80u}, {0x6Au, 0x80u}, {0x6Cu, 0x80u}, {0x6Eu, 0x80u}, {0x87u, 0x01u}, {0x93u, 0x01u}, {0xB7u, 0x01u}, {0xBFu, 0x40u}, {0xC0u, 0x24u}, {0xC5u, 0xECu}, {0xC7u, 0x20u}, {0xC8u, 0x23u}, {0xC9u, 0xFFu}, {0xCAu, 0xFFu}, {0xCBu, 0xFFu}, {0xCDu, 0x83u}, {0xCEu, 0x03u}, {0xCFu, 0x01u}, {0xD0u, 0x18u}, {0xD4u, 0x01u}, {0xD6u, 0x04u}, {0xD9u, 0x04u}, {0xDAu, 0x04u}, {0xDBu, 0x04u}, {0xDDu, 0x99u}, {0xDFu, 0x01u}, {0xE0u, 0x40u}, {0xE2u, 0x40u}, {0xE4u, 0x40u}, {0xE5u, 0x40u}, {0xE6u, 0x80u}, {0xE8u, 0x80u}, {0xEAu, 0x80u}, {0xECu, 0x80u}, {0xEEu, 0x80u}, {0x22u, 0x40u}, {0x31u, 0x02u}, {0x3Au, 0x08u}, {0x41u, 0x01u}, {0x42u, 0x08u}, {0x45u, 0x02u}, {0x46u, 0x08u}, {0x49u, 0x05u}, {0x51u, 0x03u}, {0x52u, 0x02u}, {0x59u, 0x05u}, {0x5Au, 0x80u}, {0x63u, 0x80u}, {0x83u, 0x40u}, {0x95u, 0x02u}, {0x9Au, 0x08u}, {0xA6u, 0x02u}, {0xABu, 0x83u}, {0xAEu, 0x08u}, {0xB3u, 0x80u}, {0xB4u, 0x80u}, {0xCCu, 0x01u}, {0xCEu, 0x02u}, {0xD0u, 0xA5u}, {0xD6u, 0x0Bu}, {0xD8u, 0x01u}, {0x03u, 0x08u}, {0x07u, 0x80u}, {0x0Eu, 0x02u}, {0x5Bu, 0x20u}, {0x6Cu, 0x80u}, {0x6Fu, 0x20u}, {0x73u, 0x02u}, {0x82u, 0x01u}, {0x83u, 0x22u}, {0xC0u, 0x60u}, {0xC2u, 0x80u}, {0xD4u, 0x80u}, {0xDAu, 0x80u}, {0xDCu, 0x60u}, {0xE2u, 0xA0u}, {0xE6u, 0x80u}, {0x56u, 0x01u}, {0x80u, 0x80u}, {0x9Au, 0x01u}, {0xA4u, 0x80u}, {0xAAu, 0x01u}, {0xABu, 0xA0u}, {0xAFu, 0x08u}, {0xD6u, 0x20u}, {0xE2u, 0x20u}, {0xE8u, 0x80u}, {0xECu, 0xC0u}, {0xEEu, 0x20u}, {0x5Bu, 0x01u}, {0x60u, 0x04u}, {0x8Cu, 0x04u}, {0x8Eu, 0x80u}, {0xD6u, 0x02u}, {0xD8u, 0x02u}, {0xE0u, 0x02u}, {0xE4u, 0x02u}, {0x5Fu, 0x08u}, {0x62u, 0x80u}, {0x9Bu, 0x08u}, {0xA2u, 0x80u}, {0xB3u, 0x01u}, {0xB7u, 0x08u}, {0xD6u, 0x03u}, {0xECu, 0x06u}, {0x10u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00000003u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00000003u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x33000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0330EE00u); /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000083u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x0040004Eu); /* IOPINS0_1 Starting address: CYDEV_PRT1_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000019u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00000036u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC2), 0x00000038u); /* IOPINS0_2 Starting address: CYDEV_PRT2_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_DR), 0x000000C1u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00D80000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC2), 0x00000001u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x00000060u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x001B0D80u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x80280000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x00020000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x00030000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG8), 0x20000000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x10000000u); /* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x0000000Du); /* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x0000000Eu); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F0003u, /* Base address: 0x400F0000 Count: 3 */ 0x400F3011u, /* Base address: 0x400F3000 Count: 17 */ 0x400F3136u, /* Base address: 0x400F3100 Count: 54 */ 0x400F326Bu, /* Base address: 0x400F3200 Count: 107 */ 0x400F3347u, /* Base address: 0x400F3300 Count: 71 */ 0x400F4004u, /* Base address: 0x400F4000 Count: 4 */ 0x400F4103u, /* Base address: 0x400F4100 Count: 3 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x80u, 0x72u}, {0x81u, 0x38u}, {0x83u, 0x0Fu}, {0x82u, 0x01u}, {0x8Eu, 0x04u}, {0x90u, 0x08u}, {0x9Au, 0x02u}, {0x9Eu, 0x01u}, {0xA6u, 0x02u}, {0xB0u, 0x01u}, {0xB2u, 0x02u}, {0xB4u, 0x04u}, {0xB6u, 0x08u}, {0xBBu, 0x02u}, {0xBEu, 0x45u}, {0xD4u, 0x18u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDFu, 0x01u}, {0x02u, 0x01u}, {0x03u, 0x68u}, {0x04u, 0x02u}, {0x06u, 0x01u}, {0x08u, 0x80u}, {0x09u, 0x01u}, {0x0Au, 0x24u}, {0x0Du, 0x22u}, {0x0Eu, 0x01u}, {0x10u, 0x80u}, {0x13u, 0x60u}, {0x15u, 0x08u}, {0x19u, 0xA2u}, {0x1Au, 0x01u}, {0x1Bu, 0x08u}, {0x1Du, 0x10u}, {0x1Eu, 0x02u}, {0x1Fu, 0x05u}, {0x21u, 0x04u}, {0x23u, 0x48u}, {0x27u, 0x40u}, {0x29u, 0x24u}, {0x2Au, 0x01u}, {0x31u, 0x10u}, {0x33u, 0x4Au}, {0x38u, 0x20u}, {0x3Au, 0x02u}, {0x3Bu, 0x40u}, {0x40u, 0xD1u}, {0x43u, 0x02u}, {0x49u, 0xA0u}, {0x50u, 0x01u}, {0x51u, 0x20u}, {0x5Bu, 0x08u}, {0x5Du, 0x02u}, {0x67u, 0x0Au}, {0x69u, 0x14u}, {0x6Au, 0x80u}, {0x70u, 0x90u}, {0x71u, 0x04u}, {0x72u, 0x06u}, {0x73u, 0x20u}, {0x80u, 0x10u}, {0x83u, 0x40u}, {0xC0u, 0x9Fu}, {0xC2u, 0xDFu}, {0xC4u, 0x2Bu}, {0xCAu, 0x07u}, {0xCCu, 0x0Fu}, {0xCEu, 0x0Du}, {0xD0u, 0x0Bu}, {0xD2u, 0x0Cu}, {0xD6u, 0x82u}, {0xD8u, 0x30u}, {0x00u, 0x10u}, {0x01u, 0x80u}, {0x02u, 0xACu}, {0x03u, 0x13u}, {0x04u, 0x14u}, {0x08u, 0xDCu}, {0x0Au, 0x22u}, {0x0Bu, 0x08u}, {0x12u, 0x03u}, {0x13u, 0x0Cu}, {0x14u, 0x0Cu}, {0x15u, 0x2Cu}, {0x16u, 0x71u}, {0x17u, 0x43u}, {0x1Eu, 0x20u}, {0x20u, 0x09u}, {0x22u, 0xD0u}, {0x24u, 0x10u}, {0x26u, 0x40u}, {0x29u, 0x71u}, {0x2Bu, 0x0Eu}, {0x2Du, 0x71u}, {0x2Fu, 0x06u}, {0x30u, 0x1Fu}, {0x32u, 0xE0u}, {0x33u, 0x30u}, {0x35u, 0x0Fu}, {0x37u, 0xC0u}, {0x39u, 0x88u}, {0x3Au, 0x08u}, {0x3Bu, 0x20u}, {0x3Fu, 0x04u}, {0x40u, 0x02u}, {0x46u, 0x40u}, {0x49u, 0xFFu}, {0x4Au, 0x07u}, {0x4Bu, 0xFFu}, {0x4Cu, 0x40u}, {0x4Du, 0x20u}, {0x4Eu, 0xF0u}, {0x4Fu, 0x05u}, {0x50u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Au, 0x04u}, {0x5Fu, 0x01u}, {0x60u, 0x40u}, {0x61u, 0xA8u}, {0x62u, 0x40u}, {0x63u, 0x20u}, {0x81u, 0x01u}, {0x82u, 0x08u}, {0x83u, 0x0Au}, {0x84u, 0x0Au}, {0x85u, 0x02u}, {0x86u, 0x14u}, {0x87u, 0x09u}, {0x88u, 0x20u}, {0x89u, 0x13u}, {0x8Au, 0xC0u}, {0x8Eu, 0x15u}, {0x90u, 0x13u}, {0x92u, 0x0Cu}, {0x94u, 0x80u}, {0x96u, 0x20u}, {0x98u, 0x13u}, {0x9Au, 0x04u}, {0x9Du, 0x10u}, {0xA0u, 0x03u}, {0xA1u, 0x20u}, {0xA2u, 0x14u}, {0xA4u, 0xE0u}, {0xA5u, 0x13u}, {0xA8u, 0xE0u}, {0xABu, 0x04u}, {0xACu, 0x40u}, {0xAEu, 0x20u}, {0xB0u, 0x0Fu}, {0xB1u, 0x10u}, {0xB3u, 0x20u}, {0xB4u, 0xE0u}, {0xB5u, 0x03u}, {0xB6u, 0x10u}, {0xB7u, 0x0Cu}, {0xBAu, 0x02u}, {0xBEu, 0x40u}, {0xBFu, 0x44u}, {0xC0u, 0x54u}, {0xC1u, 0x03u}, {0xC5u, 0xEBu}, {0xC6u, 0x0Cu}, {0xC8u, 0x07u}, {0xC9u, 0xFFu}, {0xCAu, 0xFFu}, {0xCBu, 0xFFu}, {0xCEu, 0xF0u}, {0xCFu, 0x44u}, {0xD0u, 0x0Cu}, {0xD4u, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDAu, 0x04u}, {0xDBu, 0x04u}, {0xDFu, 0x01u}, {0xE6u, 0xC0u}, {0xEAu, 0x40u}, {0xEBu, 0x02u}, {0x00u, 0x04u}, {0x01u, 0x20u}, {0x02u, 0x80u}, {0x03u, 0x02u}, {0x05u, 0x06u}, {0x07u, 0x08u}, {0x0Au, 0x60u}, {0x0Bu, 0x08u}, {0x0Du, 0x0Au}, {0x0Fu, 0x02u}, {0x10u, 0x90u}, {0x11u, 0x14u}, {0x12u, 0x01u}, {0x16u, 0x10u}, {0x17u, 0x01u}, {0x19u, 0xA2u}, {0x1Au, 0x40u}, {0x1Bu, 0x20u}, {0x1Du, 0x0Au}, {0x1Fu, 0x0Cu}, {0x20u, 0x41u}, {0x22u, 0x14u}, {0x23u, 0x04u}, {0x24u, 0x04u}, {0x26u, 0x80u}, {0x27u, 0x29u}, {0x28u, 0x10u}, {0x29u, 0x21u}, {0x2Cu, 0x02u}, {0x2Eu, 0x40u}, {0x2Fu, 0x08u}, {0x32u, 0x40u}, {0x37u, 0x09u}, {0x39u, 0x10u}, {0x3Au, 0x01u}, {0x3Bu, 0x04u}, {0x3Cu, 0x20u}, {0x3Fu, 0x02u}, {0x43u, 0x0Au}, {0x47u, 0x20u}, {0x48u, 0x02u}, {0x49u, 0x05u}, {0x50u, 0x80u}, {0x54u, 0x10u}, {0x56u, 0x10u}, {0x57u, 0x03u}, {0x59u, 0x81u}, {0x5Au, 0x08u}, {0x5Bu, 0x10u}, {0x8Cu, 0x80u}, {0x8Fu, 0x10u}, {0x91u, 0x14u}, {0x92u, 0x80u}, {0x94u, 0x41u}, {0x96u, 0x20u}, {0x9Au, 0x01u}, {0xA5u, 0x02u}, {0xA7u, 0x20u}, {0xA9u, 0x21u}, {0xAAu, 0x01u}, {0xB6u, 0x01u}, {0xC0u, 0x7Fu}, {0xC2u, 0xBEu}, {0xC4u, 0x3Fu}, {0xCAu, 0x37u}, {0xCCu, 0xC8u}, {0xCEu, 0xA7u}, {0xD0u, 0x23u}, {0xD2u, 0x08u}, {0xD6u, 0x0Fu}, {0xEAu, 0x10u}, {0x0Au, 0x40u}, {0x5Fu, 0x02u}, {0xC2u, 0x10u}, {0xD6u, 0x80u}, {0xAAu, 0x40u}, {0xB7u, 0x02u}, {0xE8u, 0x20u}, {0x10u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; CYPACKED typedef struct { void CYFAR *dest; const void CYCODE *src; uint16 size; } CYPACKED_ATTR cfg_memcpy_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U1_BASE), 896u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; /* UDB_0_1_0_CONFIG Address: CYDEV_UDB_P0_U0_BASE Size (bytes): 128 */ static const uint8 CYCODE BS_UDB_0_1_0_CONFIG_VAL[] = { 0xFFu, 0x10u, 0x00u, 0x00u, 0xC3u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x08u, 0xF0u, 0x00u, 0x41u, 0x3Cu, 0x00u, 0x42u, 0xF3u, 0x00u, 0x0Cu, 0x03u, 0x82u, 0x3Cu, 0x00u, 0x41u, 0x04u, 0x00u, 0x00u, 0x04u, 0x00u, 0x7Fu, 0xF3u, 0x00u, 0x08u, 0x04u, 0x00u, 0x00u, 0x00u, 0x18u, 0x00u, 0x00u, 0x0Cu, 0x67u, 0x00u, 0x18u, 0x1Cu, 0x00u, 0xE3u, 0x00u, 0xC0u, 0x1Fu, 0x2Cu, 0x40u, 0x0Fu, 0x20u, 0x1Cu, 0x00u, 0x00u, 0x08u, 0x28u, 0x02u, 0x00u, 0x00u, 0x00u, 0x10u, 0x64u, 0x03u, 0x05u, 0x00u, 0x01u, 0x00u, 0xE0u, 0xC0u, 0x28u, 0xFFu, 0xFFu, 0xFFu, 0x62u, 0xA0u, 0xF0u, 0x41u, 0x0Cu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x12u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x02u, 0x00u, 0x10u, 0x30u, 0x10u, 0x00u, 0x10u, 0x10u, 0x12u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), BS_UDB_0_1_0_CONFIG_VAL, 128u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } /* Copy device configuration data into registers */ for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) { const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i]; void * CYDATA destPtr = mc->dest; const void CYCODE * CYDATA srcPtr = mc->src; uint16 CYDATA numBytes = mc->size; CYCONFIGCPYCODE(destPtr, srcPtr, numBytes); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00300000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x02000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x04000000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_PRT0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT0_BASE), 0x00000020u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00031000u); /* IOPINS0_1 Starting address: CYDEV_PRT1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00180000u); /* IOPINS0_3 Starting address: CYDEV_PRT3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_LL_DSM_CTRL), 0x00000000u); { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F3241u, /* Base address: 0x400F3200 Count: 65 */ 0x400F3326u, /* Base address: 0x400F3300 Count: 38 */ 0x400F4105u, /* Base address: 0x400F4100 Count: 5 */ 0x400F4202u, /* Base address: 0x400F4200 Count: 2 */ 0x400F4309u, /* Base address: 0x400F4300 Count: 9 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x01u, 0x04u}, {0x05u, 0x04u}, {0x07u, 0x08u}, {0x09u, 0x04u}, {0x0Bu, 0x08u}, {0x19u, 0x01u}, {0x1Bu, 0x02u}, {0x25u, 0x01u}, {0x29u, 0x01u}, {0x2Bu, 0x02u}, {0x2Eu, 0x01u}, {0x31u, 0x0Cu}, {0x35u, 0x03u}, {0x36u, 0x01u}, {0x39u, 0x22u}, {0x40u, 0x02u}, {0x45u, 0x01u}, {0x46u, 0x40u}, {0x47u, 0x05u}, {0x48u, 0x1Bu}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, {0x4Bu, 0xFFu}, {0x4Cu, 0x02u}, {0x4Du, 0x20u}, {0x4Eu, 0xF0u}, {0x52u, 0x07u}, {0x58u, 0x04u}, {0x59u, 0x0Fu}, {0x5Au, 0x0Fu}, {0x5Bu, 0x04u}, {0x5Fu, 0x01u}, {0x62u, 0x48u}, {0x63u, 0xADu}, {0x64u, 0xC0u}, {0x66u, 0xC0u}, {0x8Fu, 0x01u}, {0xA4u, 0x01u}, {0xA8u, 0x01u}, {0xAAu, 0x02u}, {0xACu, 0x01u}, {0xAEu, 0x02u}, {0xB2u, 0x03u}, {0xB3u, 0x01u}, {0xB8u, 0x0Au}, {0xBEu, 0x01u}, {0xC0u, 0x04u}, {0xC7u, 0x10u}, {0xC8u, 0x21u}, {0xC9u, 0xFFu}, {0xCAu, 0xFFu}, {0xCBu, 0xFFu}, {0xCCu, 0x02u}, {0xCDu, 0x20u}, {0xCEu, 0xF0u}, {0xD2u, 0x03u}, {0xD8u, 0x0Eu}, {0xD9u, 0x04u}, {0xDAu, 0x0Eu}, {0xDBu, 0x04u}, {0xDFu, 0x01u}, {0xE2u, 0x48u}, {0xE3u, 0xADu}, {0xE4u, 0xC0u}, {0xE6u, 0xC0u}, {0x10u, 0x2Au}, {0x15u, 0x40u}, {0x18u, 0x80u}, {0x1Au, 0x60u}, {0x1Fu, 0x80u}, {0x21u, 0x04u}, {0x24u, 0x40u}, {0x25u, 0x20u}, {0x2Fu, 0x28u}, {0x37u, 0x10u}, {0x39u, 0x80u}, {0x3Eu, 0x10u}, {0x3Fu, 0x0Au}, {0x42u, 0x40u}, {0x47u, 0x20u}, {0x48u, 0x20u}, {0x4Fu, 0x0Au}, {0x50u, 0x02u}, {0x57u, 0x28u}, {0x68u, 0x08u}, {0x69u, 0x80u}, {0x6Du, 0x40u}, {0x6Eu, 0x10u}, {0x6Fu, 0x10u}, {0x79u, 0x08u}, {0x7Fu, 0x80u}, {0x80u, 0x40u}, {0x82u, 0x10u}, {0x83u, 0x20u}, {0x89u, 0x20u}, {0x8Cu, 0x40u}, {0xC4u, 0x87u}, {0xCAu, 0x60u}, {0xCCu, 0x20u}, {0xCEu, 0xE8u}, {0xD0u, 0x21u}, {0xDEu, 0x82u}, {0xE4u, 0x04u}, {0x38u, 0x01u}, {0x3Cu, 0x01u}, {0x80u, 0x01u}, {0xCEu, 0xC0u}, {0xE2u, 0x80u}, {0x5Du, 0x08u}, {0xD6u, 0x01u}, {0x5Au, 0x01u}, {0x5Cu, 0x08u}, {0x80u, 0x08u}, {0x8Au, 0x01u}, {0x8Du, 0x08u}, {0x9Du, 0x08u}, {0xD6u, 0x03u}, {0xE0u, 0x02u}, {0xE4u, 0x01u}, {0x01u, 0x01u}, {0x10u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* PWR_BG_CONFIG Starting address: CYDEV_PWR_BG_CONFIG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PWR_BG_CONFIG), 0x00040000u); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0xEE000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x03000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x33000000u); /* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00D80000u); /* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_DR), 0x0000007Eu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00040000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC2), 0x0000003Eu); /* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_DR), 0x000000C0u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00240000u); /* IOPINS0_4 Starting address: CYDEV_GPIO_PRT4_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT4_DR), 0x00000001u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT4_PC2), 0x00000001u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG8), 0x10000000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x40000000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F3216u, /* Base address: 0x400F3200 Count: 22 */ 0x400F3319u, /* Base address: 0x400F3300 Count: 25 */ 0x400F4005u, /* Base address: 0x400F4000 Count: 5 */ 0x400F4113u, /* Base address: 0x400F4100 Count: 19 */ 0x400F4306u, /* Base address: 0x400F4300 Count: 6 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x02u, 0x08u}, {0x06u, 0x80u}, {0x0Au, 0x40u}, {0x0Eu, 0x20u}, {0x12u, 0x02u}, {0x16u, 0x04u}, {0x18u, 0xE1u}, {0x1Au, 0x1Eu}, {0x1Eu, 0x01u}, {0x26u, 0x10u}, {0x28u, 0x99u}, {0x2Au, 0x66u}, {0x2Cu, 0x55u}, {0x2Eu, 0xAAu}, {0x36u, 0xFFu}, {0x37u, 0x01u}, {0x3Eu, 0x40u}, {0x3Fu, 0x40u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, {0x5Fu, 0x01u}, {0x05u, 0x01u}, {0x06u, 0x2Au}, {0x0Du, 0x8Au}, {0x0Eu, 0x04u}, {0x14u, 0x20u}, {0x15u, 0x50u}, {0x1Fu, 0x40u}, {0x25u, 0x40u}, {0x6Du, 0x50u}, {0x6Eu, 0x04u}, {0x82u, 0x2Au}, {0x84u, 0x20u}, {0x87u, 0x40u}, {0x89u, 0xC0u}, {0x8Du, 0x01u}, {0xA1u, 0x0Au}, {0xA9u, 0x02u}, {0xB1u, 0x08u}, {0xC0u, 0xF0u}, {0xC2u, 0xF0u}, {0xC4u, 0xE0u}, {0xE2u, 0x04u}, {0xE4u, 0x40u}, {0xE6u, 0x20u}, {0xECu, 0x20u}, {0x00u, 0x80u}, {0x07u, 0x04u}, {0x51u, 0x10u}, {0xC0u, 0xC0u}, {0xD4u, 0x20u}, {0x01u, 0x10u}, {0x03u, 0x40u}, {0x05u, 0x02u}, {0x06u, 0x01u}, {0x4Bu, 0x10u}, {0x81u, 0x02u}, {0x83u, 0x40u}, {0x85u, 0x10u}, {0x87u, 0x10u}, {0x89u, 0x10u}, {0x8Eu, 0x01u}, {0x95u, 0x20u}, {0xABu, 0x04u}, {0xB0u, 0x40u}, {0xC0u, 0xF0u}, {0xD2u, 0x10u}, {0xE2u, 0x10u}, {0xE4u, 0xB0u}, {0xE8u, 0x80u}, {0x00u, 0x08u}, {0x04u, 0x04u}, {0x80u, 0x04u}, {0x88u, 0x04u}, {0xC0u, 0x0Cu}, {0xE2u, 0x04u}, {0x02u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00990067u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x000000EEu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL6), 0x00000800u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x00A00000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x00500000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0x00AA0000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG4), 0xA00A0000u); /* TCPWM_CNT0 Starting address: CYDEV_TCPWM_CNT0_TR_CTRL0 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT0_TR_CTRL0), 0x000EEE1Eu); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT0_BASE), 0x00000023u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x001B1C40u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC2), 0x00000023u); /* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000080u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x00000249u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC2), 0x00000080u); /* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT2_BASE), 0x0000003Fu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00180000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC2), 0x0000003Fu); /* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x000000C0u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x004B6D8Eu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_INTR_CFG), 0x0000F000u); /* IOPINS0_4 Starting address: CYDEV_GPIO_PRT4_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT4_BASE), 0x00000003u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT4_PC), 0x001B6024u); /* IOPINS0_6 Starting address: CYDEV_GPIO_PRT6_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT6_BASE), 0x00000004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT6_PC), 0x000300C0u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; { CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x0000DD00u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x0000CCC0u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x00DDDD0Du); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL5), 0x00D0C000u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT0_BASE), 0x0000000Cu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00000D80u); /* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x0000000Eu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x00000DB0u); /* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT2_BASE), 0x0000003Fu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00036D86u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC2), 0x00000002u); /* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00000D80u); /* IOPINS0_5 Starting address: CYDEV_GPIO_PRT5_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT5_BASE), 0x00000028u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT5_PC), 0x00030C00u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F3301u, /* Base address: 0x400F3300 Count: 1 */ 0x400F4103u, /* Base address: 0x400F4100 Count: 3 */ 0x400F4304u, /* Base address: 0x400F4300 Count: 4 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0xE6u, 0x10u}, {0x62u, 0x04u}, {0x8Eu, 0x04u}, {0xD8u, 0x40u}, {0x18u, 0x80u}, {0x8Cu, 0x40u}, {0xC6u, 0x08u}, {0xE6u, 0x08u}, {0x02u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x03000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000099u); /* FORCED_HSIOM Starting address: CYDEV_HSIOM_PORT_SEL3 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x00000000u); /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000080u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00400000u); /* IOPINS0_1 Starting address: CYDEV_PRT1_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000040u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00180000u); /* IOPINS0_3 Starting address: CYDEV_PRT3_PC */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000000u); /* IOPINS0_4 Starting address: CYDEV_PRT4_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x00000002u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000031u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x00000002u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x80000000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x20000000u); /* TCPWM_CNT0 Starting address: CYDEV_TCPWM_CNT0_TR_CTRL0 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT0_TR_CTRL0), 0x00010010u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x06u); } /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F4003u, /* Base address: 0x400F4000 Count: 3 */ 0x400F4105u, /* Base address: 0x400F4100 Count: 5 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x00u, 0x08u}, {0x04u, 0x02u}, {0xC0u, 0x30u}, {0x48u, 0x04u}, {0x4Cu, 0x01u}, {0x90u, 0x02u}, {0xA0u, 0x04u}, {0xD2u, 0x30u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00000189u); /* IOPINS0_2 Starting address: CYDEV_PRT2_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00000006u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); /* TCPWM_CNT0 Starting address: CYDEV_TCPWM_CNT0_TR_CTRL0 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT0_TR_CTRL0), 0x000E00F0u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_LL_DSM_CTRL), 0x00000000u); /* Enable the clock in the interrupt controller for the routed interrupts */ CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u); { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F0001u, /* Base address: 0x400F0000 Count: 1 */ 0x400F322Cu, /* Base address: 0x400F3200 Count: 44 */ 0x400F3323u, /* Base address: 0x400F3300 Count: 35 */ 0x400F4104u, /* Base address: 0x400F4100 Count: 4 */ 0x400F4307u, /* Base address: 0x400F4300 Count: 7 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x83u, 0x0Du}, {0x8Bu, 0x02u}, {0x8Cu, 0x01u}, {0x8Fu, 0x01u}, {0x91u, 0x04u}, {0x94u, 0x08u}, {0x9Au, 0x04u}, {0xA3u, 0x02u}, {0xA6u, 0x07u}, {0xB0u, 0x02u}, {0xB2u, 0x04u}, {0xB3u, 0x02u}, {0xB4u, 0x08u}, {0xB5u, 0x01u}, {0xB6u, 0x01u}, {0xB7u, 0x04u}, {0xBEu, 0x10u}, {0xBFu, 0x44u}, {0xC0u, 0x20u}, {0xC1u, 0x05u}, {0xC5u, 0xD1u}, {0xC7u, 0x20u}, {0xC8u, 0x23u}, {0xC9u, 0xFFu}, {0xCAu, 0xFFu}, {0xCBu, 0xFFu}, {0xCDu, 0xA0u}, {0xCFu, 0x04u}, {0xD0u, 0x18u}, {0xD2u, 0x80u}, {0xD4u, 0x05u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDAu, 0x04u}, {0xDBu, 0x04u}, {0xDFu, 0x01u}, {0xE0u, 0x40u}, {0xE2u, 0xC0u}, {0xE4u, 0x40u}, {0xE5u, 0x40u}, {0xE6u, 0xC0u}, {0xE8u, 0xC0u}, {0xEAu, 0xC0u}, {0xECu, 0xC0u}, {0xEEu, 0xC0u}, {0x00u, 0x40u}, {0x09u, 0x20u}, {0x0Au, 0x10u}, {0x10u, 0x20u}, {0x18u, 0x44u}, {0x19u, 0x40u}, {0x1Au, 0x10u}, {0x21u, 0x30u}, {0x22u, 0x04u}, {0x23u, 0x01u}, {0x2Au, 0x01u}, {0x33u, 0x01u}, {0x39u, 0x20u}, {0x3Bu, 0x40u}, {0x41u, 0x10u}, {0x48u, 0x22u}, {0x49u, 0x01u}, {0x50u, 0x02u}, {0x52u, 0x01u}, {0x59u, 0x41u}, {0x5Au, 0x08u}, {0x73u, 0x40u}, {0x83u, 0x01u}, {0x87u, 0x01u}, {0x8Cu, 0x04u}, {0xC0u, 0x01u}, {0xC2u, 0x06u}, {0xC4u, 0x04u}, {0xCAu, 0x01u}, {0xCCu, 0x01u}, {0xCEu, 0x0Cu}, {0xD0u, 0x04u}, {0xD2u, 0x08u}, {0xD6u, 0x0Bu}, {0xE2u, 0x02u}, {0x6Cu, 0x20u}, {0x80u, 0x20u}, {0xDAu, 0x80u}, {0xE2u, 0x80u}, {0x07u, 0x80u}, {0x54u, 0x02u}, {0x87u, 0x80u}, {0x8Cu, 0x02u}, {0xC0u, 0x04u}, {0xD6u, 0x04u}, {0xE4u, 0x02u}, {0x01u, 0x01u}, {0x10u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0xEE9900EEu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x00003000u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x00C00000u); /* INT_SELECT Starting address: CYDEV_CPUSS_INT_SEL */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INT_SEL), 0x00000002u); /* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000002u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT0_BASE), 0x00000023u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00DB1DA4u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC2), 0x00000020u); /* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000090u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x009B6006u); /* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT2_BASE), 0x00000021u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x0003618Au); /* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x0000000Fu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00036C90u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC2), 0x00000001u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; /* Enable the clock in the interrupt controller for the routed interrupts */ CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u); { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F0001u, /* Base address: 0x400F0000 Count: 1 */ 0x400F3028u, /* Base address: 0x400F3000 Count: 40 */ 0x400F3108u, /* Base address: 0x400F3100 Count: 8 */ 0x400F321Fu, /* Base address: 0x400F3200 Count: 31 */ 0x400F3315u, /* Base address: 0x400F3300 Count: 21 */ 0x400F4004u, /* Base address: 0x400F4000 Count: 4 */ 0x400F4105u, /* Base address: 0x400F4100 Count: 5 */ 0x400F4304u, /* Base address: 0x400F4300 Count: 4 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x82u, 0x0Du}, {0x40u, 0x51u}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, {0x4Bu, 0xFFu}, {0x4Fu, 0x01u}, {0x50u, 0x18u}, {0x5Au, 0x04u}, {0x5Du, 0x09u}, {0x5Fu, 0x01u}, {0x60u, 0x40u}, {0x62u, 0x40u}, {0x64u, 0x40u}, {0x65u, 0x40u}, {0x66u, 0x80u}, {0x68u, 0x80u}, {0x6Au, 0x80u}, {0x6Cu, 0x80u}, {0x6Eu, 0x80u}, {0xC0u, 0x41u}, {0xC9u, 0xFFu}, {0xCAu, 0xFFu}, {0xCBu, 0xFFu}, {0xCDu, 0x83u}, {0xCEu, 0x03u}, {0xCFu, 0x01u}, {0xD0u, 0x18u}, {0xD2u, 0x80u}, {0xDAu, 0x04u}, {0xDBu, 0x04u}, {0xDDu, 0x99u}, {0xDFu, 0x01u}, {0xE0u, 0x40u}, {0xE2u, 0x40u}, {0xE4u, 0x40u}, {0xE5u, 0x40u}, {0xE6u, 0x80u}, {0xE8u, 0x80u}, {0xEAu, 0x80u}, {0xECu, 0x80u}, {0xEEu, 0x80u}, {0x42u, 0x02u}, {0x46u, 0x82u}, {0x48u, 0x01u}, {0x74u, 0x01u}, {0x76u, 0x80u}, {0x77u, 0x80u}, {0xD0u, 0x98u}, {0xD2u, 0x08u}, {0x0Eu, 0x01u}, {0x2Eu, 0x01u}, {0x30u, 0x01u}, {0x3Eu, 0x01u}, {0x40u, 0x41u}, {0x45u, 0xECu}, {0x47u, 0x20u}, {0x48u, 0x23u}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, {0x4Bu, 0xFFu}, {0x4Du, 0x83u}, {0x4Eu, 0x03u}, {0x4Fu, 0x01u}, {0x50u, 0x18u}, {0x54u, 0x01u}, {0x56u, 0x04u}, {0x58u, 0x04u}, {0x5Au, 0x04u}, {0x5Bu, 0x04u}, {0x5Du, 0x99u}, {0x5Fu, 0x01u}, {0x60u, 0x40u}, {0x62u, 0x40u}, {0x64u, 0x40u}, {0x65u, 0x40u}, {0x66u, 0x80u}, {0x68u, 0x80u}, {0x6Au, 0x80u}, {0x6Cu, 0x80u}, {0x6Eu, 0x80u}, {0x06u, 0x02u}, {0x17u, 0x80u}, {0x1Eu, 0x80u}, {0x46u, 0x82u}, {0x4Du, 0x04u}, {0x4Fu, 0x01u}, {0x56u, 0x02u}, {0x5Du, 0x04u}, {0x5Eu, 0x80u}, {0x5Fu, 0x01u}, {0x67u, 0x80u}, {0x87u, 0x40u}, {0x9Au, 0x80u}, {0x9Bu, 0x80u}, {0x9Eu, 0x02u}, {0xC0u, 0x80u}, {0xC4u, 0x80u}, {0xD0u, 0x90u}, {0xD6u, 0xD0u}, {0xD8u, 0x80u}, {0xE2u, 0x80u}, {0x53u, 0x04u}, {0x6Fu, 0x02u}, {0xD4u, 0x20u}, {0xDAu, 0x80u}, {0x87u, 0x02u}, {0x8Bu, 0x04u}, {0x97u, 0x08u}, {0xA7u, 0x02u}, {0xE2u, 0x10u}, {0x19u, 0x08u}, {0x89u, 0x08u}, {0xC6u, 0x08u}, {0xE2u, 0x01u}, {0x02u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00993000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); /* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x00000001u); /* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000002u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000028u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00031C00u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC2), 0x00000020u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }
/******************************************************************************* * Function Name: cyfitter_cfg ******************************************************************************** * Summary: * This function is called by the start-up code for the selected device. It * performs all of the necessary device configuration based on the design * settings. This includes settings from the Design Wide Resources (DWR) such * as Clocks and Pins as well as any component configuration that is necessary. * * Parameters: * void * * Return: * void * *******************************************************************************/ CY_CFG_SECTION void cyfitter_cfg(void) { /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; /* Enable the clock in the interrupt controller for the routed interrupts */ CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u); { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F3123u, /* Base address: 0x400F3100 Count: 35 */ 0x400F3211u, /* Base address: 0x400F3200 Count: 17 */ 0x400F3342u, /* Base address: 0x400F3300 Count: 66 */ 0x400F4008u, /* Base address: 0x400F4000 Count: 8 */ 0x400F4106u, /* Base address: 0x400F4100 Count: 6 */ 0x400F420Bu, /* Base address: 0x400F4200 Count: 11 */ 0x400F4312u, /* Base address: 0x400F4300 Count: 18 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x00u, 0x44u}, {0x03u, 0x08u}, {0x0Au, 0x15u}, {0x10u, 0x80u}, {0x12u, 0x29u}, {0x18u, 0x40u}, {0x1Au, 0x05u}, {0x1Bu, 0x28u}, {0x21u, 0x69u}, {0x22u, 0x80u}, {0x2Au, 0x12u}, {0x2Bu, 0x21u}, {0x30u, 0x80u}, {0x31u, 0x28u}, {0x32u, 0x01u}, {0x38u, 0x04u}, {0x39u, 0xA2u}, {0x40u, 0x04u}, {0x42u, 0x10u}, {0x4Au, 0x08u}, {0x52u, 0x10u}, {0x68u, 0x14u}, {0x6Bu, 0x01u}, {0x79u, 0x40u}, {0x87u, 0x08u}, {0x88u, 0x14u}, {0xC0u, 0x07u}, {0xC2u, 0x07u}, {0xC4u, 0x0Fu}, {0xCAu, 0x0Fu}, {0xCCu, 0x0Fu}, {0xCEu, 0x0Fu}, {0xD0u, 0x06u}, {0xD2u, 0x04u}, {0xDEu, 0x08u}, {0x40u, 0x23u}, {0x41u, 0x06u}, {0x47u, 0xB0u}, {0x48u, 0x20u}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, {0x4Bu, 0xFFu}, {0x4Fu, 0x40u}, {0x50u, 0x30u}, {0x5Au, 0x0Cu}, {0x5Du, 0x09u}, {0x5Fu, 0x01u}, {0x60u, 0xF0u}, {0x62u, 0x40u}, {0x63u, 0x02u}, {0x64u, 0x10u}, {0x65u, 0x12u}, {0x01u, 0x02u}, {0x03u, 0x20u}, {0x0Au, 0x59u}, {0x10u, 0x02u}, {0x12u, 0xA8u}, {0x18u, 0x24u}, {0x1Au, 0x79u}, {0x21u, 0x90u}, {0x22u, 0x29u}, {0x23u, 0x20u}, {0x29u, 0x02u}, {0x2Au, 0x10u}, {0x2Bu, 0x20u}, {0x31u, 0x80u}, {0x32u, 0x25u}, {0x38u, 0x22u}, {0x39u, 0x80u}, {0x3Eu, 0x30u}, {0x40u, 0x04u}, {0x42u, 0x10u}, {0x46u, 0x20u}, {0x47u, 0x20u}, {0x49u, 0x02u}, {0x4Au, 0x08u}, {0x4Eu, 0x04u}, {0x50u, 0x83u}, {0x56u, 0x01u}, {0x57u, 0x01u}, {0x69u, 0x40u}, {0x6Bu, 0x08u}, {0x79u, 0x40u}, {0x7Du, 0x40u}, {0x82u, 0x12u}, {0x83u, 0x08u}, {0x86u, 0x01u}, {0x89u, 0x80u}, {0x91u, 0x80u}, {0x94u, 0x04u}, {0x95u, 0x60u}, {0x96u, 0x52u}, {0x9Au, 0x10u}, {0x9Eu, 0x03u}, {0xA2u, 0x80u}, {0xA3u, 0x20u}, {0xA4u, 0x80u}, {0xA6u, 0x28u}, {0xA7u, 0x01u}, {0xADu, 0x01u}, {0xAEu, 0x01u}, {0xAFu, 0x01u}, {0xB1u, 0x28u}, {0xB4u, 0x40u}, {0xB6u, 0x40u}, {0xC0u, 0x0Cu}, {0xC2u, 0x0Fu}, {0xC4u, 0x0Fu}, {0xCAu, 0x07u}, {0xCCu, 0x0Fu}, {0xCEu, 0x0Du}, {0xD0u, 0x66u}, {0xD2u, 0x24u}, {0xDEu, 0x18u}, {0xE0u, 0x0Cu}, {0xE8u, 0x0Au}, {0xECu, 0x02u}, {0xEEu, 0xE0u}, {0x50u, 0x02u}, {0x5Fu, 0x02u}, {0x6Cu, 0x10u}, {0x87u, 0x02u}, {0xD4u, 0x80u}, {0xD6u, 0x80u}, {0xDAu, 0x80u}, {0xE6u, 0x40u}, {0x56u, 0x80u}, {0x9Au, 0x80u}, {0xB0u, 0x02u}, {0xB2u, 0x80u}, {0xB4u, 0x10u}, {0xD4u, 0x40u}, {0x52u, 0x40u}, {0x54u, 0x80u}, {0x58u, 0x14u}, {0x5Fu, 0x88u}, {0x66u, 0x02u}, {0x88u, 0x90u}, {0xD4u, 0x07u}, {0xD6u, 0x07u}, {0xD8u, 0x01u}, {0xE0u, 0x04u}, {0xE4u, 0x01u}, {0x5Au, 0x02u}, {0x5Cu, 0x04u}, {0x66u, 0x08u}, {0x80u, 0x04u}, {0x86u, 0x40u}, {0x8Au, 0x08u}, {0x92u, 0x02u}, {0x9Eu, 0x40u}, {0xACu, 0x04u}, {0xAEu, 0x01u}, {0xAFu, 0x80u}, {0xB6u, 0x02u}, {0xB7u, 0x08u}, {0xD6u, 0x03u}, {0xD8u, 0x01u}, {0xE0u, 0x04u}, {0xE8u, 0x02u}, {0xECu, 0x02u}, {0x02u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; CYPACKED typedef struct { void CYFAR *dest; const void CYCODE *src; uint16 size; } CYPACKED_ATTR cfg_memcpy_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U1_BASE), 512u}, {(void CYFAR *)(CYDEV_UDB_P1_ROUTE_BASE), 256u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; /* UDB_0_1_0_CONFIG Address: CYDEV_UDB_P0_U0_BASE Size (bytes): 128 */ static const uint8 CYCODE BS_UDB_0_1_0_CONFIG_VAL[] = { 0x00u, 0x04u, 0x00u, 0x08u, 0x7Eu, 0xFDu, 0x81u, 0x02u, 0x10u, 0x02u, 0x20u, 0x00u, 0x01u, 0x01u, 0x02u, 0x00u, 0x00u, 0xC3u, 0x00u, 0x3Cu, 0xCDu, 0x10u, 0x32u, 0x20u, 0x40u, 0x40u, 0x00u, 0x80u, 0x04u, 0x08u, 0x08u, 0x04u, 0x20u, 0x3Fu, 0x10u, 0xC0u, 0x80u, 0x02u, 0x00u, 0x00u, 0xF1u, 0x20u, 0x0Cu, 0x10u, 0x08u, 0x80u, 0x04u, 0x40u, 0x03u, 0x0Cu, 0x30u, 0x30u, 0xC0u, 0xC0u, 0x0Cu, 0x03u, 0x00u, 0x00u, 0xAAu, 0xAAu, 0x00u, 0x00u, 0x00u, 0x00u, 0x63u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0xB0u, 0x00u, 0x08u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x40u, 0x30u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x04u, 0x99u, 0x09u, 0x00u, 0x01u, 0xF0u, 0x00u, 0x40u, 0x02u, 0x10u, 0x12u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; /* UDB_0_0_0_CONFIG Address: CYDEV_UDB_P1_U1_BASE Size (bytes): 128 */ static const uint8 CYCODE BS_UDB_0_0_0_CONFIG_VAL[] = { 0x04u, 0x00u, 0x41u, 0x02u, 0x45u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x33u, 0x00u, 0x08u, 0x00u, 0x00u, 0x01u, 0xF1u, 0x02u, 0x04u, 0x4Du, 0x30u, 0xB2u, 0x4Cu, 0xBAu, 0x88u, 0x45u, 0x00u, 0x40u, 0x10u, 0x80u, 0x20u, 0x45u, 0x00u, 0x00u, 0x08u, 0x45u, 0x08u, 0x00u, 0x00u, 0x55u, 0x20u, 0x8Au, 0x10u, 0x22u, 0x00u, 0x00u, 0x00u, 0x03u, 0x0Fu, 0x3Cu, 0x0Fu, 0x08u, 0xC0u, 0xC0u, 0x30u, 0x08u, 0x00u, 0x82u, 0xA0u, 0x00u, 0x00u, 0x00u, 0x00u, 0x63u, 0x02u, 0x00u, 0x00u, 0x00u, 0xD0u, 0x0Bu, 0xF0u, 0x26u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x40u, 0x30u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x04u, 0x99u, 0x09u, 0x00u, 0x01u, 0xF0u, 0x00u, 0x40u, 0x02u, 0x10u, 0x12u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), BS_UDB_0_1_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYDEV_UDB_P1_U1_BASE), BS_UDB_0_0_0_CONFIG_VAL, 128u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (uint32)(ms->size)); } /* Copy device configuration data into registers */ for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) { const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i]; void * CYDATA destPtr = mc->dest; const void CYCODE * CYDATA srcPtr = mc->src; uint16 CYDATA numBytes = mc->size; CYCONFIGCPYCODE(destPtr, srcPtr, numBytes); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x30000003u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00000003u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x33033333u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x3330EE00u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000099u); /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000081u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00C00006u); /* IOPINS0_1 Starting address: CYDEV_PRT1_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000001u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00000006u); /* IOPINS0_2 Starting address: CYDEV_PRT2_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_DR), 0x000000DFu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00D86DB6u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x000000E0u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00DB0D80u); /* IOPINS0_4 Starting address: CYDEV_PRT4_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x00000002u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000031u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x40020000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x00010000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG8), 0x311B0000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0xD0000000u); /* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x00000001u); /* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000002u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x06u); } /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); }