static void setup_aspm(const stepping_t stepping, const int peg_enabled) { u32 tmp32; const device_t pciex = PCI_DEV(0, 1, 0); /* Prerequisites for ASPM: */ if (peg_enabled) { tmp32 = pci_read_config32(pciex, 0x200) | (3 << 13); pci_write_config32(pciex, 0x200, tmp32); tmp32 = pci_read_config32(pciex, 0x0f0); tmp32 &= ~((1 << 27) | (1 << 26)); pci_write_config32(pciex, 0x0f0, tmp32); tmp32 = pci_read_config32(pciex, 0x0f0) | (3 << 24); pci_write_config32(pciex, 0x0f0, tmp32); tmp32 = pci_read_config32(pciex, 0x0f4) & ~(1 << 4); pci_write_config32(pciex, 0x0f4, tmp32); tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 0); pci_write_config32(pciex, 0x0fc, tmp32); tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 1); pci_write_config32(pciex, 0x0fc, tmp32); tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 4); pci_write_config32(pciex, 0x0fc, tmp32); tmp32 = pci_read_config32(pciex, 0x0fc) & ~(7 << 5); pci_write_config32(pciex, 0x0fc, tmp32); /* Set L0s, L1 supported in LCTL? */ tmp32 = pci_read_config32(pciex, 0x0b0) | (3 << 0); pci_write_config32(pciex, 0x0b0, tmp32); tmp32 = pci_read_config32(pciex, 0x0f0) | (3 << 24); pci_write_config32(pciex, 0x0f0, tmp32); tmp32 = pci_read_config32(pciex, 0x0f0); if ((stepping >= STEPPING_B0) && (stepping <= STEPPING_B1)) tmp32 |= (1 << 31); else if (stepping >= STEPPING_B2) tmp32 &= ~(1 << 31); pci_write_config32(pciex, 0x0f0, tmp32); tmp32 = pci_read_config32(pciex, 0x0fc); if ((stepping >= STEPPING_B0) && (stepping <= STEPPING_B1)) tmp32 |= (1 << 10); else if (stepping >= STEPPING_B2) tmp32 &= ~(1 << 10); pci_write_config32(pciex, 0x0fc, tmp32); tmp32 = pci_read_config32(pciex, 0x0fc); if (stepping >= STEPPING_B2) tmp32 |= (1 << 14); pci_write_config32(pciex, 0x0fc, tmp32); tmp32 = pci_read_config32(pciex, 0x0fc); if (stepping >= STEPPING_B1) tmp32 &= ~(1 << 13); pci_write_config32(pciex, 0x0fc, tmp32); } DMIBAR8 (0x0e1c) |= (1 << 0); DMIBAR16(0x0f00) |= (3 << 8); DMIBAR16(0x0f00) |= (7 << 3); DMIBAR32(0x0f14) &= ~(1 << 17); DMIBAR16(0x0e1c) &= ~(1 << 8); if (stepping >= STEPPING_B0) { DMIBAR32(0x0e28 + 4) = (DMIBAR32(0x0e28 + 4) & ~(0xf << (52 - 32))) | (0xd << (52 - 32)); DMIBAR32(0x0e2c) = 0x88d07333; } if (peg_enabled) { tmp32 = pci_read_config32(pciex, 0xa08) & ~(1 << 15); pci_write_config32(pciex, 0xa08, tmp32); tmp32 = pci_read_config32(pciex, 0xa84) | (1 << 8); pci_write_config32(pciex, 0xa84, tmp32); tmp32 = pci_read_config32(pciex, 0xb14) & ~(1 << 17); pci_write_config32(pciex, 0xb14, tmp32); tmp32 = pci_read_config32(pciex, 0xb00) | (3 << 8); pci_write_config32(pciex, 0xb00, tmp32); tmp32 = pci_read_config32(pciex, 0xb00) | (7 << 3); pci_write_config32(pciex, 0xb00, tmp32); tmp32 = pci_read_config32(pciex, 0xa84) & ~(1 << 8); pci_write_config32(pciex, 0xa84, tmp32); tmp32 = pci_read_config32(pciex, 0xa84) | (1 << 8); pci_write_config32(pciex, 0xa84, tmp32); tmp32 = pci_read_config32(pciex, 0xb04); tmp32 = (tmp32 & ~(0x1f << 23)) | (0xe << 23); pci_write_config32(pciex, 0xb04, tmp32); tmp32 = pci_read_config32(pciex, 0xb04); tmp32 |= (1 << 31); pci_write_config32(pciex, 0xb04, tmp32); tmp32 = pci_read_config32(pciex, 0xb04); tmp32 = (tmp32 & ~(0x03 << 29)) | (0x1 << 29); pci_write_config32(pciex, 0xb04, tmp32); } /*\ Setup ASPM on DMI \*/ /* Exit latencies should be checked to be supported by the endpoint (ICH), but ICH doesn't give any limits. */ if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) DMIBAR8(0x88) |= (3 << 0); // enable ASPM L0s, L1 (write-once) else DMIBAR8(0x88) |= (1 << 0); // enable ASPM L0s (write-once) /* timing */ DMIBAR32(0x84) = (DMIBAR32(0x84) & ~(63 << 12)) | (2 << 12) | (2 << 15); DMIBAR8(0x208 + 3) = 0; DMIBAR32(0x208) &= ~(3 << 20); /*\ Setup ASPM on PEG \*/ /* * Maybe we just have to advertise ASPM through LCAP[11:10] * (LCAP[17:15] == 010b is the default, will be locked, as it's R/WO), * set 0x208[31:24,23:22] to zero, 0x224[24:21] = 1 and let the * generic ASPM code do the rest? – Nico */ /* TODO: Prepare PEG for ASPM. */ }
/* Platform has no romstage entry point under mainboard directory, * so this one is named with prefix mainboard. */ void mainboard_romstage_entry(unsigned long bist) { sysinfo_t sysinfo; int s3resume = 0; int cbmem_initted; u16 reg16; /* basic northbridge setup, including MMCONF BAR */ gm45_early_init(); if (bist == 0) enable_lapic(); /* First, run everything needed for console output. */ i82801ix_early_init(); setup_pch_gpios(&mainboard_gpio_map); mb_setup_lpc(); mb_setup_superio(); console_init(); report_bist_failure(bist); reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); gm45_early_reset(); } /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10); /* Check for S3 resume. */ s3resume = southbridge_detect_s3_resume(); /* RAM initialization */ enter_raminit_or_reset(); memset(&sysinfo, 0, sizeof(sysinfo)); get_mb_spd_addrmap(sysinfo.spd_map); const struct device *dev; dev = pcidev_on_root(2, 0); if (dev) sysinfo.enable_igd = dev->enabled; dev = pcidev_on_root(1, 0); if (dev) sysinfo.enable_peg = dev->enabled; get_gmch_info(&sysinfo); mb_pre_raminit_setup(&sysinfo); raminit(&sysinfo, s3resume); mb_post_raminit_setup(); const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN); /* Disable D4F0 (unknown signal controller). */ pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000); init_pm(&sysinfo, 0); i82801ix_dmi_setup(); gm45_late_init(sysinfo.stepping); i82801ix_dmi_poll_vc1(); MCHBAR16(SSKPD_MCHBAR) = 0xCAFE; init_iommu(); cbmem_initted = !cbmem_recovery(s3resume); romstage_handoff_init(cbmem_initted && s3resume); printk(BIOS_SPEW, "exit main()\n"); }
static void init_dmi(void) { u32 reg32; u16 reg16; /* Assume IGD present */ /* Clear error status */ DMIBAR32(0x1c4) = 0xffffffff; DMIBAR32(0x1d0) = 0xffffffff; /* VC0: TC0 only */ DMIBAR8(DMIVC0RCTL) = 1; DMIBAR8(0x4) = 1; /* VC1: ID1, TC7 */ reg32 = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24); reg32 = (reg32 & ~0xff) | 1 << 7; /* VC1: enable */ reg32 |= 1 << 31; reg32 = (reg32 & ~(0x7 << 17)) | (0x4 << 17); DMIBAR32(DMIVC1RCTL) = reg32; /* Set up VCs in southbridge RCBA */ RCBA8(0x3022) &= ~1; reg32 = (0x5 << 28) | (1 << 6); /* PCIe x4 */ RCBA32(0x2020) = (RCBA32(0x2020) & ~((0xf << 28) | (0x7 << 6))) | reg32; /* Assign VC1 id 1 */ RCBA32(0x20) = (RCBA32(0x20) & ~(0x7 << 24)) | (1 << 24); /* Map TC7 to VC1 */ RCBA8(0x20) &= 1; RCBA8(0x20) |= 1 << 7; /* Map TC0 to VC0 */ RCBA8(0x14) &= 1; /* Init DMI VC1 port arbitration table */ RCBA32(0x20) &= 0xfff1ffff; RCBA32(0x20) |= 1 << 19; RCBA32(0x30) = 0x0000000f; RCBA32(0x34) = 0x000f0000; RCBA32(0x38) = 0; RCBA32(0x3c) = 0x000000f0; RCBA32(0x40) = 0x0f000000; RCBA32(0x44) = 0; RCBA32(0x48) = 0x0000f000; RCBA32(0x4c) = 0; RCBA32(0x50) = 0x0000000f; RCBA32(0x54) = 0x000f0000; RCBA32(0x58) = 0; RCBA32(0x5c) = 0x000000f0; RCBA32(0x60) = 0x0f000000; RCBA32(0x64) = 0; RCBA32(0x68) = 0x0000f000; RCBA32(0x6c) = 0; RCBA32(0x20) |= 1 << 16; /* Enable VC1 */ RCBA32(0x20) |= 1 << 31; /* Wait for VC1 */ while ((RCBA8(0x26) & (1 << 1)) != 0); /* Wait for table load */ while ((RCBA8(0x26) & (1 << 0)) != 0); /* ASPM on DMI link */ RCBA16(0x1a8) &= ~0x3; reg16 = RCBA16(0x1a8); RCBA32(0x2010) = (RCBA32(0x2010) & ~(0x3 << 10)) | (1 << 10); reg32 = RCBA32(0x2010); /* Set up VC1 max time */ RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000; while ((DMIBAR32(0x26) & (1 << 1)) != 0); printk(BIOS_DEBUG, "Done DMI setup\n"); /* ASPM on DMI */ DMIBAR32(0x200) &= ~(0x3 << 26); DMIBAR16(0x210) = (DMIBAR16(0x210) & ~(0xff7)) | 0x101; DMIBAR32(0x88) &= ~0x3; DMIBAR32(0x88) |= 0x3; reg16 = DMIBAR16(0x88); }