void __init nmdk_timer_init(void) { unsigned long rate; struct clk *clk0; u32 cr = MTU_CRn_32BITS; clk0 = clk_get_sys("mtu0", NULL); BUG_ON(IS_ERR(clk0)); clk_enable(clk0); /* * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz * for ux500. * Use a divide-by-16 counter if the tick rate is more than 32MHz. * At 32 MHz, the timer (with 32 bit counter) can be programmed * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer * with 16 gives too low timer resolution. */ rate = clk_get_rate(clk0); if (rate > 32000000) { rate /= 16; cr |= MTU_CRn_PRESCALE_16; } else { cr |= MTU_CRn_PRESCALE_1; } /* Timer 0 is the free running clocksource */ writel(cr, mtu_base + MTU_CR(0)); writel(0, mtu_base + MTU_LR(0)); writel(0, mtu_base + MTU_BGLR(0)); writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0)); /* Now the clock source is ready */ nmdk_clksrc.read = nmdk_read_timer; if (clocksource_register_hz(&nmdk_clksrc, rate)) pr_err("timer: failed to initialize clock source %s\n", nmdk_clksrc.name); init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate); /* Timer 1 is used for events */ clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE); writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */ nmdk_clkevt.max_delta_ns = clockevent_delta2ns(0xffffffff, &nmdk_clkevt); nmdk_clkevt.min_delta_ns = clockevent_delta2ns(0x00000002, &nmdk_clkevt); nmdk_clkevt.cpumask = cpumask_of(0); /* Register irq and clockevents */ setup_irq(IRQ_MTU0, &nmdk_timer_irq); clockevents_register_device(&nmdk_clkevt); }
void mtu_clocksource_reset(void) { writel(MTU_CRn_DIS, mtu0_base + MTU_CR(1)); /* ClockSource: configure load and background-load, and fire it up */ writel(u8500_cycle, mtu0_base + MTU_LR(1)); writel(u8500_cycle, mtu0_base + MTU_BGLR(1)); writel(MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS | MTU_CRn_ENA | MTU_CRn_FREERUNNING, mtu0_base + MTU_CR(1)); }
void nmdk_clksrc_reset(void) { writel(0, mtu_base + MTU_CR(0)); writel(nmdk_cycle, mtu_base + MTU_LR(0)); writel(nmdk_cycle, mtu_base + MTU_BGLR(0)); writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA, mtu_base + MTU_CR(0)); }
void nmdk_clksrc_reset(void) { /* Disable */ writel(0, mtu_base + MTU_CR(0)); /* ClockSource: configure load and background-load, and fire it up */ writel(nmdk_cycle, mtu_base + MTU_LR(0)); writel(nmdk_cycle, mtu_base + MTU_BGLR(0)); writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA, mtu_base + MTU_CR(0)); }
void nmdk_clkevt_reset(void) { if (clkevt_periodic) { writel(nmdk_cycle, mtu_base + MTU_LR(1)); writel(nmdk_cycle, mtu_base + MTU_BGLR(1)); writel(MTU_CRn_PERIODIC | clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA, mtu_base + MTU_CR(1)); writel(1 << 1, mtu_base + MTU_IMSC); } else { (void) nmdk_clkevt_next(nmdk_cycle, NULL); } }
void nmdk_clkevt_reset(void) { if (clkevt_periodic) { /* Timer: configure load and background-load, and fire it up */ writel(nmdk_cycle, mtu_base + MTU_LR(1)); writel(nmdk_cycle, mtu_base + MTU_BGLR(1)); writel(MTU_CRn_PERIODIC | clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA, mtu_base + MTU_CR(1)); writel(1 << 1, mtu_base + MTU_IMSC); } else { /* Generate an interrupt to start the clockevent again */ (void) nmdk_clkevt_next(nmdk_cycle, NULL); } }
void mtu_clockevent_reset(void) { if (mtu_periodic) { /* Timer: configure load and background-load, and fire it up */ writel(u8500_cycle, mtu0_base + MTU_LR(0)); writel(u8500_cycle, mtu0_base + MTU_BGLR(0)); writel(MTU_CRn_PERIODIC | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS | MTU_CRn_ENA, mtu0_base + MTU_CR(0)); writel(1 << 0, mtu0_base + MTU_IMSC); } else { /* Generate an interrupt to start the clockevent again */ u8500_mtu_clkevt_next(u8500_cycle, NULL); } }
void __init nmdk_timer_init(void) { unsigned long rate; struct clk *clk0; struct clk *clk1; u32 cr; clk0 = clk_get_sys("mtu0", NULL); BUG_ON(IS_ERR(clk0)); clk1 = clk_get_sys("mtu1", NULL); BUG_ON(IS_ERR(clk1)); clk_enable(clk0); clk_enable(clk1); /* * Tick rate is 2.4MHz for Nomadik and 110MHz for ux500: * use a divide-by-16 counter if it's more than 16MHz */ cr = MTU_CRn_32BITS;; rate = clk_get_rate(clk0); if (rate > 16 << 20) { rate /= 16; cr |= MTU_CRn_PRESCALE_16; } else { cr |= MTU_CRn_PRESCALE_1; } clocksource_calc_mult_shift(&nmdk_clksrc, rate, MTU_MIN_RANGE); /* Timer 0 is the free running clocksource */ writel(cr, mtu_base + MTU_CR(0)); writel(0, mtu_base + MTU_LR(0)); writel(0, mtu_base + MTU_BGLR(0)); writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0)); /* Now the scheduling clock is ready */ nmdk_clksrc.read = nmdk_read_timer; if (clocksource_register(&nmdk_clksrc)) pr_err("timer: failed to initialize clock source %s\n", nmdk_clksrc.name); /* Timer 1 is used for events, fix according to rate */ cr = MTU_CRn_32BITS; rate = clk_get_rate(clk1); if (rate > 16 << 20) { rate /= 16; cr |= MTU_CRn_PRESCALE_16; } else { cr |= MTU_CRn_PRESCALE_1; } clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE); writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */ nmdk_clkevt.max_delta_ns = clockevent_delta2ns(0xffffffff, &nmdk_clkevt); nmdk_clkevt.min_delta_ns = clockevent_delta2ns(0x00000002, &nmdk_clkevt); nmdk_clkevt.cpumask = cpumask_of(0); /* Register irq and clockevents */ setup_irq(IRQ_MTU0, &nmdk_timer_irq); clockevents_register_device(&nmdk_clkevt); }