/** Initialize the low power ticker * */ void lp_ticker_init(void) { lptmr_config_t lptmrConfig; if (lp_ticker_inited) { return; } lp_ticker_inited = true; /* Setup low resolution clock - RTC */ if (!rtc_isenabled()) { rtc_init(); RTC_DisableInterrupts(RTC, kRTC_AlarmInterruptEnable | kRTC_SecondsInterruptEnable); RTC_StartTimer(RTC); } RTC->TAR = 0; /* Write clears the IRQ flag */ NVIC_ClearPendingIRQ(RTC_IRQn); NVIC_SetVector(RTC_IRQn, (uint32_t)rtc_isr); NVIC_EnableIRQ(RTC_IRQn); /* Setup high resolution clock - LPTMR */ LPTMR_GetDefaultConfig(&lptmrConfig); /* Use 32kHz drive */ CLOCK_SetXtal32Freq(OSC32K_CLK_HZ); lptmrConfig.prescalerClockSource = kLPTMR_PrescalerClock_2; LPTMR_Init(LPTMR0, &lptmrConfig); LPTMR_EnableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable); NVIC_ClearPendingIRQ(LPTMR0_IRQn); NVIC_SetVector(LPTMR0_IRQn, (uint32_t)lptmr_isr); EnableIRQ(LPTMR0_IRQn); }
void t_init(void) { LPC_TIM0->PR = 96000000-1; LPC_TIM1->PR = 96-1; *(int*)PCLKSEL0 |= 0x154; *(int*)PCLKSEL1 |= 0x50000; LPC_TIM0->TC=0; LPC_TIM0->PC=0; LPC_TIM1->TC=0; LPC_TIM1->PC=0; LPC_TIM0->MR0 = 0x1; LPC_TIM1->MR0 = 10000000; LPC_TIM0->MCR = 0x1; LPC_TIM1->MCR = 0x0; NVIC_SetVector(TIMER0_IRQn, (uint32_t)&en_uscount); // NVIC_SetVector(TIMER0_IRQn, (uint32_t)&test1); NVIC_SetVector (TIMER1_IRQn, (uint32_t)(executeI)); NVIC_EnableIRQ(TIMER0_IRQn); NVIC_DisableIRQ(TIMER1_IRQn); LPC_TIM0->TCR |= 0x1; LPC_TIM1->TCR |= 0x1; /* NVIC_SetPriority(TIMER0_IRQn, 0); NVIC_SetPriority(UART1_IRQn, 2); NVIC_SetPriority(TIMER1_IRQn, 0); NVIC_SetPriority(UART0_IRQn, 2); NVIC_SetPriority(UART3_IRQn, 2); */ }
void us_ticker_init(void) { TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; if (us_ticker_inited) return; us_ticker_inited = 1; // Enable Timer clock TIM_MST_RCC; // Configure time base TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); TIM_TimeBaseStructure.TIM_Period = 0xFFFF; TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 �s tick TIM_TimeBaseStructure.TIM_ClockDivision = 0; TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; TIM_TimeBaseInit(TIM_MST, &TIM_TimeBaseStructure); // Configure interrupts TIM_ITConfig(TIM_MST, TIM_IT_Update, ENABLE); // Update interrupt used for 32-bit counter NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)tim_update_irq_handler); NVIC_EnableIRQ(TIM_MST_UP_IRQ); // Output compare interrupt used for timeout feature NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)tim_oc_irq_handler); NVIC_EnableIRQ(TIM_MST_OC_IRQ); // Enable timer TIM_Cmd(TIM_MST, ENABLE); }
/**************************************************************************** * void spi_enable_interrupt(spi_t *obj, uint32_t handler, uint8_t enable) * * This will enable the interrupt in NVIC for the associated USART RX channel * * * obj: pointer to spi object * * handler: pointer to interrupt handler for this channel * * enable: Whether to enable (true) or disable (false) the interrupt * ****************************************************************************/ void spi_enable_interrupt(spi_t *obj, uint32_t handler, uint8_t enable) { IRQn_Type IRQvector; switch ((uint32_t)obj->spi.spi) { #ifdef USART0 case USART_0: IRQvector = USART0_RX_IRQn; break; #endif #ifdef USART1 case USART_1: IRQvector = USART1_RX_IRQn; break; #endif #ifdef USART2 case USART_2: IRQvector = USART2_RX_IRQn; break; #endif default: error("Undefined SPI peripheral"); return; } if (enable == true) { NVIC_SetVector(IRQvector, handler); USART_IntEnable(obj->spi.spi, USART_IEN_RXDATAV); NVIC_EnableIRQ(IRQvector); } else { NVIC_SetVector(IRQvector, handler); USART_IntDisable(obj->spi.spi, USART_IEN_RXDATAV); NVIC_DisableIRQ(IRQvector); } }
void us_ticker_init(void) { if (us_ticker_inited) return; us_ticker_inited = 1; // Enable timer clock TIM_MST_RCC; // Configure time base TimMasterHandle.Instance = TIM_MST; TimMasterHandle.Init.Period = 0xFFFF; TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 �s tick TimMasterHandle.Init.ClockDivision = 0; TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; HAL_TIM_Base_Init(&TimMasterHandle); // Configure interrupts __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // Update interrupt used for 32-bit counter NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)tim_update_irq_handler); NVIC_EnableIRQ(TIM_MST_UP_IRQ); // Output compare interrupt used for timeout feature NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)tim_oc_irq_handler); NVIC_EnableIRQ(TIM_MST_OC_IRQ); // Enable timer HAL_TIM_Base_Start(&TimMasterHandle); }
//****************************************************************************** void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { MBED_ASSERT(obj->index < MXC_CFG_UART_INSTANCES); // objs[obj->index] = obj; switch (obj->index) { case 0: NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler); NVIC_EnableIRQ(UART0_IRQn); break; case 1: NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler); NVIC_EnableIRQ(UART1_IRQn); break; case 2: NVIC_SetVector(UART2_IRQn, (uint32_t)uart2_handler); NVIC_EnableIRQ(UART2_IRQn); break; case 3: NVIC_SetVector(UART3_IRQn, (uint32_t)uart3_handler); NVIC_EnableIRQ(UART3_IRQn); break; default: MBED_ASSERT(0); } if (irq == RxIrq) { // Enable RX FIFO Threshold Interrupt if (enable) { // Clear pending interrupts obj->uart->intfl = obj->uart->intfl; obj->uart->inten |= (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS); } else { // Clear pending interrupts obj->uart->intfl = obj->uart->intfl; obj->uart->inten &= ~(MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS); } } else if (irq == TxIrq) { // Set TX Almost Empty level to interrupt when empty MXC_SET_FIELD(&obj->uart->tx_fifo_ctrl, MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL, (MXC_UART_FIFO_DEPTH - 1) << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS); // Enable TX Almost Empty Interrupt if (enable) { // Clear pending interrupts obj->uart->intfl = obj->uart->intfl; obj->uart->inten |= MXC_F_UART_INTFL_TX_FIFO_AE; } else { // Clear pending interrupts obj->uart->intfl = obj->uart->intfl; obj->uart->inten &= ~MXC_F_UART_INTFL_TX_FIFO_AE; } } else { MBED_ASSERT(0); } }
// Reconfigure the HAL tick using a standard timer instead of systick. HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { // Enable timer clock TIM_MST_RCC; // Reset timer TIM_MST_RESET_ON; TIM_MST_RESET_OFF; // Update the SystemCoreClock variable SystemCoreClockUpdate(); // Configure time base TimMasterHandle.Instance = TIM_MST; TimMasterHandle.Init.Period = 0xFFFF; TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick TimMasterHandle.Init.ClockDivision = 0; TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; HAL_TIM_Base_Init(&TimMasterHandle); // Configure output compare channel 1 for mbed timeout (enabled later when used) HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1); // Configure output compare channel 2 for HAL tick HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); // Configure interrupts // Update interrupt used for 32-bit counter // Output compare channel 1 interrupt for mbed timeout // Output compare channel 2 interrupt for HAL tick NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)timer_update_irq_handler); NVIC_EnableIRQ(TIM_MST_UP_IRQ); NVIC_SetPriority(TIM_MST_UP_IRQ, 0); NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)timer_oc_irq_handler); NVIC_EnableIRQ(TIM_MST_OC_IRQ); NVIC_SetPriority(TIM_MST_OC_IRQ, 1); // Enable interrupts __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // For 32-bit counter __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); // For HAL tick // Enable timer HAL_TIM_Base_Start(&TimMasterHandle); #if 0 // For DEBUG only __GPIOB_CLK_ENABLE(); GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Pin = GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); #endif return HAL_OK; }
int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) #endif { // DMA usage is currently ignored (void) hint; // Check buffer is ok MBED_ASSERT(tx != (void*)0); MBED_ASSERT(tx_width == 8); // support only 8b width if (tx_length == 0) return 0; // Set up buffer h_serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width); // Set up events h_serial_tx_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events h_serial_tx_enable_event(obj, event, 1); // Set only the wanted events UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; // Enable interrupt IRQn_Type irqn = h_serial_get_irq_index(obj); NVIC_ClearPendingIRQ(irqn); NVIC_DisableIRQ(irqn); NVIC_SetPriority(irqn, 1); NVIC_SetVector(irqn, (uint32_t)handler); NVIC_EnableIRQ(irqn); #if DEVICE_SERIAL_ASYNCH_DMA // Enable DMA interrupt irqn = h_serial_tx_get_irqdma_index(obj); NVIC_ClearPendingIRQ(irqn); NVIC_DisableIRQ(irqn); NVIC_SetPriority(irqn, 1); NVIC_SetVector(irqn, (uint32_t)handler); NVIC_EnableIRQ(irqn); // the following function will enable program and enable the DMA transfer if (HAL_UART_Transmit_DMA(handle, (uint8_t*)tx, tx_length) != HAL_OK) { /* Transfer error in transmission process */ return 0; } #else // the following function will enable UART_IT_TXE and error interrupts if (HAL_UART_Transmit_IT(handle, (uint8_t*)tx, tx_length) != HAL_OK) { /* Transfer error in transmission process */ return 0; } #endif DEBUG_PRINTF("UART%u: Tx: 0=(%u, %u) %x\n", obj->serial.module+1, tx_length, tx_width, HAL_UART_GetState(handle)); return tx_length; }
os_error_t os_arch_os_init(void) { os_error_t err; int i; /* Cannot be called within an ISR */ err = OS_ERR_IN_ISR; if (__get_IPSR() == 0) { err = OS_OK; /* Drop priority for all interrupts */ for (i = 0; i < sizeof(NVIC->IP); i++) { NVIC->IP[i] = 0xff; } /* * Install default interrupt handler, which'll print out system * state at the time of the interrupt, and few other regs which * should help in trying to figure out what went wrong. */ NVIC_SetVector(-13, (uint32_t)os_default_irq_asm); /* Hardfault */ NVIC_SetVector(MemoryManagement_IRQn, (uint32_t)os_default_irq_asm); NVIC_SetVector(BusFault_IRQn, (uint32_t)os_default_irq_asm); NVIC_SetVector(UsageFault_IRQn, (uint32_t)os_default_irq_asm); for (i = 0; i < NVIC_NUM_VECTORS - NVIC_USER_IRQ_OFFSET; i++) { NVIC_SetVector(i, (uint32_t)os_default_irq_asm); } /* Call bsp related OS initializations */ os_bsp_init(); /* Set the PendSV interrupt exception priority to the lowest priority */ NVIC_SetPriority(PendSV_IRQn, PEND_SV_PRIO); /* Set the SVC interrupt to priority 0 (highest configurable) */ NVIC_SetPriority(SVCall_IRQn, SVC_PRIO); /* * Set the os environment. This will set stack pointers and, based * on the contents of os_flags, will determine if the tasks run in * priviliged or un-privileged mode. */ os_set_env(); /* Check if privileged or not */ if ((__get_CONTROL() & 1) == 0) { os_arch_init(); } else { svc_os_arch_init(); } } return err; }
void lp_ticker_init(void) { if (lp_ticker_inited) { return; } lp_ticker_inited = 1; counter_major = 0; cd_major_minor_clks = 0; cd_minor_clks = 0; wakeup_tick = (uint32_t) -1; // Reset module SYS_ResetModule(timer2_modinit.rsetidx); SYS_ResetModule(timer3_modinit.rsetidx); // Select IP clock source CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv); CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv); // Enable IP clock CLK_EnableModuleClock(timer2_modinit.clkidx); CLK_EnableModuleClock(timer3_modinit.clkidx); // Configure clock uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1; MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127); MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0); uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT; MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX); // Continuous mode // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default. ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2/* | TIMER_CTL_CNTDATEN_Msk*/; ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2; // Set vector NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var); NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var); NVIC_EnableIRQ(timer2_modinit.irq_n); NVIC_EnableIRQ(timer3_modinit.irq_n); TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); // NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because // timer is not running. // Start timer TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); // Schedule wakeup to match semantics of lp_ticker_get_compare_match() lp_ticker_set_interrupt(wakeup_tick); }
/** Begin asynchronous TX transfer. The used buffer is specified in the serial object, * tx_buff * * @param obj The serial object * @param tx The buffer for sending * @param tx_length The number of words to transmit * @param tx_width The bit width of buffer word * @param handler The serial handler * @param event The logical OR of events to be registered * @param hint A suggestion for how to use DMA with this transfer * @return Returns number of data transfered, or 0 otherwise */ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) { // Check buffer is ok MBED_ASSERT(tx != (void*)0); MBED_ASSERT(tx_width == 8); // support only 8b width if (tx_length == 0) return 0; // Set up buffer h_serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width); // Set up events h_serial_tx_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events h_serial_tx_enable_event(obj, event, 1); // Set only the wanted events // Enable interrupt IRQn_Type irqn = h_serial_get_irq_index(obj); NVIC_ClearPendingIRQ(irqn); NVIC_DisableIRQ(irqn); NVIC_SetPriority(irqn, 1); NVIC_SetVector(irqn, (uint32_t)handler); UartHandle.Instance = (USART_TypeDef *)SERIAL_OBJ(uart); NVIC_EnableIRQ(irqn); #if DEVICE_SERIAL_ASYNCH_DMA // Enable DMA interrupt irqn = h_serial_tx_get_irqdma_index(obj); NVIC_ClearPendingIRQ(irqn); NVIC_DisableIRQ(irqn); NVIC_SetPriority(irqn, 1); // NVIC_SetVector(irqn, (uint32_t)&h_serial_txdma_irq_handler_asynch); NVIC_SetVector(irqn, (uint32_t)handler); NVIC_EnableIRQ(irqn); // the following function will enable program and enable the DMA transfer if (HAL_UART_Transmit_DMA(&UartHandle, (uint8_t*)tx, tx_length) != HAL_OK) { /* Transfer error in transmission process */ return 0; } #else // the following function will enable UART_IT_TXE and error interrupts if (HAL_UART_Transmit_IT(&UartHandle, (uint8_t*)tx, tx_length) != HAL_OK) { /* Transfer error in transmission process */ return 0; } #endif return tx_length; }
void lp_ticker_init(void) { if (lp_ticker_inited) { return; } lp_ticker_inited = 1; counter_major = 0; cd_major_minor_ms = 0; cd_minor_ms = 0; wakeup_tick = TMR_CMP_MAX * MS_PER_TMR2_CLK / MS_PER_TICK; // Reset module SYS_ResetModule(timer2_modinit.rsetidx); SYS_ResetModule(timer3_modinit.rsetidx); // Select IP clock source CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv); CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv); // Enable IP clock CLK_EnableModuleClock(timer2_modinit.clkidx); CLK_EnableModuleClock(timer3_modinit.clkidx); // Configure clock uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_FREQ - 1; MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127); uint32_t cmp_timer2 = MS_PER_TMR2_INT / MS_PER_TMR2_CLK; MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX); // Continuous mode ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2 | TIMER_CTL_CNTDATEN_Msk; ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2; // Set vector NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var); NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var); NVIC_EnableIRQ(timer2_modinit.irq_n); NVIC_EnableIRQ(timer3_modinit.irq_n); TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); // Schedule wakeup to match semantics of lp_ticker_get_compare_match() lp_ticker_set_interrupt(lp_ticker_read(), wakeup_tick); // Start timer TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); }
/** Begin asynchronous RX transfer (enable interrupt for data collecting) * The used buffer is specified in the serial object - rx_buff * * @param obj The serial object * @param rx The buffer for sending * @param rx_length The number of words to transmit * @param rx_width The bit width of buffer word * @param handler The serial handler * @param event The logical OR of events to be registered * @param handler The serial handler * @param char_match A character in range 0-254 to be matched * @param hint A suggestion for how to use DMA with this transfer */ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) { // DMA usage is currently ignored (void) hint; /* Sanity check arguments */ MBED_ASSERT(obj); MBED_ASSERT(rx != (void*)0); MBED_ASSERT(rx_width == 8); // support only 8b width h_serial_rx_enable_event(obj, SERIAL_EVENT_RX_ALL, 0); h_serial_rx_enable_event(obj, event, 1); // set CharMatch if (char_match != SERIAL_RESERVED_CHAR_MATCH) { obj->char_match = char_match; } h_serial_rx_buffer_set(obj, rx, rx_length, rx_width); IRQn_Type irqn = h_serial_get_irq_index(obj); NVIC_ClearPendingIRQ(irqn); NVIC_DisableIRQ(irqn); NVIC_SetPriority(irqn, 0); NVIC_SetVector(irqn, (uint32_t)handler); NVIC_EnableIRQ(irqn); UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; // flush current data + error flags __HAL_UART_CLEAR_PEFLAG(handle); #if DEVICE_SERIAL_ASYNCH_DMA // Enable DMA interrupt irqn = h_serial_rx_get_irqdma_index(obj); NVIC_ClearPendingIRQ(irqn); NVIC_DisableIRQ(irqn); NVIC_SetPriority(irqn, 1); NVIC_SetVector(irqn, (uint32_t)handler); NVIC_EnableIRQ(irqn); // following HAL function will program and enable the DMA transfer MBED_UART_Receive_DMA(handle, (uint8_t*)rx, rx_length); #else // following HAL function will enable the RXNE interrupt + error interrupts HAL_UART_Receive_IT(handle, (uint8_t*)rx, rx_length); #endif /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(handle, UART_IT_ERR); DEBUG_PRINTF("UART%u: Rx: 0=(%u, %u, %u) %x\n", obj->serial.module+1, rx_length, rx_width, char_match, HAL_UART_GetState(handle)); return; }
static void lptmr_init(void) { uint32_t extosc; /* Clock the timer */ SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK; /* Reset */ LPTMR0->CSR = 0; #if defined(TARGET_KL43Z) /* Set interrupt handler */ NVIC_SetVector(LPTMR0_IRQn, (uint32_t)lptmr_isr); NVIC_EnableIRQ(LPTMR0_IRQn); MCG->C1 |= MCG_C1_IRCLKEN_MASK; extosc = mcgirc_frequency(); #else /* Set interrupt handler */ NVIC_SetVector(LPTimer_IRQn, (uint32_t)lptmr_isr); NVIC_EnableIRQ(LPTimer_IRQn); /* Clock at (1)MHz -> (1)tick/us */ /* Check if the external oscillator can be divided to 1MHz */ extosc = extosc_frequency(); #endif if (extosc != 0) { //If external oscillator found if (extosc % 1000000u == 0) { //If it is a multiple if 1MHz extosc /= 1000000; if (extosc == 1) { //1MHz, set timerprescaler in bypass mode LPTMR0->PSR = LPTMR_PSR_PCS(3) | LPTMR_PSR_PBYP_MASK; return; } else { //See if we can divide it to 1MHz uint32_t divider = 0; extosc >>= 1; while (1) { if (extosc == 1) { LPTMR0->PSR = LPTMR_PSR_PCS(3) | LPTMR_PSR_PRESCALE(divider); return; } if (extosc % 2 != 0) //If we can't divide by two anymore break; divider++; extosc >>= 1; } } } }
void us_ticker_init(void) { if (ticker_inited) { return; } ticker_inited = 1; // Reset IP SYS_ResetModule(TIMER_MODINIT.rsetidx); // Select IP clock source CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); // Enable IP clock CLK_EnableModuleClock(TIMER_MODINIT.clkidx); // Timer for normal counter uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); uint32_t cmp_timer = TMR_CMP_MAX; MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default. ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/; ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer; NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); NVIC_EnableIRQ(TIMER_MODINIT.irq_n); TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); }
void us_ticker_init(void) { if (us_ticker_inited) { us_ticker_disable_interrupt(); return; } US_TICKER_COUNTER->TimerControl = 0x0ul; // disable TIMER1 and reset all control US_TICKER_INTERRUPT->TimerControl = 0x0ul; // disable TIMER2 and reset all control US_TICKER_COUNTER->TimerLoad = 0xFFFFFFFFul; US_TICKER_INTERRUPT->TimerLoad = 0xFFFFFFFFul; US_TICKER_COUNTER->TimerControl |= CMSDK_DUALTIMER1_CTRL_SIZE_Msk; // set TIMER1 to 32 bit counter US_TICKER_INTERRUPT->TimerControl |= CMSDK_DUALTIMER2_CTRL_SIZE_Msk; // set TIMER2 to 32 bit counter US_TICKER_COUNTER->TimerControl |= 0x1 << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos; // set TIMER1 with 4 stages prescale US_TICKER_INTERRUPT->TimerControl |= 0x1 << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos; // set TIMER2 with 4 stages prescale US_TICKER_INTERRUPT->TimerControl |= CMSDK_DUALTIMER2_CTRL_MODE_Msk; // set TIMER2 periodic mode US_TICKER_INTERRUPT->TimerControl |= CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk; // set TIMER2 one-shot mode US_TICKER_COUNTER->TimerControl |= CMSDK_DUALTIMER1_CTRL_EN_Msk; // enable TIMER1 counter NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); us_ticker_inited = 1; }
void os_tick_init(uint32_t os_ticks_per_sec, int prio) { os_sr_t sr; /* Reset the timer to 0. */ am_hal_stimer_counter_clear(); /* The OS tick timer uses: * o The 1024 Hz low-frequency RC oscillator (LFRC) * o The first comparator (COMPAREA) */ am_hal_stimer_config(AM_HAL_STIMER_LFRC_1KHZ | AM_HAL_STIMER_CFG_COMPARE_A_ENABLE); am_hal_stimer_int_enable(AM_HAL_STIMER_INT_COMPAREA); apollo2_os_tick_dur = APOLLO2_OS_TICK_FREQ / os_ticks_per_sec; /* Enable the STIMER interrupt in the NVIC. */ NVIC_SetPriority(APOLLO2_OS_TICK_IRQ, prio); NVIC_SetVector(APOLLO2_OS_TICK_IRQ, (uint32_t)apollo2_os_tick_handler); NVIC_EnableIRQ(APOLLO2_OS_TICK_IRQ); /* Schedule timer to interrupt at the next tick. */ OS_ENTER_CRITICAL(sr); apollo2_os_tick_set_timer(1); OS_EXIT_CRITICAL(sr); }
/** * Begin asynchronous RX transfer (enable interrupt for data collecting) * The used buffer is specified in the serial object, rx_buff * * @param obj The serial object * @param rx The buffer for sending * @param rx_length The number of words to transmit * @param rx_width The bit width of buffer word * @param handler The serial handler * @param event The logical OR of events to be registered * @param handler The serial handler * @param char_match A character in range 0-254 to be matched * @param hint A suggestion for how to use DMA with this transfer */ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) { // TODO: DMA usage is currently ignored (void) hint; /* Sanity check arguments */ MBED_ASSERT(obj); MBED_ASSERT(rx != (void*)0); MBED_ASSERT(rx_width == 8); // support only 8b width struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0); serial_enable_event(obj, event, 1); // set CharMatch obj->char_match = char_match; serial_rx_buffer_set(obj, rx, rx_length, rx_width); IRQn_Type irq_n = serial_get_irq_n(obj); NVIC_ClearPendingIRQ(irq_n); NVIC_DisableIRQ(irq_n); NVIC_SetPriority(irq_n, 0); NVIC_SetVector(irq_n, (uint32_t)handler); NVIC_EnableIRQ(irq_n); // following HAL function will enable the RXNE interrupt + error interrupts HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length); }
void lp_ticker_init() { core_util_critical_section_enter(); if (!rtc_inited) { CMU_ClockEnable(cmuClock_RTC, true); /* Initialize RTC */ RTC_Init_TypeDef init = RTC_INIT_DEFAULT; init.enable = 1; /* Don't use compare register 0 as top value */ init.comp0Top = 0; /* Initialize */ RTC_Init(&init); RTC_CounterSet(20); /* Enable Interrupt from RTC */ RTC_IntDisable(RTC_IF_COMP0); RTC_IntClear(RTC_IF_COMP0); NVIC_SetVector(RTC_IRQn, (uint32_t)RTC_IRQHandler); NVIC_EnableIRQ(RTC_IRQn); rtc_inited = true; } else { /* Cancel current interrupt by virtue of calling init again */ RTC_IntDisable(RTC_IF_COMP0); RTC_IntClear(RTC_IF_COMP0); } core_util_critical_section_exit(); }
void us_ticker_set_interrupt(unsigned int timestamp) { if (timestamp > 0xFFFF) { TIM_SetCompare1(TIM4, (uint16_t)((timestamp >> 16) & 0xFFFF)); TIM_ITConfig(TIM4, TIM_IT_CC1, ENABLE); NVIC_SetVector(TIM4_IRQn, (uint32_t)us_ticker_irq_handler); NVIC_EnableIRQ(TIM4_IRQn); }
void uvisor_disabled_set_vector(uint32_t irqn, uint32_t vector) { uint8_t box_id; /* Check IRQn. * We only allow user IRQs to be registered (NVIC). This is consistent with * the corresponding API when uVisor is enabled. */ if (irqn >= NVIC_USER_IRQ_NUMBER) { uvisor_error(USER_NOT_ALLOWED); } /* Get current box ID. * We use the call stack pointer to assess the currently active box ID. */ box_id = g_call_stack[g_call_sp]; /* Register IRQ. * If vector is 0 it corresponds to a de-registration. */ g_uvisor_disabled_vectors[irqn].box_id = vector ? box_id : 0; g_uvisor_disabled_vectors[irqn].vector = vector; /* Register default handler. * The default handler performs the context switch around the actual user * handler. */ NVIC_SetVector((IRQn_Type) irqn, (uint32_t) &uvisor_disabled_default_vector); }
// Clear or set a irq void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) { uint32_t ier; switch (type) { case IRQ_RX: ier = (1 << 0); break; case IRQ_TX: ier = (1 << 1); break; case IRQ_ERROR: ier = (1 << 2); break; case IRQ_OVERRUN: ier = (1 << 3); break; case IRQ_WAKEUP: ier = (1 << 4); break; case IRQ_PASSIVE: ier = (1 << 5); break; case IRQ_ARB: ier = (1 << 6); break; case IRQ_BUS: ier = (1 << 7); break; case IRQ_READY: ier = (1 << 8); break; default: return; } obj->dev->MOD |= 1; if(enable == 0) { obj->dev->IER &= ~ier; } else { obj->dev->IER |= ier; } obj->dev->MOD &= ~(1); // Enable NVIC if at least 1 interrupt is active if(((LPC_SC->PCONP & (1 << 13)) && LPC_CAN1->IER) || ((LPC_SC->PCONP & (1 << 14)) && LPC_CAN2->IER)) { NVIC_SetVector(CAN_IRQn, (uint32_t) &can_irq_n); NVIC_EnableIRQ(CAN_IRQn); } else { NVIC_DisableIRQ(CAN_IRQn); } }
void us_ticker_init(void) { if (us_ticker_inited) return; us_ticker_inited = 1; // Enable the SCT clock LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); // Clear peripheral reset the SCT: LPC_SYSCON->PRESETCTRL |= (1 << 8); // Unified counter (32 bits) LPC_SCT->CONFIG |= 1; // halt and clear the counter LPC_SCT->CTRL_L |= (1 << 2) | (1 << 3); // System Clock (12)MHz -> us_ticker (1)MHz LPC_SCT->CTRL_L |= ((SystemCoreClock/1000000 - 1) << 5); // unhalt the counter: // - clearing bit 2 of the CTRL register LPC_SCT->CTRL_L &= ~(1 << 2); NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); }
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { IRQn_Type irq_n = (IRQn_Type)0; uint32_t vector = 0; switch ((int)obj->uart) { case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break; case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break; case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break; } if (enable) { obj->uart->INTENSET = (1 << ((irq == RxIrq) ? 0 : 2)); NVIC_SetVector(irq_n, vector); NVIC_EnableIRQ(irq_n); } else { // disable int all_disabled = 0; SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); obj->uart->INTENSET &= ~(1 << ((irq == RxIrq) ? 0 : 2)); all_disabled = (obj->uart->INTENSET & (1 << ((other_irq == RxIrq) ? 0 : 2))) == 0; if (all_disabled) NVIC_DisableIRQ(irq_n); } }
void us_ticker_init(void) { if (us_ticker_inited) { return; } us_ticker_inited = 1; //Common for ticker/timer uint32_t busClock; // Structure to initialize PIT pit_config_t pitConfig; PIT_GetDefaultConfig(&pitConfig); PIT_Init(PIT, &pitConfig); busClock = CLOCK_GetFreq(kCLOCK_BusClk); //Timer PIT_SetTimerPeriod(PIT, kPIT_Chnl_0, busClock / 1000000 - 1); PIT_SetTimerPeriod(PIT, kPIT_Chnl_1, 0xFFFFFFFF); PIT_SetTimerChainMode(PIT, kPIT_Chnl_1, true); PIT_StartTimer(PIT, kPIT_Chnl_0); PIT_StartTimer(PIT, kPIT_Chnl_1); //Ticker PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1); PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true); NVIC_SetVector(PIT0_IRQn, (uint32_t)pit_isr); NVIC_EnableIRQ(PIT0_IRQn); }
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { IRQn_Type uart_irqs[] = UART_RX_TX_IRQS; uint32_t vector = 0; switch (obj->index) { case 0: vector = (uint32_t)&uart0_irq; break; case 1: vector = (uint32_t)&uart1_irq; break; case 2: vector = (uint32_t)&uart2_irq; break; default: break; } if (enable) { switch (irq) { case RxIrq: UART_EnableInterrupts(uart_addrs[obj->index], kUART_RxDataRegFullInterruptEnable); break; case TxIrq: UART_EnableInterrupts(uart_addrs[obj->index], kUART_TxDataRegEmptyInterruptEnable); break; default: break; } NVIC_SetVector(uart_irqs[obj->index], vector); NVIC_EnableIRQ(uart_irqs[obj->index]); } else { // disable int all_disabled = 0; SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); switch (irq) { case RxIrq: UART_DisableInterrupts(uart_addrs[obj->index], kUART_RxDataRegFullInterruptEnable); break; case TxIrq: UART_DisableInterrupts(uart_addrs[obj->index], kUART_TxDataRegEmptyInterruptEnable); break; default: break; } switch (other_irq) { case RxIrq: all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->index]) & kUART_RxDataRegFullInterruptEnable) == 0); break; case TxIrq: all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->index]) & kUART_TxDataRegEmptyInterruptEnable) == 0); break; default: break; } if (all_disabled) NVIC_DisableIRQ(uart_irqs[obj->index]); } }
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { if (pin == NC) return -1; irq_handler = handler; obj->port = pin >> PORT_SHIFT; obj->pin = (pin & 0x7F) >> 2; uint32_t ch_base, vector; IRQn_Type irq_n; switch (obj->port) { case PortA: ch_base = 0; irq_n = PORTA_IRQn; vector = (uint32_t)gpio_irqA; break; case PortB: ch_base = 32; irq_n = PORTB_IRQn; vector = (uint32_t)gpio_irqB; break; default: error("gpio_irq only supported on Port A and B"); break; } NVIC_SetVector(irq_n, vector); NVIC_EnableIRQ(irq_n); obj->ch = ch_base + obj->pin; channel_ids[obj->ch] = id; return 0; }
void i2c_enable_interrupt(i2c_t *obj, uint32_t address, uint8_t enable) { IRQn_Type irq_number; switch (i2c_get_index(obj)) { #ifdef I2C0 case 0: irq_number = I2C0_IRQn; break; #endif #ifdef I2C1 case 1: irq_number = I2C1_IRQn; break; #endif } NVIC_SetVector(irq_number, address); /* Lower IRQ priority to avoid messing with asynch RX on UART */ NVIC_SetPriority(irq_number, 1); if (enable) { NVIC_EnableIRQ(irq_number); } else { NVIC_DisableIRQ(irq_number); } }
/** * Callback to initialize an adc_dev structure from the os device * initialization callback. This sets up a nrf52_adc_device(), so * that subsequent lookups to this device allow us to manipulate it. */ int nrf52_adc_dev_init(struct os_dev *odev, void *arg) { struct adc_dev *dev; struct adc_driver_funcs *af; dev = (struct adc_dev *) odev; os_mutex_init(&dev->ad_lock); dev->ad_chans = (void *) nrf52_adc_chans; dev->ad_chan_count = NRF_SAADC_CHANNEL_COUNT; OS_DEV_SETHANDLERS(odev, nrf52_adc_open, nrf52_adc_close); assert(init_adc_config == NULL || init_adc_config == arg); init_adc_config = arg; af = &dev->ad_funcs; af->af_configure_channel = nrf52_adc_configure_channel; af->af_sample = nrf52_adc_sample; af->af_read_channel = nrf52_adc_read_channel; af->af_set_buffer = nrf52_adc_set_buffer; af->af_release_buffer = nrf52_adc_release_buffer; af->af_read_buffer = nrf52_adc_read_buffer; af->af_size_buffer = nrf52_adc_size_buffer; NVIC_SetVector(SAADC_IRQn, (uint32_t) nrfx_saadc_irq_handler); return (0); }
void us_ticker_init(void) { if (us_ticker_inited) return; us_ticker_inited = 1; // Enable the RIT clock LPC_SYSCON->SYSAHBCLKCTRL1 |= (1 << 1); // Clear peripheral reset the RIT LPC_SYSCON->PRESETCTRL1 |= (1 << 1); LPC_SYSCON->PRESETCTRL1 &= ~(1 << 1); LPC_RIT->MASK = 0; LPC_RIT->MASK_H = 0; LPC_RIT->COUNTER = 0; LPC_RIT->COUNTER_H = 0; LPC_RIT->COMPVAL = 0xffffffff; LPC_RIT->COMPVAL_H = 0x0000ffff; // Timer enable, enable for debug LPC_RIT->CTRL = 0xC; NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); }