/* PTR data structures
ptr_dev PTR device descriptor
ptr_unit PTR unit descriptor
ptr_reg PTR register list
*/
DIB ptr_dib = { DEV_PTR, 1, { &ptr } };
UNIT ptr_unit = {
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),
SERIAL_IN_WAIT
};
REG ptr_reg[] = {
{ ORDATA (BUF, ptr_unit.buf, 8) },
{ FLDATA (DONE, dev_done, INT_V_PTR) },
{ FLDATA (ENABLE, int_enable, INT_V_PTR) },
{ FLDATA (INT, int_req, INT_V_PTR) },
{ DRDATA (POS, ptr_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
{ NULL }
};
MTAB ptr_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", NULL, NULL, &show_dev },
{ 0 }
};
DEVICE ptr_dev = {
/* PTR data structures
ptr_dev PTR device descriptor
ptr_unit PTR unit
ptr_reg PTR register list
*/
DIB ptr_dib = { CHAN_W, DEV_PTR, XFR_PTR, std_tplt, &ptr };
UNIT ptr_unit = {
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),
SERIAL_IN_WAIT
};
REG ptr_reg[] = {
{ ORDATA (BUF, ptr_unit.buf, 7) },
{ FLDATA (XFR, xfr_req, XFR_V_PTR) },
{ FLDATA (SOR, ptr_sor, 0) },
{ DRDATA (POS, ptr_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, ptr_unit.wait, 24), REG_NZ + PV_LEFT },
{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
{ NULL }
};
MTAB ptr_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "CHANNEL", "CHANNEL",
&set_chan, &show_chan, NULL },
{ 0 }
};
DEVICE ptr_dev = {
ptr_dev PTR device descriptor
ptr_unit PTR unit descriptor
ptr_mod PTR modifiers
ptr_reg PTR register list
*/
DIB ptr_dib = { &ptrio, PTR };
UNIT ptr_unit = {
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),
SERIAL_IN_WAIT
};
REG ptr_reg[] = {
{ ORDATA (BUF, ptr_unit.buf, 8) },
{ FLDATA (CTL, ptr.control, 0) },
{ FLDATA (FLG, ptr.flag, 0) },
{ FLDATA (FBF, ptr.flagbuf, 0) },
{ DRDATA (TRLCTR, ptr_trlcnt, 8), REG_HRO },
{ DRDATA (TRLLIM, ptr_trllim, 8), PV_LEFT },
{ DRDATA (POS, ptr_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
{ ORDATA (SC, ptr_dib.select_code, 6), REG_HRO },
{ ORDATA (DEVNO, ptr_dib.select_code, 6), REG_HRO },
{ NULL }
};
MTAB ptr_mod[] = {
{ UNIT_DIAG, UNIT_DIAG, "diagnostic mode", "DIAG", NULL },
t_stat inq_svc (UNIT *uptr);
t_stat inq_reset (DEVICE *dptr);
void inq_puts (char *cptr);
/* INQ data structures
inq_dev INQ device descriptor
inq_unit INQ unit descriptor
inq_reg INQ register list
*/
UNIT inq_unit = { UDATA (&inq_svc, 0, 0), KBD_POLL_WAIT };
REG inq_reg[] = {
{ ORDATA (INQC, inq_char, 7) },
{ FLDATA (INR, ind[IN_INR], 0) },
{ FLDATA (INC, ind[IN_INC], 0) },
{ DRDATA (TIME, inq_unit.wait, 24), REG_NZ + PV_LEFT },
{ NULL }
};
MTAB inq_mod[] = {
{ UNIT_PCH, 0, "business set", "BUSINESS" },
{ UNIT_PCH, UNIT_PCH, "Fortran set", "FORTRAN" },
{ 0 }
};
DEVICE inq_dev = {
"INQ", &inq_unit, inq_reg, inq_mod,
1, 10, 31, 1, 8, 7,
ttix_dev TTIx device descriptor
ttix_unit TTIx unit descriptor
ttix_reg TTIx register list
ttix_mod TTIx modifiers list
*/
DIB ttix_dib = {
DEV_TTO1, 8, NULL,
{ &ttox, &ttix, &ttox, &ttix, &ttox, &ttix, &ttox, &ttix }
};
UNIT ttix_unit = { UDATA (&ttix_svc, UNIT_IDLE|UNIT_ATTABLE, 0), KBD_POLL_WAIT };
REG ttix_reg[] = {
{ BRDATA (BUF, ttix_buf, 8, 8, TTX_MAXL) },
{ ORDATA (DONE, ttix_done, TTX_MAXL) },
{ FLDATA (INT, int_hwre[API_TTI1], INT_V_TTI1) },
{ DRDATA (TIME, ttix_unit.wait, 24), REG_NZ + PV_LEFT },
{ ORDATA (DEVNUM, ttix_dib.dev, 6), REG_HRO },
{ NULL }
};
MTAB ttix_mod[] = {
{ MTAB_XTD | MTAB_VDV, 0, "LINES", "LINES",
&ttx_vlines, &tmxr_show_lines, (void *) &ttx_desc },
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &ttx_desc },
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, (void *) &ttx_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &ttx_desc },
t_stat tty_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc);
/* TTI data structures
tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
tti_mod TTI modifiers list
*/
DIB tti_dib = { DEV_TTI, 1, { &tti } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_KSR, 0), 0 };
REG tti_reg[] = {
{ ORDATA (BUF, tti_unit.buf, 8) },
{ FLDATA (DONE, dev_done, INT_V_TTI) },
{ FLDATA (ENABLE, int_enable, INT_V_TTI) },
{ FLDATA (INT, int_req, INT_V_TTI) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_KSR, "KSR", "KSR", &tty_set_mode },
{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
{ TT_MODE, TT_MODE_7P, "7b", NULL, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", NULL, NULL, &show_dev, NULL },
{ 0 }
fe_unit FE unit descriptor
fe_reg FE register list
*/
#define fei_unit fe_unit[0]
#define feo_unit fe_unit[1]
#define kaf_unit fe_unit[2]
UNIT fe_unit[] = {
{ UDATA (&fei_svc, UNIT_IDLE, 0), 0 },
{ UDATA (&feo_svc, 0, 0), SERIAL_OUT_WAIT },
{ UDATA (&kaf_svc, 0, 0), (1*1000*1000) }
};
REG fe_reg[] = {
{ ORDATA (IBUF, fei_unit.buf, 8) },
{ DRDATA (ICOUNT, fei_unit.pos, T_ADDR_W), REG_RO + PV_LEFT },
{ DRDATA (ITIME, fei_unit.wait, 24), PV_LEFT },
{ ORDATA (OBUF, feo_unit.buf, 8) },
{ DRDATA (OCOUNT, feo_unit.pos, T_ADDR_W), REG_RO + PV_LEFT },
{ DRDATA (OTIME, feo_unit.wait, 24), REG_NZ + PV_LEFT },
{ NULL }
};
MTAB fe_mod[] = {
{ UNIT_DUMMY, 0, NULL, "STOP", &fe_stop_os },
{ 0 }
};
DEVICE fe_dev = {
"FE", fe_unit, fe_reg, fe_mod,
/* LPT data structures
lpt_dev LPT device descriptor
lpt_unit LPT unit descriptor
lpt_reg LPT register list
*/
DIB lpt_dib = { DEV_LPT, 1, { &lpt } };
UNIT lpt_unit = {
UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_TEXT, 0), SERIAL_OUT_WAIT
};
REG lpt_reg[] = {
{ ORDATA (BUF, lpt_unit.buf, 8) },
{ FLDATA (ERR, lpt_err, 0) },
{ FLDATA (DONE, dev_done, INT_V_LPT) },
{ FLDATA (ENABLE, int_enable, INT_V_LPT) },
{ FLDATA (INT, int_req, INT_V_LPT) },
{ DRDATA (POS, lpt_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, lpt_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, lpt_stopioe, 0) },
{ ORDATA (DEVNUM, lpt_dib.dev, 6), REG_HRO },
{ NULL }
};
MTAB lpt_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
&set_dev, &show_dev, NULL },
{ 0 }
qty_dev QTY device descriptor
qty_unit QTY unit descriptor
qty_reg QTY register list
*/
DIB qty_dib = { DEV_QTY, INT_QTY, PI_QTY, &qty } ;
UNIT qty_unit =
{
UDATA (&qty_svc, (UNIT_ATTABLE), 0)
} ;
REG qty_reg[] = /* ('alm_reg' should be similar to this except for device code related items) */
{
{ ORDATA (BUF, qty_unit.buf, 8) },
{ FLDATA (BUSY, dev_busy, INT_V_QTY) },
{ FLDATA (DONE, dev_done, INT_V_QTY) },
{ FLDATA (DISABLE, dev_disable, INT_V_QTY) },
{ FLDATA (INT, int_req, INT_V_QTY) },
{ FLDATA (MDMCTL, qty_mdm, 0) },
{ FLDATA (AUTODS, qty_auto, 0) },
{ DRDATA (POLLS, qty_polls, 32) },
{ NULL }
} ;
MTAB qty_mod[] =
{
{ UNIT_8B, 0, "7b", "7B", NULL },
{ UNIT_8B, UNIT_8B, "8b", "8B", NULL },
/* Card reader data structures
cdr_dev CDR descriptor
cdr_unit CDR unit descriptor
cdr_reg CDR register list
*/
DIB cdr_dib = { &cdr_chsel, NULL };
UNIT cdr_unit = {
UDATA (&cdr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE+UNIT_TEXT, 0)
};
REG cdr_reg[] = {
{ ORDATA (STATE, cdr_sta, 2) },
{ DRDATA (BPTR, cdr_bptr, 5), PV_LEFT },
{ BRDATA (BUF, cdr_bbuf, 8, 36, CD_BINLNT) },
{ DRDATA (POS, cdr_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TSTART, cdr_tstart, 24), PV_LEFT + REG_NZ },
{ DRDATA (TSTOP, cdr_tstop, 24), PV_LEFT + REG_NZ },
{ DRDATA (TLEFT, cdr_tleft, 24), PV_LEFT + REG_NZ },
{ DRDATA (TRIGHT, cdr_tright, 24), PV_LEFT + REG_NZ },
{ NULL } };
MTAB cdr_mod[] = {
{ UNIT_CBN, UNIT_CBN, "column binary", "BINARY", &cd_set_mode },
{ UNIT_CBN, UNIT_CBN, "text", "TEXT", &cd_set_mode },
{ 0 }
};
/* LPT data structures
lpt_dev LPT device descriptor
lpt_unit LPT unit descriptor
lpt_reg LPT register list
*/
DIB lpt_dib = { &lpt_chsel, &lpt_chwr };
UNIT lpt_unit = {
UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_CONS+UNIT_TEXT, 0)
};
REG lpt_reg[] = {
{ ORDATA (STATE, lpt_sta, 2) },
{ ORDATA (CMD, lpt_cmd, 2) },
{ ORDATA (CHOB, lpt_chob, 36) },
{ FLDATA (CHOBV, lpt_chob_v, 0) },
{ DRDATA (BPTR, lpt_bptr, 6), PV_LEFT },
{ BRDATA (BUF, lpt_bbuf, 8, 36, LPT_BINLNT) },
{ BRDATA (EBUF, lpt_ebuf, 8, 36, LPT_ECHLNT) },
{ DRDATA (POS, lpt_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TSTART, lpt_tstart, 24), PV_LEFT + REG_NZ },
{ DRDATA (TSTOP, lpt_tstop, 24), PV_LEFT + REG_NZ },
{ DRDATA (TLEFT, lpt_tleft, 24), PV_LEFT + REG_NZ },
{ DRDATA (TRIGHT, lpt_tright, 24), PV_LEFT + REG_NZ },
{ NULL }
};
MTAB lpt_mod[] = {
/* 88DSK Standard I/O Data Structures */
UNIT dsk_unit[] = {
{ UDATA (&dsk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, DSK_SIZE) },
{ UDATA (&dsk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, DSK_SIZE) },
{ UDATA (&dsk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, DSK_SIZE) },
{ UDATA (&dsk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, DSK_SIZE) },
{ UDATA (&dsk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, DSK_SIZE) },
{ UDATA (&dsk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, DSK_SIZE) },
{ UDATA (&dsk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, DSK_SIZE) },
{ UDATA (&dsk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, DSK_SIZE) }
};
REG dsk_reg[] = {
{ ORDATA (DISK, cur_disk, 4) },
{ NULL }
};
DEVICE dsk_dev = {
"DSK", dsk_unit, dsk_reg, NULL,
8, 10, 31, 1, 8, 8,
NULL, NULL, &dsk_reset,
NULL, NULL, NULL
};
/* Service routines to handle simlulator functions */
/* service routine - actually gets char & places in buffer */
t_stat dsk_svc (UNIT *uptr)
/* Type 62 LPT data structures
lp62_dev LPT device descriptor
lp62_unit LPT unit
lp62_reg LPT register list
*/
DIB lp62_dib = { DEV_LPT, 2, &lp62_iors, { &lp62_65, &lp62_66 } };
UNIT lp62_unit = {
UDATA (&lp62_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_TEXT, 0), SERIAL_OUT_WAIT
};
REG lp62_reg[] = {
{ ORDATA (BUF, lp62_unit.buf, 8) },
{ FLDATA (INT, int_hwre[API_LPT], INT_V_LPT) },
{ FLDATA (DONE, int_hwre[API_LPT], INT_V_LPT) },
{ FLDATA (SPC, int_hwre[API_LPTSPC], INT_V_LPTSPC) },
{ DRDATA (BPTR, lp62_bp, 6) },
{ ORDATA (STATE, lp62_spc, 6), REG_HRO },
{ FLDATA (OVRPR, lp62_ovrpr, 0), REG_HRO },
{ DRDATA (POS, lp62_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, lp62_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, lp62_stopioe, 0) },
{ BRDATA (LBUF, lp62_buf, 8, 8, LP62_BSIZE) },
{ ORDATA (DEVNO, lp62_dib.dev, 6), REG_HRO },
{ NULL }
};
MTAB lp62_mod[] = {
ttix_mod TTIx modifiers list
*/
DIB ttix_dib = { DEV_KJ8, 8,
{ &ttix, &ttox, &ttix, &ttox, &ttix, &ttox, &ttix, &ttox } };
UNIT ttix_unit = { UDATA (&ttix_svc, UNIT_IDLE|UNIT_ATTABLE, 0), SERIAL_IN_WAIT };
REG ttix_reg[] = {
{ BRDATAD (BUF, ttix_buf, 8, 8, TTX_LINES, "input buffer, lines 0 to 3") },
{ GRDATAD (DONE, dev_done, 8, TTX_LINES, INT_V_TTI1, "device done flag (line 0 rightmost)") },
{ GRDATAD (ENABLE, int_enable, 8, TTX_LINES, INT_V_TTI1, "interrupt enable flag") },
{ GRDATAD (INT, int_req, 8, TTX_LINES, INT_V_TTI1, "interrupt pending flag") },
{ DRDATAD (TIME, ttix_unit.wait, 24, "initial polling interval"), REG_NZ + PV_LEFT },
{ DRDATAD (TPS, ttx_tps, 10, "polls per second after calibration"), REG_NZ + PV_LEFT },
{ ORDATA (DEVNUM, ttix_dib.dev, 6), REG_HRO },
{ NULL }
};
MTAB ttix_mod[] = {
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &ttx_desc },
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, (void *) &ttx_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &ttx_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
NULL, &tmxr_show_cstat, (void *) &ttx_desc },
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
&set_dev, &show_dev, NULL },
{ 0 }
pclk_dev PCLK device descriptor
pclk_unit PCLK unit descriptor
pclk_reg PCLK register list
*/
#define IOLN_PCLK 006
DIB pclk_dib = {
IOBA_AUTO, IOLN_PCLK, &pclk_rd, &pclk_wr,
1, IVCL (PCLK), VEC_AUTO, { NULL }
};
UNIT pclk_unit = { UDATA (&pclk_svc, UNIT_IDLE, 0) };
REG pclk_reg[] = {
{ ORDATA (CSR, pclk_csr, 16) },
{ ORDATA (CSB, pclk_csb, 16) },
{ ORDATA (CNT, pclk_ctr, 16) },
{ FLDATA (INT, IREQ (PCLK), INT_V_PCLK) },
{ FLDATA (OVFL, pclk_csr, CSR_V_ERR) },
{ FLDATA (DONE, pclk_csr, CSR_V_DONE) },
{ FLDATA (IE, pclk_csr, CSR_V_IE) },
{ FLDATA (UPDN, pclk_csr, CSR_V_UPDN) },
{ FLDATA (MODE, pclk_csr, CSR_V_MODE) },
{ FLDATA (RUN, pclk_csr, CSR_V_GO) },
{ BRDATA (TIME, xtim, 10, 32, 4), REG_NZ + PV_LEFT },
{ BRDATA (TPS, rate, 10, 32, 4), REG_NZ + PV_LEFT },
{ ORDATA (DEVADDR, pclk_dib.ba, 32), REG_HRO },
{ ORDATA (DEVVEC, pclk_dib.vec, 16), REG_HRO },
{ NULL }
};
*/
DIB rx_dib = {
IOBA_RX, IOLN_RX, &rx_rd, &rx_wr,
1, IVCL (RX), VEC_RX, { NULL }
};
UNIT rx_unit[] = {
{ UDATA (&rx_svc,
UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RX_SIZE) },
{ UDATA (&rx_svc,
UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RX_SIZE) }
};
REG rx_reg[] = {
{ ORDATA (RXCS, rx_csr, 16) },
{ ORDATA (RXDB, rx_dbr, 8) },
{ ORDATA (RXES, rx_esr, 8) },
{ ORDATA (RXERR, rx_ecode, 8) },
{ ORDATA (RXTA, rx_track, 8) },
{ ORDATA (RXSA, rx_sector, 8) },
{ DRDATA (STAPTR, rx_state, 3), REG_RO },
{ DRDATA (BUFPTR, rx_bptr, 7) },
{ FLDATA (INT, IREQ (RX), INT_V_RX) },
{ FLDATA (ERR, rx_csr, RXCS_V_ERR) },
{ FLDATA (TR, rx_csr, RXCS_V_TR) },
{ FLDATA (IE, rx_csr, RXCS_V_IE) },
{ FLDATA (DONE, rx_csr, RXCS_V_DONE) },
{ DRDATA (CTIME, rx_cwait, 24), PV_LEFT },
{ DRDATA (STIME, rx_swait, 24), PV_LEFT },
{ DRDATA (XTIME, rx_xwait, 24), PV_LEFT },
/* LPT data structures
lpt_dev LPT device descriptor
lpt_unit LPT unit descriptor
lpt_reg LPT register list
*/
DIB lpt_dib = { DEV_LPT, INT_LPT, PI_LPT, &lpt };
UNIT lpt_unit = { /* 2007-May-30, bkr */
UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_TEXT, 0), SERIAL_OUT_WAIT
};
REG lpt_reg[] = {
{ ORDATA (BUF, lpt_unit.buf, 8) },
{ FLDATA (BUSY, dev_busy, INT_V_LPT) },
{ FLDATA (DONE, dev_done, INT_V_LPT) },
{ FLDATA (DISABLE, dev_disable, INT_V_LPT) },
{ FLDATA (INT, int_req, INT_V_LPT) },
{ DRDATA (POS, lpt_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, lpt_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, lpt_stopioe, 0) },
{ NULL }
};
DEVICE lpt_dev = {
"LPT", &lpt_unit, lpt_reg, NULL,
1, 10, 31, 1, 8, 8,
NULL, NULL, &lpt_reset,
NULL, NULL, NULL,
dqd_unit DQD unit list
dqd_reg DQD register list
*/
DIB dq_dib[] = {
{ &dqdio, DQD },
{ &dqcio, DQC }
};
#define dqd_dib dq_dib[0]
#define dqc_dib dq_dib[1]
UNIT dqd_unit = { UDATA (&dqd_svc, 0, 0) };
REG dqd_reg[] = {
{ ORDATA (IBUF, dqd_ibuf, 16) },
{ ORDATA (OBUF, dqd_obuf, 16) },
{ BRDATA (DBUF, dqxb, 8, 16, DQ_NUMWD) },
{ DRDATA (BPTR, dq_ptr, DQ_N_NUMWD) },
{ FLDATA (CMD, dqd.command, 0) },
{ FLDATA (CTL, dqd.control, 0) },
{ FLDATA (FLG, dqd.flag, 0) },
{ FLDATA (FBF, dqd.flagbuf, 0) },
{ FLDATA (XFER, dqd_xfer, 0) },
{ FLDATA (WVAL, dqd_wval, 0) },
{ ORDATA (SC, dqd_dib.select_code, 6), REG_HRO },
{ ORDATA (DEVNO, dqd_dib.select_code, 6), REG_HRO },
{ NULL }
};
MTAB dqd_mod[] = {
t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc);
/* CLK data structures
clk_dev CLK device descriptor
clk_unit CLK unit descriptor
clk_reg CLK register list
*/
DIB clk_dib = { DEV_CLK, INT_CLK, PI_CLK, &clk };
UNIT clk_unit = { UDATA (&clk_svc, 0, 0) };
REG clk_reg[] = {
{ ORDATA (SELECT, clk_sel, 2) },
{ FLDATA (BUSY, dev_busy, INT_V_CLK) },
{ FLDATA (DONE, dev_done, INT_V_CLK) },
{ FLDATA (DISABLE, dev_disable, INT_V_CLK) },
{ FLDATA (INT, int_req, INT_V_CLK) },
{ DRDATA (TIME0, clk_time[0], 24), REG_NZ + PV_LEFT },
{ DRDATA (TIME1, clk_time[1], 24), REG_NZ + PV_LEFT },
{ DRDATA (TIME2, clk_time[2], 24), REG_NZ + PV_LEFT },
{ DRDATA (TIME3, clk_time[3], 24), REG_NZ + PV_LEFT },
{ DRDATA (TPS0, clk_tps[0], 6), PV_LEFT + REG_HRO },
{ NULL }
};
MTAB clk_mod[] = {
{ MTAB_XTD|MTAB_VDV, 50, NULL, "50HZ",
&clk_set_freq, NULL, NULL },
mux_dev MUX device descriptor
mux_unit MUX unit descriptor
mux_reg MUX register list
mux_mod MUX modifiers list
*/
DIB mux_dib = { -1, DEV3_GMUX, 0, NULL, &mux };
UNIT mux_unit = { UDATA (&muxi_svc, UNIT_ATTABLE, 0), MUX_INIT_POLL };
REG mux_reg[] = {
{ BRDATA (STA, mux_sta, 8, 6, MUX_LINES) },
{ BRDATA (RBUF, mux_rbuf, 8, 8, MUX_LINES) },
{ BRDATA (XBUF, mux_xbuf, 8, 8, MUX_LINES) },
{ BRDATA (INT, mux_flags, 8, 1, MUX_SCANMAX) },
{ ORDATA (SCAN, mux_scan, 7) },
{ FLDATA (SLCK, mux_slck, 0) },
{ DRDATA (TPS, mux_tps, 8), REG_NZ + PV_LEFT },
{ NULL }
};
MTAB mux_mod[] = {
{ MTAB_XTD | MTAB_VDV, 0, "LINES", "LINES",
&mux_vlines, tmxr_show_lines, (void *) &mux_desc },
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &mux_desc },
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &mux_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &mux_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
t_stat clk_svc (UNIT *uptr);
t_stat clk_reset (DEVICE *dptr);
/* CLK data structures
clk_dev CLK device descriptor
clk_unit CLK unit
clk_reg CLK register list
*/
UNIT clk_unit = {
UDATA (&clk_svc, 0, 0), 5000
};
REG clk_reg[] = {
{ ORDATA (CNTR, clk_cntr, 16) },
{ DRDATA (SBS32LVL, clk32ms_sbs, 4), REG_HRO },
{ DRDATA (SBS1MLVL, clk1min_sbs, 4), REG_HRO },
{ NULL }
};
MTAB clk_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "SBS32MSLVL", "SBS32MSLVL",
&dev_set_sbs, &dev_show_sbs, (void *) &clk32ms_sbs },
{ MTAB_XTD|MTAB_VDV, 0, "SBS1MINLVL", "SBS1MINLVL",
&dev_set_sbs, &dev_show_sbs, (void *) &clk1min_sbs },
{ 0 }
};
DEVICE clk_dev = {
"CLK", &clk_unit, clk_reg, clk_mod,
DIB rk_dib = { DEV_RK, 1, { &rk } };
UNIT rk_unit[] = {
{ UDATA (&rk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, RK_SIZE) },
{ UDATA (&rk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, RK_SIZE) },
{ UDATA (&rk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, RK_SIZE) },
{ UDATA (&rk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, RK_SIZE) }
};
REG rk_reg[] = {
{ ORDATA (RKSTA, rk_sta, 12) },
{ ORDATA (RKCMD, rk_cmd, 12) },
{ ORDATA (RKDA, rk_da, 12) },
{ ORDATA (RKMA, rk_ma, 12) },
{ FLDATA (BUSY, rk_busy, 0) },
{ FLDATA (INT, int_req, INT_V_RK) },
{ DRDATA (STIME, rk_swait, 24), PV_LEFT },
{ DRDATA (RTIME, rk_rwait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, rk_stopioe, 0) },
{ ORDATA (DEVNUM, rk_dib.dev, 6), REG_HRO },
{ NULL }
};
MTAB rk_mod[] = {
{ UNIT_HWLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_HWLK, UNIT_HWLK, "write locked", "LOCKED", NULL },
/* TTI data structures
tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
*/
DIB tti_dib = {
IOBA_TTI, IOLN_TTI, &tti_rd, &tti_wr,
1, IVCL (TTI), VEC_TTI, { NULL }
};
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), 0 };
REG tti_reg[] = {
{ ORDATA (BUF, tti_unit.buf, 8) },
{ ORDATA (CSR, tti_csr, 16) },
{ FLDATA (INT, IREQ (TTI), INT_V_TTI) },
{ FLDATA (ERR, tti_csr, CSR_V_ERR) },
{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
{ FLDATA (IE, tti_csr, CSR_V_IE) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_UC, "UC", "UC", &tty_set_mode },
{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
{ TT_MODE, TT_MODE_7P, "7b", NULL, NULL },
UNIT_ROABLE, RK_SIZE) },
{ UDATA (&rk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, RK_SIZE) }
};
REG rk_reg[] = {
{ ORDATAD (RKSTA, rk_sta, 12, "status") },
{ ORDATAD (RKCMD, rk_cmd, 12, "disk command") },
{ ORDATAD (RKDA, rk_da, 12, "disk address") },
{ ORDATAD (RKMA, rk_ma, 12, "current memory address") },
{ FLDATAD (BUSY, rk_busy, 0, "control busy flag") },
{ FLDATAD (INT, int_req, INT_V_RK, "interrupt pending flag") },
{ DRDATAD (STIME, rk_swait, 24, "seek time, per cylinder"), PV_LEFT },
{ DRDATAD (RTIME, rk_rwait, 24, "rotational delay"), PV_LEFT },
{ FLDATAD (STOP_IOE, rk_stopioe, 0, "stop on I/O error") },
{ ORDATA (DEVNUM, rk_dib.dev, 6), REG_HRO },
{ NULL }
};
MTAB rk_mod[] = {
{ UNIT_HWLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_HWLK, UNIT_HWLK, "write locked", "LOCKED", NULL },
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
&set_dev, &show_dev, NULL },
{ 0 }
};
DEVICE rk_dev = {
"RK", rk_unit, rk_reg, rk_mod,
RK_NUMDR, 8, 24, 1, 8, 12,
NULL, NULL, &rk_reset,
{ UDATA (&dp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, CAP_4651) },
{ UDATA (&dp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, CAP_4651) },
{ UDATA (&dp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, CAP_4651) },
{ UDATA (&dp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, CAP_4651) },
{ UDATA (&dp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, CAP_4651) },
{ UDATA (&dp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, CAP_4651) }
};
REG dp_reg[] = {
{ ORDATA (STA, dp_sta, 16) },
{ ORDATA (BUF, dp_buf, 16) },
{ ORDATA (FNC, dp_fnc, 4) },
{ ORDATA (CW1, dp_cw1, 16) },
{ ORDATA (CW2, dp_cw2, 16) },
{ ORDATA (CSUM, dp_csum, 16) },
{ FLDATA (BUSY, dp_sta, 15) },
{ FLDATA (RDY, dp_sta, 14) },
{ FLDATA (EOR, dp_eor, 0) },
{ FLDATA (DEFINT, dp_defint, 0) },
{ FLDATA (INTREQ, dev_int, INT_V_DP) },
{ FLDATA (ENABLE, dev_enb, INT_V_DP) },
{ BRDATA (TBUF, dpxb, 8, 16, DP_TRKLEN) },
{ ORDATA (RPTR, dp_rptr, 11), REG_RO },
{ ORDATA (WPTR, dp_wptr, 11), REG_RO },
{ ORDATA (BCTR, dp_bctr, 15), REG_RO },
DIB rp_dib = { DEV_RP, 2, &rp_iors, { &rp63, &rp64 } };
UNIT rp_unit[] = {
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP_SIZE) },
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP_SIZE) },
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP_SIZE) },
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP_SIZE) },
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP_SIZE) },
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP_SIZE) },
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP_SIZE) },
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP_SIZE) }
};
REG rp_reg[] = {
{ ORDATA (STA, rp_sta, 18) },
{ ORDATA (STB, rp_stb, 18) },
{ ORDATA (DA, rp_da, 18) },
{ ORDATA (MA, rp_ma, 18) },
{ ORDATA (WC, rp_wc, 18) },
{ FLDATA (INT, int_hwre[API_RP], INT_V_RP) },
{ FLDATA (BUSY, rp_busy, 0) },
{ FLDATA (STOP_IOE, rp_stopioe, 0) },
{ DRDATA (STIME, rp_swait, 24), PV_LEFT },
{ DRDATA (RTIME, rp_rwait, 24), PV_LEFT },
{ ORDATA (DEVNO, rp_dib.dev, 6), REG_HRO },
{ NULL }
};
MTAB rp_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
/* RX11 data structures
rx_dev RX device descriptor
rx_unit RX unit list
rx_reg RX register list
rx_mod RX modifier list
*/
UNIT rx_unit[] = {
{ UDATA (&rx_svc,
UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RX_SIZE) },
{ UDATA (&rx_svc,
UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RX_SIZE) } };
REG rx_reg[] = {
{ ORDATA (RXCS, rx_csr, 16) },
{ ORDATA (RXDB, rx_dbr, 8) },
{ ORDATA (RXES, rx_esr, 8) },
{ ORDATA (RXERR, rx_ecode, 8) },
{ ORDATA (RXTA, rx_track, 8) },
{ ORDATA (RXSA, rx_sector, 8) },
{ ORDATA (STAPTR, rx_state, 3), REG_RO },
{ ORDATA (BUFPTR, bptr, 7) },
{ FLDATA (INT, int_req, INT_V_RX) },
{ FLDATA (ERR, rx_csr, CSR_V_ERR) },
{ FLDATA (TR, rx_csr, RXCS_V_TR) },
{ FLDATA (IE, rx_csr, CSR_V_IE) },
{ FLDATA (DONE, rx_csr, RXCS_V_DONE) },
{ DRDATA (CTIME, rx_cwait, 24), PV_LEFT },
{ DRDATA (STIME, rx_swait, 24), PV_LEFT },
{ DRDATA (XTIME, rx_xwait, 24), PV_LEFT },
/* DR15 data structures
dr15_dev DR15 device descriptor
dr15_unit DR15 unit descriptor
dr15_reg DR15 register list
*/
DIB dr15_dib = { DEV_DR, 2 ,NULL, { &dr60, &dr61 } };
UNIT dr15_unit = {
UDATA (&dr15_svc, UNIT_FIX+UNIT_BINK+UNIT_ATTABLE, UC15_STATE_SIZE)
};
REG dr15_reg[] = {
{ ORDATA (TCBP, dr15_tcbp, ADDRSIZE) },
{ FLDATA (TCBACK, dr15_tcb_ack, 0) },
{ FLDATA (IE, dr15_ie, 0) },
{ ORDATA (REQ, dr15_int_req, 4) },
{ FLDATA (API0, int_hwre[API_DR0], INT_V_DR) },
{ FLDATA (API1, int_hwre[API_DR1], INT_V_DR) },
{ FLDATA (API2, int_hwre[API_DR2], INT_V_DR) },
{ FLDATA (API3, int_hwre[API_DR3], INT_V_DR) },
{ ORDATA (APIVEC0, api_vec[API_DR0][INT_V_DR], 7) },
{ ORDATA (APIVEC1, api_vec[API_DR1][INT_V_DR], 7) },
{ ORDATA (APIVEC2, api_vec[API_DR2][INT_V_DR], 7) },
{ ORDATA (APIVEC3, api_vec[API_DR3][INT_V_DR], 7) },
{ DRDATA (POLL, dr15_poll, 10), REG_NZ },
{ ORDATA (DEVNO, dr15_dib.dev, 6), REG_HRO },
{ NULL }
};
/* DCS data structures
dcs_dev DCS device descriptor
dcs_unit DCS unit descriptor
dcs_reg DCS register list
dcs_mod DCS modifiers list
*/
UNIT dcs_unit = { UDATA (&dcsi_svc, UNIT_ATTABLE, 0) };
REG dcs_reg[] = {
{ BRDATA (BUF, dcs_buf, 8, 8, DCS_LINES) },
{ BRDATA (FLAGS, dcs_flg, 8, 1, DCS_LINES) },
{ FLDATA (SCNF, iosta, IOS_V_DCS) },
{ ORDATA (SCAN, dcs_scan, 5) },
{ ORDATA (SEND, dcs_send, 5) },
{ DRDATA (SBSLVL, dcs_sbs, 4), REG_HRO },
{ NULL }
};
MTAB dcs_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "SBSLVL", "SBSLVL",
&dev_set_sbs, &dev_show_sbs, (void *) &dcs_sbs },
{ MTAB_XTD | MTAB_VDV, 0, "LINES", "LINES",
&dcs_vlines, &tmxr_show_lines, (void *) &dcs_desc },
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, (void *) &dcs_desc },
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &dcs_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
ptr_dev PTR device descriptor
ptr_unit PTR unit descriptor
ptr_mod PTR modifiers
ptr_reg PTR register list
*/
DIB ptr_dib = { PTR, IOBUS, 1, &ptrio };
UNIT ptr_unit = {
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),
SERIAL_IN_WAIT
};
REG ptr_reg[] = {
{ ORDATA (BUF, ptr_unit.buf, 8) },
{ FLDATA (READY, dev_int, INT_V_PTR) },
{ FLDATA (ENABLE, dev_enb, INT_V_PTR) },
{ FLDATA (MOTION, ptr_motion, 0) },
{ DRDATA (POS, ptr_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
{ ORDATA (RSTATE, ptr_unit.STA, 2), REG_HIDDEN },
{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
{ NULL }
};
MTAB pt_mod[] = {
{ UNIT_ATT+UNIT_ASC+UNIT_UASC, UNIT_ATT+UNIT_ASC, "ASCII", NULL },
{ UNIT_ATT+UNIT_ASC+UNIT_UASC, UNIT_ATT+UNIT_ASC+UNIT_UASC, "Unix ASCII", NULL },
{ 0 }
};