static void gfx_panel_setup(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script gfx_pipea_init[] = { /* CONTROL */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL), PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), /* POWER ON */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS), (config->gpu_pipea_port_select << 30 | config->gpu_pipea_power_on_delay << 16 | config->gpu_pipea_light_on_delay)), /* POWER OFF */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_OFF_DELAYS), (config->gpu_pipea_power_off_delay << 16 | config->gpu_pipea_light_off_delay)), /* DIVISOR */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR), ~0x1f, config->gpu_pipea_power_cycle_delay), REG_SCRIPT_END }; struct reg_script gfx_pipeb_init[] = { /* CONTROL */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL), PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), /* POWER ON */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS), (config->gpu_pipeb_port_select << 30 | config->gpu_pipeb_power_on_delay << 16 | config->gpu_pipeb_light_on_delay)), /* POWER OFF */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_OFF_DELAYS), (config->gpu_pipeb_power_off_delay << 16 | config->gpu_pipeb_light_off_delay)), /* DIVISOR */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR), ~0x1f, config->gpu_pipeb_power_cycle_delay), REG_SCRIPT_END }; if (config->gpu_pipea_port_select) { printk(BIOS_INFO, "GFX: Initialize PIPEA\n"); reg_script_run_on_dev(dev, gfx_pipea_init); set_backlight_pwm(dev, PIPEA_REG(BACKLIGHT_CTL), config->gpu_pipea_pwm_freq_hz); } if (config->gpu_pipeb_port_select) { printk(BIOS_INFO, "GFX: Initialize PIPEB\n"); reg_script_run_on_dev(dev, gfx_pipeb_init); set_backlight_pwm(dev, PIPEB_REG(BACKLIGHT_CTL), config->gpu_pipeb_pwm_freq_hz); } }
/* Warm Reset a USB3 port */ static void xhci_reset_port_usb3(device_t dev, int port) { struct reg_script reset_port_usb3_script[] = { /* Issue Warm Port Rest to the port */ REG_RES_OR32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), XHCI_USB3_PORTSC_WPR), /* Wait up to 100ms for it to complete */ REG_RES_POLL32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), XHCI_USB3_PORTSC_WRC, XHCI_USB3_PORTSC_WRC, XHCI_RESET_TIMEOUT), /* Clear change status bits, do not set PED */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), ~XHCI_USB3_PORTSC_PED, XHCI_USB3_PORTSC_CHST), REG_SCRIPT_END }; reg_script_run_on_dev(dev, reset_port_usb3_script); }
gms >>= 3; if (gms > ARRAY_SIZE(gms_size_map)) return; gmsize = gms_size_map[gms]; /* PcBase = BDSM + GMS Size - WOPCMSZ - PowerContextSize */ pcbase = pci_read_config32(dev, GSM_BASE) & 0xfff00000; pcbase += (gmsize-1) * wopcmsz - pcsize; pcbase |= 1; /* Lock */ write32((u32 *)(uintptr_t)(res->base + 0x182120), pcbase); } static const struct reg_script gfx_init_script[] = { /* Allow-Wake render/media wells */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x130090, ~1, 1), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130094, 1, 1, GFX_TIMEOUT), /* Render Force-Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80008000), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0x8000, GFX_TIMEOUT), /* Media Force-Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80008000), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0x8000, GFX_TIMEOUT), /* Workaround - X0:261954/A0:261955 */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x182060, ~0xf, 1), /* * PowerMeter Weights */
#define GT_CDCLK_675 3 struct reg_script haswell_early_init_script[] = { /* Enable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY), /* Enable Counters */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016), /* GFXPAUSE settings */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00070020), /* ECO Settings */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0xa180, 0xff3fffff, 0x15000000), /* Enable DOP Clock Gating */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000003fd), /* Enable Unit Level Clock Gating */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0x00000080), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0x40401000), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0x00000000), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0x02000001), /* * RC6 Settings */ /* Wake Rate Limits */
/* RCBA + 0x31c[3,2,1,0]=0011b */ REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x31c, ~0x0000000c, 0x00000003), REG_SCRIPT_END }; static const struct reg_script ehci_clock_gating_script[] = { /* Enable SB local clock gating */ REG_PCI_OR32(0x7c, 0x00004000), /* RCBA + 0x284=0xbe (step B0+) */ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x284, 0x000000be), REG_SCRIPT_END }; static const struct reg_script ehci_disable_script[] = { /* Clear Run/Stop Bit */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, ~USB2CMD_RS, 0), /* Wait for HC Halted */ REG_RES_POLL32(PCI_BASE_ADDRESS_0, USB2STS, USB2STS_HCHALT, USB2STS_HCHALT, 10000), /* Disable Interrupts */ REG_PCI_OR32(EHCI_CMD_STS, INTRDIS), /* Disable Asynchronous and Periodic Scheduler */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, ~(USB2CMD_ASE | USB2CMD_PSE), 0), /* Disable port wake */ REG_PCI_RMW32(EHCI_SBRN_FLA_PWC, ~(PORTWKIMP | PORTWKCAPMASK), 0), /* Set Function Disable bit in RCBA */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + RCBA_FUNC_DIS, RCBA_EHCI_DIS), REG_SCRIPT_END };
~0x000000f0, 0x000000f0), REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_OFFSET_COR_CONFIG_DIAG, ~0x000001c0, 0x00000000), REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_VGA_GAIN_CONFIG_DIAG, ~0x00000070, 0x00000020), REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_REE_DAC_CONTROL, ~0x00000002, 0x00000002), REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_U1_POWER_STATE_DEF, ~0x00000000, 0x00040000), REG_SCRIPT_END }; const struct reg_script xhci_init_script[] = { /* CommonXhciHcInit() */ /* BAR + 0x0c[31:16] = 0x0200 */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x000c, 0x0000ffff, 0x02000000), /* BAR + 0x0c[7:0] = 0x0a */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x000c, 0xffffff00, 0x0000000a), /* BAR + 0x8094[23,21,14]=111b */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8094, 0x00a04000), /* BAR + 0x8110[20,11,8,2]=1100b */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8110, ~0x00000104, 0x00100800), /* BAR + 0x8144[8,7,6]=111b */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8144, 0x000001c0), /* BAR + 0x8154[21,13,3]=010b */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8154, ~0x00200008, 0x80002000), /* BAR + 0x816c[19:0]=1110x100000000111100b */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x816c, 0xfff08000, 0x000e0030), /* BAR + 0x8188[26,24]=11b */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8188, 0x05000000), /* BAR + 0x8174=0x1000c0a*/