void Fifo_Init() { // Padded so that SIMD overreads in the vertex loader are safe s_video_buffer = (u8*)AllocateMemoryPages(FIFO_SIZE + 4); ResetVideoBuffer(); GpuRunningState = false; Common::AtomicStore(CommandProcessor::VITicks, CommandProcessor::m_cpClockOrigin); }
void Fifo_Init() { // Padded so that SIMD overreads in the vertex loader are safe s_video_buffer = (u8*)AllocateMemoryPages(FIFO_SIZE + 4); ResetVideoBuffer(); if (SConfig::GetInstance().bCPUThread) s_gpu_mainloop.Prepare(); s_sync_ticks.store(0); }
void RegisterMMIO(MMIO::Mapping* mmio, u32 base) { struct { u32 addr; u16* ptr; bool readonly; bool writes_align_to_32_bytes; } directly_mapped_vars[] = { { FIFO_TOKEN_REGISTER, &m_tokenReg }, // Bounding box registers are read only. { FIFO_BOUNDING_BOX_LEFT, &m_bboxleft, true }, { FIFO_BOUNDING_BOX_RIGHT, &m_bboxright, true }, { FIFO_BOUNDING_BOX_TOP, &m_bboxtop, true }, { FIFO_BOUNDING_BOX_BOTTOM, &m_bboxbottom, true }, // Some FIFO addresses need to be aligned on 32 bytes on write - only // the high part can be written directly without a mask. { FIFO_BASE_LO, MMIO::Utils::LowPart(&fifo.CPBase), false, true }, { FIFO_BASE_HI, MMIO::Utils::HighPart(&fifo.CPBase) }, { FIFO_END_LO, MMIO::Utils::LowPart(&fifo.CPEnd), false, true }, { FIFO_END_HI, MMIO::Utils::HighPart(&fifo.CPEnd) }, { FIFO_HI_WATERMARK_LO, MMIO::Utils::LowPart(&fifo.CPHiWatermark) }, { FIFO_HI_WATERMARK_HI, MMIO::Utils::HighPart(&fifo.CPHiWatermark) }, { FIFO_LO_WATERMARK_LO, MMIO::Utils::LowPart(&fifo.CPLoWatermark) }, { FIFO_LO_WATERMARK_HI, MMIO::Utils::HighPart(&fifo.CPLoWatermark) }, // FIFO_RW_DISTANCE has some complex read code different for // single/dual core. { FIFO_WRITE_POINTER_LO, MMIO::Utils::LowPart(&fifo.CPWritePointer), false, true }, { FIFO_WRITE_POINTER_HI, MMIO::Utils::HighPart(&fifo.CPWritePointer) }, // FIFO_READ_POINTER has different code for single/dual core. }; for (auto& mapped_var : directly_mapped_vars) { u16 wmask = mapped_var.writes_align_to_32_bytes ? 0xFFE0 : 0xFFFF; mmio->Register(base | mapped_var.addr, MMIO::DirectRead<u16>(mapped_var.ptr), mapped_var.readonly ? MMIO::InvalidWrite<u16>() : MMIO::DirectWrite<u16>(mapped_var.ptr, wmask) ); } mmio->Register(base | FIFO_BP_LO, MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPBreakpoint)), MMIO::ComplexWrite<u16>([](u32, u16 val) { WriteLow(fifo.CPBreakpoint, val & 0xffe0); }) ); mmio->Register(base | FIFO_BP_HI, MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.CPBreakpoint)), MMIO::ComplexWrite<u16>([](u32, u16 val) { WriteHigh(fifo.CPBreakpoint, val); }) ); // Timing and metrics MMIOs are stubbed with fixed values. struct { u32 addr; u16 value; } metrics_mmios[] = { { XF_RASBUSY_L, 0 }, { XF_RASBUSY_H, 0 }, { XF_CLKS_L, 0 }, { XF_CLKS_H, 0 }, { XF_WAIT_IN_L, 0 }, { XF_WAIT_IN_H, 0 }, { XF_WAIT_OUT_L, 0 }, { XF_WAIT_OUT_H, 0 }, { VCACHE_METRIC_CHECK_L, 0 }, { VCACHE_METRIC_CHECK_H, 0 }, { VCACHE_METRIC_MISS_L, 0 }, { VCACHE_METRIC_MISS_H, 0 }, { VCACHE_METRIC_STALL_L, 0 }, { VCACHE_METRIC_STALL_H, 0 }, { CLKS_PER_VTX_OUT, 4 }, }; for (auto& metrics_mmio : metrics_mmios) { mmio->Register(base | metrics_mmio.addr, MMIO::Constant<u16>(metrics_mmio.value), MMIO::InvalidWrite<u16>() ); } mmio->Register(base | STATUS_REGISTER, MMIO::ComplexRead<u16>([](u32) { SetCpStatusRegister(); return m_CPStatusReg.Hex; }), MMIO::InvalidWrite<u16>() ); mmio->Register(base | CTRL_REGISTER, MMIO::DirectRead<u16>(&m_CPCtrlReg.Hex), MMIO::ComplexWrite<u16>([](u32, u16 val) { UCPCtrlReg tmp(val); m_CPCtrlReg.Hex = tmp.Hex; SetCpControlRegister(); RunGpu(); }) ); mmio->Register(base | CLEAR_REGISTER, MMIO::DirectRead<u16>(&m_CPClearReg.Hex), MMIO::ComplexWrite<u16>([](u32, u16 val) { UCPClearReg tmp(val); m_CPClearReg.Hex = tmp.Hex; SetCpClearRegister(); RunGpu(); }) ); mmio->Register(base | PERF_SELECT, MMIO::InvalidRead<u16>(), MMIO::Nop<u16>() ); // Some MMIOs have different handlers for single core vs. dual core mode. mmio->Register(base | FIFO_RW_DISTANCE_LO, IsOnThread() ? MMIO::ComplexRead<u16>([](u32) { if (fifo.CPWritePointer >= fifo.SafeCPReadPointer) return ReadLow(fifo.CPWritePointer - fifo.SafeCPReadPointer); else return ReadLow(fifo.CPEnd - fifo.SafeCPReadPointer + fifo.CPWritePointer - fifo.CPBase + 32); }) : MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance)), MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance), 0xFFE0) ); mmio->Register(base | FIFO_RW_DISTANCE_HI, IsOnThread() ? MMIO::ComplexRead<u16>([](u32) { if (fifo.CPWritePointer >= fifo.SafeCPReadPointer) return ReadHigh(fifo.CPWritePointer - fifo.SafeCPReadPointer); else return ReadHigh(fifo.CPEnd - fifo.SafeCPReadPointer + fifo.CPWritePointer - fifo.CPBase + 32); }) : MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.CPReadWriteDistance)), MMIO::ComplexWrite<u16>([](u32, u16 val) { WriteHigh(fifo.CPReadWriteDistance, val); SyncGPU(SYNC_GPU_OTHER); if (fifo.CPReadWriteDistance == 0) { GPFifo::ResetGatherPipe(); ResetVideoBuffer(); } else { ResetVideoBuffer(); } RunGpu(); }) ); mmio->Register(base | FIFO_READ_POINTER_LO, IsOnThread() ? MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.SafeCPReadPointer)) : MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer)), MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer), 0xFFE0) ); mmio->Register(base | FIFO_READ_POINTER_HI, IsOnThread() ? MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.SafeCPReadPointer)) : MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.CPReadPointer)), IsOnThread() ? MMIO::ComplexWrite<u16>([](u32, u16 val) { WriteHigh(fifo.CPReadPointer, val); fifo.SafeCPReadPointer = fifo.CPReadPointer; }) : MMIO::DirectWrite<u16>(MMIO::Utils::HighPart(&fifo.CPReadPointer)) ); }