void
vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable )
{
if( xRxEnable )
{
USART_SetReceiverEnabled( xUSARTHWMappings[ucUsedPort].pUsart, 1 );
USART_EnableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IDR_RXRDY );
}
else
{
USART_DisableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IDR_RXRDY );
USART_SetReceiverEnabled( xUSARTHWMappings[ucUsedPort].pUsart, 0 );
}
if( xTxEnable )
{
if( NULL != xUSARTHWMappings[ucUsedPort].USARTNotREPin )
{
PIO_Set( xUSARTHWMappings[ucUsedPort].USARTNotREPin );
}
if( NULL != xUSARTHWMappings[ucUsedPort].USARTDEPin )
{
PIO_Set( xUSARTHWMappings[ucUsedPort].USARTDEPin );
}
USART_SetTransmitterEnabled( xUSARTHWMappings[ucUsedPort].pUsart, 1 );
USART_EnableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IER_TXRDY );
USART_DisableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IER_TXEMPTY );
}
else
{
USART_DisableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IDR_TXRDY );
USART_EnableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IER_TXEMPTY );
}
}
void usart0_change_baud(u32_t baud)
{
USART_SetTransmitterEnabled(AT91C_BASE_US0, 0);
USART_SetReceiverEnabled(AT91C_BASE_US0, 0);
AT91C_BASE_US0->US_BRGR = (BOARD_MCK / baud) / 16;
USART_SetTransmitterEnabled(AT91C_BASE_US0, 1);
USART_SetReceiverEnabled(AT91C_BASE_US0, 1);
}
uint32_t USARTD_EnableRxChannels( UsartDma *pUsartd, UsartChannel *pRxCh)
{
Usart *pUsartHw = pUsartd->pUsartHw;
// Initialize the callback
pUsartd->pRxChannel = pRxCh;
/* Enables the USART to receive data. */
USART_SetReceiverEnabled ( pUsartHw , 1);
XDMAD_FreeChannel( pUsartd->pXdmad, pRxCh->ChNum);
/* Allocate a DMA channel for USART0/1 RX. */
pRxCh->ChNum = XDMAD_AllocateChannel( pUsartd->pXdmad, pUsartd->usartId, XDMAD_TRANSFER_MEMORY);
if ( pRxCh->ChNum == XDMAD_ALLOC_FAILED ) {
return USARTD_ERROR;
}
/* Setup callbacks for USART0/1 RX */
XDMAD_SetCallback(pUsartd->pXdmad, pRxCh->ChNum, (XdmadTransferCallback)USARTD_Rx_Cb, pUsartd);
if (XDMAD_PrepareChannel( pUsartd->pXdmad, pRxCh->ChNum ))
return USARTD_ERROR;
/* Enable interrupt */
NVIC_EnableIRQ(XDMAC_IRQn);
if (_configureRxLinkList(pUsartHw, pUsartd->pXdmad, pRxCh))
return USARTD_ERROR_LOCK;
return 0;
}
void USART1_UART_Init(unsigned int baudrate) {
unsigned int mode = AT91C_US_USMODE_NORMAL
| AT91C_US_CLKS_CLOCK
| AT91C_US_CHRL_8_BITS
| AT91C_US_PAR_NONE
| AT91C_US_NBSTOP_1_BIT
| AT91C_US_CHMODE_NORMAL;
// Configure pins
PIO_Configure(pins, PIO_LISTSIZE(pins));
// Enable the peripheral clock in the PMC
PMC_EnablePeripheral(AT91C_ID_US0);
// Configure the USART in the desired mode
USART_Configure(AT91C_BASE_US0, mode, baudrate, BOARD_MCK);
// Configure the RXBUFF interrupt
AT91C_BASE_US0->US_IER = AT91C_US_RXRDY;
AIC_ConfigureIT(AT91C_ID_US0, 0, ISR_Usart0);
AIC_EnableIT(AT91C_ID_US0);
// Enable receiver & transmitter
USART_SetTransmitterEnabled(AT91C_BASE_US0, 1);
USART_SetReceiverEnabled(AT91C_BASE_US0, 1);
}
/**
* \brief Configures USART in spi mode with respect to state
* \param state the master or slave of USART
*/
static void _ConfigureUsart( uint8_t state )
{
uint32_t mode = US_MR_USART_MODE_SPI_MASTER | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT
| US_MR_PAR_NO | US_MR_CHMODE_NORMAL | US_MR_CLKO
| US_SPI_BPMODE_1 ;
/* slave mode configuration*/
if ( state == STATE_US_SM )
{
mode = US_MR_USART_MODE_SPI_SLAVE | US_MR_CHRL_8_BIT
| US_MR_CHMODE_NORMAL
| US_SPI_BPMODE_1;
}
/* Enable the peripheral clock in the PMC */
PMC_EnablePeripheral( BOARD_ID_USART ) ;
/* Configure the USART in the desired mode @USART_SPI_CLK bauds*/
USART_Configure( BOARD_USART_BASE, mode, USART_SPI_CLK, BOARD_MCK ) ;
/* enable USART1 interrupt */
NVIC_EnableIRQ( USART1_IRQn ) ;
/* Enable receiver & transmitter */
USART_SetTransmitterEnabled( BOARD_USART_BASE, 1 ) ;
USART_SetReceiverEnabled( BOARD_USART_BASE, 1 ) ;
}
u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int stopbits )
{
unsigned int mode;
AT91S_USART* base = id == 0 ? AT91C_BASE_US0 : AT91C_BASE_US1;
// Setup mode
mode = AT91C_US_USMODE_NORMAL | AT91C_US_CHMODE_NORMAL | AT91C_US_CLKS_CLOCK;
switch( databits )
{
case 5:
mode |= AT91C_US_CHRL_5_BITS;
break;
case 6:
mode |= AT91C_US_CHRL_6_BITS;
break;
case 7:
mode |= AT91C_US_CHRL_7_BITS;
break;
case 8:
mode |= AT91C_US_CHRL_8_BITS;
break;
}
if( parity == PLATFORM_UART_PARITY_EVEN )
mode |= AT91C_US_PAR_EVEN;
else if( parity == PLATFORM_UART_PARITY_ODD )
mode |= AT91C_US_PAR_ODD;
else if( parity == PLATFORM_UART_PARITY_MARK )
mode |= AT91C_US_PAR_MARK;
else if( parity == PLATFORM_UART_PARITY_SPACE )
mode |= AT91C_US_PAR_SPACE;
else
mode |= AT91C_US_PAR_NONE;
if( stopbits == PLATFORM_UART_STOPBITS_1 )
mode |= AT91C_US_NBSTOP_1_BIT;
else if( stopbits == PLATFORM_UART_STOPBITS_1_5 )
mode |= AT91C_US_NBSTOP_15_BIT;
else
mode |= AT91C_US_NBSTOP_2_BIT;
// Configure pins
PIO_Configure(platform_uart_pins[ id ], PIO_LISTSIZE(platform_uart_pins[ id ]));
// Configure the USART in the desired mode @115200 bauds
baud = USART_Configure( base, mode, baud, BOARD_MCK );
// Enable receiver & transmitter
USART_SetTransmitterEnabled(base, 1);
USART_SetReceiverEnabled(base, 1);
// Return actual baud
return baud;
}
/**
* Configure USART to work @ 115200
*/
static void _ConfigureUsart(void)
{
PIO_Configure(pins, PIO_LISTSIZE(pins));
PMC_EnablePeripheral(ID_USART);
USART_DisableIt(BASE_USART, 0xFFFFFFFF);
USART_Configure(BASE_USART,
USART_MODE_ASYNCHRONOUS,
115200,
BOARD_MCK);
USART_SetTransmitterEnabled(BASE_USART, 1);
USART_SetReceiverEnabled(BASE_USART, 1);
NVIC_EnableIRQ(USART2_IRQn);
}
/**
* Configure USART to work @ 115200
*/
static void ConfigureUsart(void)
{
PIO_Configure(pinsUsart, PIO_LISTSIZE(pinsUsart));
PMC_EnablePeripheral(ID_USART);
BASE_USART->US_IDR = 0xFFFFFFFF;
USART_Configure(BASE_USART,
USART_MODE_ASYNCHRONOUS,
115200,
BOARD_MCK);
USART_SetTransmitterEnabled(BASE_USART, 1);
USART_SetReceiverEnabled(BASE_USART, 1);
NVIC_EnableIRQ(IRQn_USART);
}
/* _____GLOBAL FUNCTIONS_____________________________________________________ */
void usart0_init(void)
{
// Clear flag
usart0_tx_finished_flag = FALSE;
// Initialise ring buffers
ring_buffer_init(&usart0_rx_ring_buffer, usart0_rx_buffer, USART0_RX_BUFFER_SIZE);
ring_buffer_init(&usart0_tx_ring_buffer, usart0_tx_buffer, USART0_TX_BUFFER_SIZE);
// Configure PIO pins for USART0 peripheral
PIO_Configure(USART0_Pins, PIO_LISTSIZE(USART0_Pins));
// Disable the interrupt on the interrupt controller
AIC_DisableIT(AT91C_ID_US0);
// Enable USART0 clock
PMC_EnablePeripheral(AT91C_ID_US0);
// Disable all USART0 interrupts
AT91C_BASE_US0->US_IDR = 0xFFFFFFFF;
// Configure USART
USART_Configure(AT91C_BASE_US0,
AT91C_US_USMODE_NORMAL |
AT91C_US_CLKS_CLOCK |
AT91C_US_CHRL_8_BITS |
AT91C_US_PAR_NONE |
AT91C_US_NBSTOP_1_BIT,
115200,
BOARD_MCK);
USART_SetTransmitterEnabled(AT91C_BASE_US0, 1);
USART_SetReceiverEnabled(AT91C_BASE_US0, 1);
// Configure the AIC for USART0 interrupts
AIC_ConfigureIT(AT91C_ID_US0, AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, usart0_interrupt);
// Enable the interrupt on the interrupt controller
AIC_EnableIT(AT91C_ID_US0);
// Enable selected USART0 interrupts
AT91C_BASE_US0->US_IER = AT91C_US_RXRDY |
AT91C_US_RXBRK |
AT91C_US_OVRE |
AT91C_US_FRAME |
AT91C_US_PARE;
}
/*
* See the serial2.h header file.
*/
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
xComPortHandle xReturn = serHANDLE;
extern void ( vUART_ISR )( void );
const Pin xUSART_Pins[] = { BOARD_PIN_USART_RXD, BOARD_PIN_USART_TXD };
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
/* If the queues were created correctly then setup the serial port
hardware. */
if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )
{
portENTER_CRITICAL();
{
/* Enable the peripheral clock in the PMC. */
PMC_EnablePeripheral( BOARD_ID_USART );
/* Configure the USART. */
USART_Configure( BOARD_USART_BASE, AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT, ulWantedBaud, configCPU_CLOCK_HZ );
/* Configure the interrupt. Note the pre-emption priority is set
in bits [8:15] of the priority value passed as the parameter. */
IRQ_ConfigureIT( BOARD_ID_USART, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 8 ), vSerialISR );
IRQ_EnableIT( BOARD_ID_USART );
/* Enable receiver & transmitter. */
USART_SetTransmitterEnabled( BOARD_USART_BASE, pdTRUE );
USART_SetReceiverEnabled( BOARD_USART_BASE, pdTRUE );
/* Configure IO for USART use. */
PIO_Configure( xUSART_Pins, PIO_LISTSIZE( xUSART_Pins ) );
}
portEXIT_CRITICAL();
}
else
{
xReturn = ( xComPortHandle ) 0;
}
/* This demo file only supports a single port but we have to return
something to comply with the standard demo header file. */
return xReturn;
}
/**
* \brief This function initialize the appropriate DMA channel for Rx channel
* of USART
* \param pUsartd Pointer to a UsartDma instance.
* \param pRxCh Pointer to TxChannel configuration
* \returns 0 if the transfer has been started successfully;
* otherwise returns USARTD_ERROR_LOCK is the driver is in use, or
* USARTD_ERROR if the command is not valid.
*/
uint32_t USARTD_EnableRxChannels(UsartDma *pUsartd, UsartChannel *pRxCh)
{
uint32_t Channel;
assert(pRxCh);
/* Init USART Rx Channel. */
pUsartd->pRxChannel = pRxCh;
/* Enables the USART to receive data. */
USART_SetReceiverEnabled (pUsartd->pUsartHw , ENABLE);
/* Allocate a DMA channel for USART0/1 RX. */
Channel = XDMAD_AllocateChannel(pUsartd->pXdmad, pUsartd->usartId,
XDMAD_TRANSFER_MEMORY);
if (Channel == XDMAD_ALLOC_FAILED)
return USARTD_ERROR;
pRxCh->ChNum = Channel;
/* Setup callbacks for USART RX */
if (pUsartd->pRxChannel->callback) {
XDMAD_SetCallback(pUsartd->pXdmad, pRxCh->ChNum,
(XdmadTransferCallback)pRxCh->callback, pRxCh->pArgument);
} else {
XDMAD_SetCallback(pUsartd->pXdmad, pRxCh->ChNum,
(XdmadTransferCallback)USARTD_Rx_Cb, pUsartd);
}
if (XDMAD_PrepareChannel(pUsartd->pXdmad, pRxCh->ChNum))
return USARTD_ERROR;
if (_configureRxDma(pUsartd , pUsartd->pRxChannel))
return USARTD_ERROR_LOCK;
/* Check if DMA IRQ is enable; if not Enable it */
if (!(NVIC_GetActive(XDMAC_IRQn))) {
/* Enable interrupt */
NVIC_EnableIRQ(XDMAC_IRQn);
}
return 0;
}
int UartInit()
{
//CDCDSerialDriver_Initialize();
PIO_Configure(g_UartPins, PIO_LISTSIZE(g_UartPins));
PMC_EnablePeripheral(AT91C_ID_US0);
USART_Configure(AT91C_BASE_US0, USART_MODE_ASYNCHRONOUS, 115200, MCK);
USART_SetReceiverEnabled(AT91C_BASE_US0, 1);
USART_SetTransmitterEnabled(AT91C_BASE_US0, 1);
//DMA_Init(&g_Uart1DMA, AT91C_BASE_PDC_US0);
//SetPitCallback(UartRefresh, 2);
UartRefresh();
while(1){ USART_Write(AT91C_BASE_US0,'a',0);
}
return 1;
}
/*
* See the serial2.h header file.
*/
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
xComPortHandle xReturn = serHANDLE;
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
/* If the queues were created correctly then setup the serial port
hardware. */
if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )
{
PMC_EnablePeripheral( AT91C_ID_US0 );
portENTER_CRITICAL();
{
USART_Configure( serCOM0, ( AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE ), ulWantedBaud, configCPU_CLOCK_HZ );
/* Enable Rx and Tx. */
USART_SetTransmitterEnabled( serCOM0, pdTRUE );
USART_SetReceiverEnabled( serCOM0, pdTRUE );
/* Enable the Rx interrupts. The Tx interrupts are not enabled
until there are characters to be transmitted. */
serCOM0->US_IER = AT91C_US_RXRDY;
/* Enable the interrupts in the AIC. */
AIC_ConfigureIT( AT91C_ID_US0, AT91C_AIC_PRIOR_LOWEST, ( void (*)( void ) ) vSerialISR );
AIC_EnableIT( AT91C_ID_US0 );
}
portEXIT_CRITICAL();
}
else
{
xReturn = ( xComPortHandle ) 0;
}
/* This demo file only supports a single port but we have to return
something to comply with the standard demo header file. */
return xReturn;
}
/**
* \brief USART hardware handshaking configuration
*
* Configures USART in hardware handshaking mode, asynchronous, 8 bits, 1 stop
* bit, no parity, 115200 bauds and enables its transmitter and receiver.
*/
static void _ConfigureUsart( void )
{
uint32_t mode = US_MR_USART_MODE_HW_HANDSHAKING
| US_MR_USCLKS_MCK
| US_MR_CHRL_8_BIT
| US_MR_PAR_NO
| US_MR_NBSTOP_1_BIT
| US_MR_CHMODE_NORMAL ;
/* Enable the peripheral clock in the PMC*/
PMC->PMC_PCER0 = 1 << BOARD_ID_USART ;
/* Configure the USART in the desired mode @115200 bauds*/
USART_Configure( BOARD_USART_BASE, mode, 115200, BOARD_MCK ) ;
/* Configure the RXBUFF interrupt*/
NVIC_EnableIRQ( USART1_IRQn ) ;
/* Enable receiver & transmitter*/
USART_SetTransmitterEnabled( BOARD_USART_BASE, 1 ) ;
USART_SetReceiverEnabled( BOARD_USART_BASE, 1 ) ;
}
/**
* \brief This function disables the appropriate DMA channel for Rx channel of
* USART
* \param pUsartd Pointer to a UsartDma instance.
* \param pRxCh Pointer to TxChannel configuration
* \returns 0 if the transfer has been started successfully;
* otherwise returns USARTD_ERROR_LOCK is the driver is in use, or
* USARTD_ERROR if the command is not valid.
*/
uint32_t USARTD_DisableRxChannels(UsartDma *pUsartd, UsartChannel *pRxCh)
{
assert(pRxCh);
/* Enables the USART to transfer data. */
USART_SetReceiverEnabled (pUsartd->pUsartHw , DISABLE);
XDMAD_StopTransfer(pUsartd->pXdmad, pRxCh->ChNum);
XDMAD_SetCallback(pUsartd->pXdmad, pRxCh->ChNum, NULL, NULL);
/* Free allocated DMA channel for USART TX. */
if (XDMAD_FreeChannel(pUsartd->pXdmad, pRxCh->ChNum) != XDMAD_OK)
return USARTD_ERROR;
if (pRxCh->dmaProgrammingMode == XDMAD_LLI) {
free(pRxCh->pLLIview);
pRxCh->pLLIview = NULL;
}
pRxCh->dmaProgress = 1;
return 0;
}
int platform_init()
{
int i;
unsigned int mode = AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK | AT91C_US_CHRL_8_BITS |
AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT | AT91C_US_CHMODE_NORMAL;
// Enable the peripherals we use in the PMC
PMC_EnablePeripheral(AT91C_ID_US0);
PMC_EnablePeripheral(AT91C_ID_US1);
PMC_EnablePeripheral(AT91C_ID_PIOA);
PMC_EnablePeripheral(AT91C_ID_PIOB);
PMC_EnablePeripheral(AT91C_ID_TC0);
PMC_EnablePeripheral(AT91C_ID_TC1);
PMC_EnablePeripheral(AT91C_ID_TC2);
// Configure pins
PIO_Configure(platform_uart_pins[ 0 ], PIO_LISTSIZE(platform_uart_pins[ 0 ]));
// Configure the USART in the desired mode @115200 bauds
USART_Configure(AT91C_BASE_US0, mode, 115200, BOARD_MCK);
// Enable receiver & transmitter
USART_SetTransmitterEnabled(AT91C_BASE_US0, 1);
USART_SetReceiverEnabled(AT91C_BASE_US0, 1);
// Configure the timers
AT91C_BASE_TCB->TCB_BMR = 7;
for( i = 0; i < 3; i ++ )
TC_Configure( ( AT91S_TC* )timer_base[ i ], AT91C_TC_CLKS_TIMER_DIV5_CLOCK | AT91C_TC_WAVE );
// Set the send/recv functions
std_set_send_func( uart_send );
std_set_get_func( uart_recv );
return PLATFORM_OK;
}
//------------------------------------------------------------------------------
/// Initializes drivers and start the USB <-> Serial bridge.
//------------------------------------------------------------------------------
int main()
{
TRACE_CONFIGURE(DBGU_STANDARD, 115200, BOARD_MCK);
TRACE_INFO("-- USB Device CDC Serial Project %s --\n\r", SOFTPACK_VERSION);
TRACE_INFO("-- %s\n\r", BOARD_NAME);
TRACE_INFO("-- Compiled: %s %s --\n\r", __DATE__, __TIME__);
// If they are present, configure Vbus & Wake-up pins
PIO_InitializeInterrupts(0);
// Configure USART
PIO_Configure(pins, PIO_LISTSIZE(pins));
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0;
AT91C_BASE_US0->US_IDR = 0xFFFFFFFF;
USART_Configure(AT91C_BASE_US0,
USART_MODE_ASYNCHRONOUS,
115200,
BOARD_MCK);
USART_SetTransmitterEnabled(AT91C_BASE_US0, 1);
USART_SetReceiverEnabled(AT91C_BASE_US0, 1);
AIC_ConfigureIT(AT91C_ID_US0, 0, ISR_Usart0);
AIC_EnableIT(AT91C_ID_US0);
// Configure timer 0
AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
AT91C_BASE_TC0->TC_IDR = 0xFFFFFFFF;
AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV5_CLOCK
| AT91C_TC_CPCSTOP
| AT91C_TC_CPCDIS
| AT91C_TC_WAVESEL_UP_AUTO
| AT91C_TC_WAVE;
AT91C_BASE_TC0->TC_RC = 0x00FF;
AT91C_BASE_TC0->TC_IER = AT91C_TC_CPCS;
AIC_ConfigureIT(AT91C_ID_TC0, 0, ISR_Timer0);
AIC_EnableIT(AT91C_ID_TC0);
// BOT driver initialization
CDCDSerialDriver_Initialize();
// connect if needed
VBus_Configure();
// Driver loop
while (1) {
// Device is not configured
if (USBD_GetState() < USBD_STATE_CONFIGURED) {
// Connect pull-up, wait for configuration
USBD_Connect();
while (USBD_GetState() < USBD_STATE_CONFIGURED);
// Start receiving data on the USART
usartCurrentBuffer = 0;
USART_ReadBuffer(AT91C_BASE_US0, usartBuffers[0], DATABUFFERSIZE);
USART_ReadBuffer(AT91C_BASE_US0, usartBuffers[1], DATABUFFERSIZE);
AT91C_BASE_US0->US_IER = AT91C_US_ENDRX
| AT91C_US_FRAME
| AT91C_US_OVER;
AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
// Start receiving data on the USB
CDCDSerialDriver_Read(usbBuffer,
DATABUFFERSIZE,
(TransferCallback) UsbDataReceived,
0);
}
if( USBState == STATE_SUSPEND ) {
TRACE_DEBUG("suspend !\n\r");
LowPowerMode();
USBState = STATE_IDLE;
}
if( USBState == STATE_RESUME ) {
// Return in normal MODE
TRACE_DEBUG("resume !\n\r");
NormalPowerMode();
USBState = STATE_IDLE;
}
}
}
/**
* \brief Configures USART in LON mode
*/
static void _ConfigureUsart( void )
{
/* Initialization for Sending/Receiving A LON Frame */
uint32_t mode;
Usart *pUsart = USART;
/* 1. Write TXEN and RXEN in US_CR to enable both the transmitter and the
receiver. */
/* Enable receiver & transmitter */
USART_SetTransmitterEnabled(pUsart, 1);
USART_SetReceiverEnabled(pUsart, 1);
/* 2. Write USART_MODE in US_MR to select the LON mode configuration. */
/* Enable the peripheral clock in the PMC */
PMC_EnablePeripheral(ID_USART);
mode = US_MR_USART_MODE_LON | US_MR_USCLKS_MCK
| US_MR_CHRL_8_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT
| US_MR_CHMODE_NORMAL
//| US_MR_CHMODE_LOCAL_LOOPBACK //US_MR_CHMODE_NORMAL
| US_MR_MAN;
pUsart->US_CR = US_CR_RSTRX | US_CR_RSTTX
| US_CR_RXDIS | US_CR_TXDIS | US_CR_RSTSTA;
pUsart->US_IDR = 0xFFFFFFFF;
pUsart->US_MR = mode;
/* 3. Write CD and FP in US_BRGR to configure the baud rate. */
USART_SetBaudrate(pUsart, 0, BAUDRATE, BOARD_MCK);
/* 4. Write COMMT, COLDET, TCOL, CDTAIL, RDMNBM and DMAM in US_LONMR to
configure the LON operating mode. */
pUsart->US_LONMR = US_LONMR_COMMT /* LON comm_type = 2 mode */
| US_LONMR_COLDET /* LON collision detection feature enabled */
| US_LONMR_DMAM /* The LON data length register US_LONDL is written by the DMA */
| US_LONMR_LCDS /* LON collision detection source is internal. */
| US_LONMR_EOFS(1);
/* 5. Write BETA2, BETA1TX, BETA1RX, PCYCLE, PSNB, NPS, IDTTX and ITDRX
respectively in US_FIDI, US_LONB1TX, US_LONB1RX, US_TTGR, US_LONPRIO,
US_LONIDTTX and US_LONIDTRX to set the LON network configuration. */
pUsart->US_FIDI = 5; /* LON BETA2 length */
pUsart->US_LONB1TX = 5; /* LON Beta1 Tx */
pUsart->US_LONB1RX = 5; /* LON Beta1 Rx */
pUsart->US_TTGR = US_TTGR_PCYCLE(5); /* package cycle timer value */
pUsart->US_LONPRIO = US_LONPRIO_PSNB(5) /* Number of priority slots */
| US_LONPRIO_NPS(5); /* Node priority slot */
/* Set LON Indeterminate Time after Transmission or Reception
* (comm_type = 1 mode only) */
if (0 == (pUsart->US_LONMR & US_LONMR_COMMT)) {
pUsart->US_IDTTX = US_IDTTX_IDTTX(3);
pUsart->US_IDTRX = US_IDTRX_IDTRX(3);
}
/* (TX) 6. Write TX_PL in US_MAN to select the preamble pattern to use. */
/* (RX) 6. Write RXIDLEV and RX_PL in US_MAN to indicate the receiver line
value and select the preamble pattern to use. */
// preamble pattern
pUsart->US_MAN = US_MAN_TX_PL(5) | US_MAN_TX_PP_ALL_ONE
| US_MAN_RX_PL(5) | US_MAN_RX_PP_ALL_ONE
| US_MAN_ONE | US_MAN_DRIFT;
pUsart->US_LONPR = US_LONPR_LONPL(5);
/* proceed by a software reset of the transmitter and the receiver and
followed by a transmitter/receiver enable to avoid unpredictable behavior */
pUsart->US_CR = US_CR_RSTRX | US_CR_RSTTX;
pUsart->US_CR = US_CR_RXEN | US_CR_TXEN;
}
/**
* \brief Applet main entry. This function decodes received command and executes it.
*
* \param argc always 1
* \param argv Address of the argument area..
*/
int main(int argc, char **argv)
{
struct _Mailbox *pMailbox = (struct _Mailbox *) argv;
uint32_t bytesToWrite, bufferAddr, memoryOffset;
uint32_t l_start, l_end;
uint32_t *pActualStart = NULL;
uint32_t *pActualEnd = NULL;
uint8_t error;
/* Disable watchdog */
WDT_Disable( WDT ) ;
//TRACE_CONFIGURE_ISP(DBGU_STANDARD, 115200, BOARD_MCK);
// ----------------------------------------------------------
// INIT:
// ----------------------------------------------------------
if (pMailbox->command == APPLET_CMD_INIT) {
// Save communication link type
comType = pMailbox->argument.inputInit.comType;
if (comType == DBGU_COM_TYPE){
USART_Configure(UART0, UART_MR_PAR_NONE, 115200, BOARD_MCK);
USART_SetTransmitterEnabled(UART0, 1);
USART_SetReceiverEnabled(UART0, 1);
}
flashBaseAddr = AT91C_IFLASH;
flashBaseAddrInit = AT91C_IFLASH;
flashSize = AT91C_IFLASH_SIZE;
flashPageSize = AT91C_IFLASH_PAGE_SIZE;
flashNbLockBits = AT91C_IFLASH_NB_OF_LOCK_BITS;
flashLockRegionSize = AT91C_IFLASH_LOCK_REGION_SIZE;
TRACE_INFO("-- Internal Flash Applet %s --\n\r", SAM_BA_APPLETS_VERSION);
TRACE_INFO("-- %s\n\r", BOARD_NAME);
TRACE_INFO("-- Compiled: %s %s --\n\r", __DATE__, __TIME__);
// Initialize flash driver
//FLASHD_Initialize(BOARD_MCK);
// flash accesses must be 4 bytes aligned
pMailbox->argument.outputInit.bufferAddress = ((uint32_t) &end);
bufferSize = AT91C_ISRAM_SIZE // sram size
- ( ((uint32_t) &end) - AT91C_ISRAM ) // program size (romcode, code+data)
- STACK_SIZE; // stack size at the end
// integer number of pages can be contained in each buffer
// operation is : buffersize -= bufferSize % flashPageSize
// modulo can be done with a mask since flashpagesize is a power of two integer
bufferSize -= (bufferSize & (flashPageSize - 1));
pMailbox->argument.outputInit.bufferSize = bufferSize;
pMailbox->argument.outputInit.memorySize = flashSize;
pMailbox->argument.outputInit.memoryInfo.lockRegionSize = flashLockRegionSize;
pMailbox->argument.outputInit.memoryInfo.numbersLockBits = flashNbLockBits;
TRACE_INFO("bufferSize : %d bufferAddr: 0x%x \n\r",
pMailbox->argument.outputInit.bufferSize,
(uint32_t) &end );
TRACE_INFO("memorySize : %d lockRegionSize : 0x%x numbersLockBits : 0x%x \n\r",
pMailbox->argument.outputInit.memorySize,
pMailbox->argument.outputInit.memoryInfo.lockRegionSize,
pMailbox->argument.outputInit.memoryInfo.numbersLockBits);
pMailbox->status = APPLET_SUCCESS;
}
// ----------------------------------------------------------
// WRITE:
// ----------------------------------------------------------
else if (pMailbox->command == APPLET_CMD_WRITE) {
memoryOffset = pMailbox->argument.inputWrite.memoryOffset;
bufferAddr = pMailbox->argument.inputWrite.bufferAddr;
bytesToWrite = pMailbox->argument.inputWrite.bufferSize;
TRACE_INFO("WRITE at offset: 0x%x buffer at : 0x%x of: 0x%x Bytes (flash base addr : 0x%x)\n\r",
memoryOffset, bufferAddr, bytesToWrite, flashBaseAddr);
// Check the giving sector have been locked before.
if (FLASHD_IsLocked(flashBaseAddr + memoryOffset, flashBaseAddr + memoryOffset + bytesToWrite) != 0) {
TRACE_INFO("Error page locked\n\r");
pMailbox->argument.outputWrite.bytesWritten = 0;
pMailbox->status = APPLET_PROTECT_FAIL;
goto exit;
}
// Write data
if (FLASHD_Write(flashBaseAddr + memoryOffset, (const void *)bufferAddr, bytesToWrite) != 0) {
TRACE_INFO("Error write operation\n\r");
pMailbox->argument.outputWrite.bytesWritten = 0;
pMailbox->status = APPLET_WRITE_FAIL;
goto exit;
}
TRACE_INFO("Write achieved\n\r");
pMailbox->argument.outputWrite.bytesWritten = bytesToWrite;
pMailbox->status = APPLET_SUCCESS;
}
// ----------------------------------------------------------
// READ:
// ----------------------------------------------------------
else if (pMailbox->command == APPLET_CMD_READ) {
memoryOffset = pMailbox->argument.inputRead.memoryOffset;
bufferAddr = pMailbox->argument.inputRead.bufferAddr;
bufferSize = pMailbox->argument.inputRead.bufferSize;
TRACE_INFO("READ at offset: 0x%x buffer at : 0x%x of: 0x%x Bytes (flash base addr : 0x%x)\n\r",
memoryOffset, bufferAddr, bufferSize, flashBaseAddr);
// read data
memcpy((void *)bufferAddr, (void *)(flashBaseAddr + memoryOffset), bufferSize);
TRACE_INFO("Read achieved\n\r");
pMailbox->argument.outputRead.bytesRead = bufferSize;
pMailbox->status = APPLET_SUCCESS;
}
// ----------------------------------------------------------
// FULL ERASE:
// ----------------------------------------------------------
else if (pMailbox->command == APPLET_CMD_FULL_ERASE) {
TRACE_INFO("FULL ERASE command \n\r");
// Check if at least one page has been locked
if (FLASHD_IsLocked(flashBaseAddr, flashBaseAddr + flashSize) != 0) {
TRACE_INFO("Error page locked \n\r");
pMailbox->status = APPLET_PROTECT_FAIL;
goto exit;
}
// Implement the erase all command
if (FLASHD_Erase(flashBaseAddr) != 0) {
TRACE_INFO("Full erase failed! \n\r");
pMailbox->status = APPLET_ERASE_FAIL;
goto exit;
}
TRACE_INFO("Full erase achieved\n\r");
pMailbox->status = APPLET_SUCCESS;
}
// ----------------------------------------------------------
// LOCK SECTOR:
// ----------------------------------------------------------
else if (pMailbox->command == APPLET_CMD_LOCK) {
TRACE_INFO("LOCK command \n\r");
l_start = (pMailbox->argument.inputLock.sector * flashLockRegionSize) + flashBaseAddr;
l_end = l_start + flashLockRegionSize;
if( FLASHD_Lock(l_start, l_end, pActualStart, pActualEnd) != 0) {
TRACE_INFO("Lock failed! \n\r");
pMailbox->status = APPLET_PROTECT_FAIL;
goto exit;
}
TRACE_INFO("Lock sector achieved\n\r");
pMailbox->status = APPLET_SUCCESS;
}
// ----------------------------------------------------------
// UNLOCK SECTOR:
// ----------------------------------------------------------
else if (pMailbox->command == APPLET_CMD_UNLOCK) {
TRACE_INFO("UNLOCK command \n\r");
l_start = (pMailbox->argument.inputLock.sector * flashLockRegionSize) + flashBaseAddr;
l_end = l_start + flashLockRegionSize;
if( FLASHD_Unlock(l_start, l_end, pActualStart, pActualEnd) != 0) {
TRACE_INFO("Unlock failed! \n\r");
pMailbox->status = APPLET_UNPROTECT_FAIL;
goto exit;
}
TRACE_INFO("Unlock sector achieved\n\r");
pMailbox->status = APPLET_SUCCESS;
}
// ----------------------------------------------------------
// GPNVM :
// ----------------------------------------------------------
else if (pMailbox->command == APPLET_CMD_GPNVM) {
if( pMailbox->argument.inputGPNVM.action == 0) {
TRACE_INFO("DEACTIVATES GPNVM command \n\r");
error = FLASHD_ClearGPNVM(pMailbox->argument.inputGPNVM.bitsOfNVM);
}
else {
TRACE_INFO("ACTIVATES GPNVM command \n\r");
error = FLASHD_SetGPNVM(pMailbox->argument.inputGPNVM.bitsOfNVM);
}
if(error != 0) {
TRACE_INFO("GPNVM failed! \n\r");
pMailbox->status = APPLET_FAIL;
goto exit;
}
TRACE_INFO("GPNVM achieved\n\r");
pMailbox->status = APPLET_SUCCESS;
}
// ----------------------------------------------------------
// READ UNIQUE ID :
// ----------------------------------------------------------
else if (pMailbox->command == APPLET_CMD_READ_UNIQUE_ID) {
TRACE_INFO("READ UNIQUE ID command \n\r");
if (FLASHD_ReadUniqueID ((pMailbox->argument.inputReadUniqueID.bufferAddr)) != 0) {
TRACE_INFO("Read Unique ID failed! \n\r");
pMailbox->status = APPLET_FAIL;
goto exit;
}
TRACE_INFO("Read Unique ID achieved\n\r");
pMailbox->status = APPLET_SUCCESS;
}
exit:
// Acknowledge the end of command
TRACE_INFO("\tEnd of Applet %x %x.\n\r", pMailbox->command, pMailbox->status);
// Notify the host application of the end of the command processing
pMailbox->command = ~(pMailbox->command);
if (comType == DBGU_COM_TYPE) {
UART_PutChar(0x6);
}
return 0;
}
////////////////////////////////////////////////////////////////////////////////
// Konfiguracja USART0 w trybie DMA (DMA tylko do nadawania)
// Odbi�r danych za pomoc� przerwania
////////////////////////////////////////////////////////////////////////////////
void UART0_DMA_Configure(unsigned long baudrate) {
float podzielnik_float;
int calkowity, ulamkowy;
unsigned int mode = AT91C_US_USMODE_NORMAL | /* Normal Mode */
AT91C_US_CLKS_CLOCK | /* Clock = MCK */
AT91C_US_CHRL_8_BITS | /* 8-bit Data */
AT91C_US_PAR_NONE | /* No Parity */
AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */
//W��czenie zegara dla UART0
PMC_EnablePeripheral(AT91C_ID_US0);
// AT91F_PMC_EnablePeriphClock ( AT91C_BASE_PMC, 1 << AT91C_ID_US0 );
USART_Configure(AT91C_BASE_US0, mode, baudrate, BOARD_MCK);
//wylaczenie przyjmowania przerwan
AT91C_BASE_US0->US_IDR = 0xFFFFFFFF;
USART_SetReceiverEnabled(AT91C_BASE_US0, 0);
USART_SetTransmitterEnabled(AT91C_BASE_US0, 0);
// //reset portu
// AT91C_BASE_US0->US_CR = AT91C_US_RSTRX | /* Reset Receiver */
// AT91C_US_RSTTX | /* Reset Transmitter */
// AT91C_US_RXDIS | /* Receiver Disable */
// AT91C_US_TXDIS; /* Transmitter Disable */
//wylaczenie DMA
PDC_Disable(AT91C_BASE_PDC_US0);
// //konfiguracja USART0
// AT91C_BASE_US0->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */
// AT91C_US_CLKS_CLOCK | /* Clock = MCK */
// AT91C_US_CHRL_8_BITS | /* 8-bit Data */
// AT91C_US_PAR_NONE | /* No Parity */
// AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */
//predkosc
//AT91C_BASE_US0->US_BRGR = (MCK/16/baudrate);
//wyliczenie podzielnikow zegara MCLK
podzielnik_float = ((float) MCK / 16.0 / (float) baudrate);
calkowity = podzielnik_float;
podzielnik_float = (podzielnik_float - calkowity) * 8;
ulamkowy = podzielnik_float;
AT91C_BASE_US0->US_BRGR = (calkowity) | (ulamkowy << 16); /* podzielnik calkowity + podzielnik ulamkowy */
//konfiguracja przerwania
AIC_ConfigureIT(AT91C_ID_US0, 0x3 | AT91C_AIC_SRCTYPE_HIGH_LEVEL,
UART0_DMA_irq_handler);
// AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC, AT91C_ID_US0, 0x3, AT91C_AIC_SRCTYPE_HIGH_LEVEL, UART0_DMA_irq_handler);
AIC_EnableIT(AT91C_ID_US0);
// AT91F_AIC_EnableIt (AT91C_BASE_AIC, AT91C_ID_US0);
//w��czenie USART0
USART_SetReceiverEnabled(AT91C_BASE_US0, 1);
USART_SetTransmitterEnabled(AT91C_BASE_US0, 1);
// AT91C_BASE_US0->US_CR = AT91C_US_RXEN | /* Receiver Enable */
// AT91C_US_TXEN; /* Transmitter Enable */
//wlaczenie DMA (nadawanie)
PDC_Enable(AT91C_BASE_PDC_US0);
//konfiguracja wyprowadzen
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, (AT91C_PA5_RXD0 | AT91C_PA6_TXD0), 0);
//wlaczenie przerwania od odbiornika
AT91C_BASE_US0->US_IER = (0x1 << 0); //RXRDY
}