int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high, u32 init_val_low) { u32 temp; /* Parameter checking */ if (chan >= MV_XOR_MAX_CHAN) return MV_BAD_PARAM; if (MV_ACTIVE == mv_xor_state_get(chan)) return MV_BUSY; if ((block_size < XEXBSR_BLOCK_SIZE_MIN_VALUE) || (block_size > XEXBSR_BLOCK_SIZE_MAX_VALUE)) return MV_BAD_PARAM; /* set the operation mode to Memory Init */ temp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); temp &= ~XEXCR_OPERATION_MODE_MASK; temp |= XEXCR_OPERATION_MODE_MEM_INIT; reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp); /* * update the start_ptr field in XOR Engine [0..1] Destination Pointer * Register */ reg_write(XOR_DST_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)), start_ptr); /* * update the Block_size field in the XOR Engine[0..1] Block Size * Registers */ reg_write(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)), block_size); /* * update the field Init_val_l in the XOR Engine Initial Value Register * Low (XEIVRL) */ reg_write(XOR_INIT_VAL_LOW_REG(XOR_UNIT(chan)), init_val_low); /* * update the field Init_val_h in the XOR Engine Initial Value Register * High (XEIVRH) */ reg_write(XOR_INIT_VAL_HIGH_REG(XOR_UNIT(chan)), init_val_high); /* start transfer */ reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), XEXACTR_XESTART_MASK); return MV_OK; }
/******************************************************************************* * mvXorMemInit - * * DESCRIPTION: * * * INPUT: * None. * * OUTPUT: * None. * * RETURN: * * *******************************************************************************/ MV_STATUS mvXorMemInit(MV_U32 chan, MV_U32 startPtr, MV_U32 blockSize, MV_U32 initValHigh, MV_U32 initValLow) { MV_U32 temp; /* Parameter checking */ if (chan >= MV_XOR_MAX_CHAN) { mvOsPrintf("%s: ERR. Invalid chan num %d\n", __func__, chan); return MV_BAD_PARAM; } if (MV_ACTIVE == mvXorStateGet(chan)) { mvOsPrintf("%s: ERR. Channel is already active\n", __func__); return MV_BUSY; } if ((blockSize < XEXBSR_BLOCK_SIZE_MIN_VALUE) || (blockSize > XEXBSR_BLOCK_SIZE_MAX_VALUE)) { mvOsPrintf("%s: ERR. Block size must be between %d to %ul\n", __func__, XEXBSR_BLOCK_SIZE_MIN_VALUE, XEXBSR_BLOCK_SIZE_MAX_VALUE); return MV_BAD_PARAM; } /* set the operation mode to Memory Init */ temp = MV_REG_READ(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); temp &= ~XEXCR_OPERATION_MODE_MASK; temp |= XEXCR_OPERATION_MODE_MEM_INIT; MV_REG_WRITE(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp); /* update the startPtr field in XOR Engine [0..1] Destination Pointer Register (XExDPR0) */ MV_REG_WRITE(XOR_DST_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)), startPtr); /* update the BlockSize field in the XOR Engine[0..1] Block Size Registers (XExBSR) */ MV_REG_WRITE(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)), blockSize); /* update the field InitValL in the XOR Engine Initial Value Register Low (XEIVRL) */ MV_REG_WRITE(XOR_INIT_VAL_LOW_REG(XOR_UNIT(chan)), initValLow); /* update the field InitValH in the XOR Engine Initial Value Register High (XEIVRH) */ MV_REG_WRITE(XOR_INIT_VAL_HIGH_REG(XOR_UNIT(chan)), initValHigh); /* start transfer */ MV_REG_BIT_SET(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), XEXACTR_XESTART_MASK); return MV_OK; }
/******************************************************************************* * mvXorMemInit - * * DESCRIPTION: * * * INPUT: * None. * * OUTPUT: * None. * * RETURN: * * *******************************************************************************/ GT_STATUS mvXorMemInit(GT_U32 chan, GT_U32 startPtr, GT_U32 blockSize, GT_U32 initValHigh, GT_U32 initValLow) { GT_U32 temp; /* Parameter checking */ if (chan >= MV_XOR_MAX_CHAN) { return GT_BAD_PARAM; } if (MV_ACTIVE == mvXorStateGet(chan)) { return GT_BUSY; } if ((blockSize < XEXBSR_BLOCK_SIZE_MIN_VALUE) || (blockSize > XEXBSR_BLOCK_SIZE_MAX_VALUE)) { return GT_BAD_PARAM; } /* set the operation mode to Memory Init */ temp = MV_REG_READ(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); temp &= ~XEXCR_OPERATION_MODE_MASK; temp |= XEXCR_OPERATION_MODE_MEM_INIT; MV_REG_WRITE(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp); /* update the startPtr field in XOR Engine [0..1] Destination Pointer Register (XExDPR0) */ MV_REG_WRITE(XOR_DST_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)), startPtr); /* update the BlockSize field in the XOR Engine[0..1] Block Size Registers (XExBSR) */ MV_REG_WRITE(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)), blockSize); /* update the field InitValL in the XOR Engine Initial Value Register Low (XEIVRL) */ MV_REG_WRITE(XOR_INIT_VAL_LOW_REG(XOR_UNIT(chan)), initValLow); /* update the field InitValH in the XOR Engine Initial Value Register High (XEIVRH) */ MV_REG_WRITE(XOR_INIT_VAL_HIGH_REG(XOR_UNIT(chan)), initValHigh); /* start transfer */ MV_REG_BIT_SET(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), XEXACTR_XESTART_MASK); return GT_OK; }
/******************************************************************************* * mvXorEccClean - . * * DESCRIPTION: * * * INPUT: * destPtr - * * OUTPUT: * None. * * RETURN: * *******************************************************************************/ MV_STATUS mvXorEccClean(MV_U32 chan, MV_XOR_ECC *pXorEccConfig) { MV_U32 tClkCycles; MV_U32 temp; /* Parameter checking */ if (chan >= MV_XOR_MAX_CHAN) { DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __func__, chan)); return MV_BAD_PARAM; } if (NULL == pXorEccConfig) { DB(mvOsPrintf("%s: ERR. pXorEccConfig is NULL pointer\n", __func__)); return MV_BAD_PTR; } if (MV_ACTIVE == mvXorStateGet(chan)) { DB(mvOsPrintf("%s: ERR. Channel is already active\n", __func__)); return MV_BUSY; } if ((pXorEccConfig->sectorSize < XETMCR_SECTION_SIZE_MIN_VALUE) || (pXorEccConfig->sectorSize > XETMCR_SECTION_SIZE_MAX_VALUE)) { DB(mvOsPrintf("%s: ERR. sectorSize must be between %d to %d\n", __func__, XETMCR_SECTION_SIZE_MIN_VALUE, XETMCR_SECTION_SIZE_MAX_VALUE)); return MV_BAD_PARAM; } if ((pXorEccConfig->blockSize < XEXBSR_BLOCK_SIZE_MIN_VALUE) || (pXorEccConfig->blockSize > XEXBSR_BLOCK_SIZE_MAX_VALUE)) { DB(mvOsPrintf("%s: ERR. Block size must be between %d to %ul\n", __func__, XEXBSR_BLOCK_SIZE_MIN_VALUE, XEXBSR_BLOCK_SIZE_MAX_VALUE)); return MV_BAD_PARAM; } if (0x0 == pXorEccConfig->destPtr) { DB(mvOsPrintf("%s: ERR. destPtr is NULL pointer\n", __func__)); return MV_BAD_PARAM; } /* set the operation mode to ECC */ temp = MV_REG_READ(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); temp &= ~XEXCR_OPERATION_MODE_MASK; temp |= XEXCR_OPERATION_MODE_ECC; MV_REG_WRITE(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp); /* update the TimerEn bit in the XOR Engine Timer Mode Control Register (XETMCR) */ if (pXorEccConfig->periodicEnable) MV_REG_BIT_SET(XOR_TIMER_MODE_CTRL_REG(XOR_UNIT(chan)), XETMCR_TIMER_EN_MASK); else MV_REG_BIT_RESET(XOR_TIMER_MODE_CTRL_REG(XOR_UNIT(chan)), XETMCR_TIMER_EN_MASK); /* update the SectionSizeCtrl bit in the XOR Engine Timer Mode Control Register (XETMCR) */ temp = MV_REG_READ(XOR_TIMER_MODE_CTRL_REG(XOR_UNIT(chan))); temp &= ~XETMCR_SECTION_SIZE_CTRL_MASK; temp |= (pXorEccConfig->sectorSize << XETMCR_SECTION_SIZE_CTRL_OFFS); MV_REG_WRITE(XOR_TIMER_MODE_CTRL_REG(XOR_UNIT(chan)), temp); /* update the DstPtr field in the XOR Engine [0..1] Destination Pointer Register (XExDPR0) */ MV_REG_WRITE(XOR_DST_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)), pXorEccConfig->destPtr); /* update the BlockSize field in the XOR Engine[0..1] Block Size Registers (XExBSR) */ MV_REG_WRITE(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)), pXorEccConfig->blockSize); /* update the XOR Engine Timer Mode Initial Value Register (XETMIVR) */ tClkCycles = pXorEccConfig->tClkTicks; MV_REG_WRITE(XOR_TIMER_MODE_INIT_VAL_REG(XOR_UNIT(chan)), tClkCycles); /* start transfer */ MV_REG_BIT_SET(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), XEXACTR_XESTART_MASK); return MV_OK; }