Пример #1
0
/******************************************************************************
* @brief Main function.
*
* @return Always returns 0.
******************************************************************************/
int main() 
{

   Xil_ICacheEnable();
   Xil_DCacheEnable();

   I2C_Init_axi(IIC_BASEADDR, AD7991IICAddr);

   unsigned char rxBuffer[2] = {0x00, 0x00};

   // Configure AD7991
   /*
    	Use external reference (2V, selected from Jumper JP1)
    	Read all 3 Channels
    	4th Channel used as reference
    */
   AD7991_Config(0,1,1,1,1,0,0,0);

	   // Print the value read on one of the channels
	   AD7991_Print(20,VREF);

   Xil_DCacheDisable();
   Xil_ICacheDisable();

   return 0;
}
Пример #2
0
int main()
{
	int ret = XST_SUCCESS;
	u32 n, wdata;

	Xil_DCacheDisable();
	Xil_ICacheDisable();

	/* walking 1 */
	for(n = 0; n < 28; n++) {
		wdata = 1 << n;
		gpio_write(wdata);
		gpio_wait();
		if (gpio_read(n, wdata) != XST_SUCCESS)
			ret = XST_FAILURE;
	}

	/* walking 0 */
	for(n = 0; n < 28; n++) {
		wdata = 1 << n;
		wdata = ~wdata;
		gpio_write(wdata);
		gpio_wait();
		if (gpio_read(n, wdata) != XST_SUCCESS)
			ret = XST_FAILURE;
	}

	return ret;
}
Пример #3
0
/***************************************************************************//**
 * @brief Main function.
 *
 * @return Returns 0.
*******************************************************************************/
int main()
{
	UINT32 StartCount;

	MajorRev     = 1;
	MinorRev     = 1;
	RcRev        = 1;
	DriverEnable = TRUE;
	LastEnable   = FALSE;

	Xil_ICacheEnable();
	Xil_DCacheEnable();

#ifdef XPAR_AXI_IIC_0_BASEADDR
	HAL_PlatformInit(XPAR_AXI_IIC_0_BASEADDR,	/* Perform any required platform init */
					 XPAR_SCUTIMER_DEVICE_ID,	/* including hardware reset to HDMI devices */
					 XPAR_SCUGIC_SINGLE_DEVICE_ID,
					 XPAR_SCUTIMER_INTR);
#else
	HAL_PlatformInit(XPAR_AXI_IIC_MAIN_BASEADDR,	/* Perform any required platform init */
					 XPAR_SCUTIMER_DEVICE_ID,	/* including hardware reset to HDMI devices */
					 XPAR_SCUGIC_SINGLE_DEVICE_ID,
					 XPAR_SCUTIMER_INTR);
#endif

	Xil_ExceptionEnable();

	SetVideoResolution(RESOLUTION_640x480);
	InitHdmiAudioPcore();

	APP_PrintRevisions();       /* Display S/W and H/W revisions */

	DBG_MSG("To change the video resolution press:\r\n");
	DBG_MSG("  '0' - 640x480;  '1' - 800x600;  '2' - 1024x768; '3' - 1280x720 \r\n");
	DBG_MSG("  '4' - 1360x768; '5' - 1600x900; '6' - 1920x1080.\r\n");

	ADIAPI_TransmitterInit();   /* Initialize ADI repeater software and h/w */

	ADIAPI_TransmitterSetPowerMode(REP_POWER_UP);

	StartCount = HAL_GetCurrentMsCount();

	while(1)
	{
		if (ATV_GetElapsedMs (StartCount, NULL) >= HDMI_CALL_INTERVAL_MS)
		{
			StartCount = HAL_GetCurrentMsCount();
			if (APP_DriverEnabled())
			{
				ADIAPI_TransmitterMain();
			}
		}
		APP_ChangeResolution();
	}

	Xil_DCacheDisable();
	Xil_ICacheDisable();

	return(0);
}
Пример #4
0
/***************************************************************************//**
 * @brief main
*******************************************************************************/
int main(void)
{
	Xil_ICacheEnable();
	Xil_DCacheEnable();

	gpio_init(GPIO_DEVICE_ID);
	gpio_direction(54 + 46, 1);
	spi_init(SPI_DEVICE_ID, 1, 0);

	adc_init();
	dac_init(DATA_SEL_DDS);

	ad9361_phy = ad9361_init(&default_init_param);

	ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
	ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);

#ifdef DAC_DMA
	dac_init(DATA_SEL_DMA);
#else
	dac_init(DATA_SEL_DDS);
#endif

#ifdef CAPTURE_SCRIPT
	adc_capture(16384, ADC_DDR_BASEADDR);
	while(1);
#endif
	get_help(NULL, 0);

	while(1)
	{
		console_get_command(received_cmd);
		invalid_cmd = 0;
		for(cmd = 0; cmd < cmd_no; cmd++)
		{
			param_no = 0;
			cmd_type = console_check_commands(received_cmd, cmd_list[cmd].name,
											  param, &param_no);
			if(cmd_type == UNKNOWN_CMD)
			{
				invalid_cmd++;
			}
			else
			{
				cmd_list[cmd].function(param, param_no);
			}
		}
		if(invalid_cmd == cmd_no)
		{
			console_print("Invalid command!\n");
		}
	}

	Xil_DCacheDisable();
	Xil_ICacheDisable();

	return 0;
}
Пример #5
0
/***************************************************************************//**
 * @brief Main function.
 *
 * @return Returns 0.
*******************************************************************************/
int main()
{
	UINT32 StartCount;

	MajorRev     = 1;
	MinorRev     = 1;
	RcRev        = 1;
	DriverEnable = TRUE;
	LastEnable   = FALSE;

	Xil_ICacheEnable();
	Xil_DCacheEnable();

	HAL_PlatformInit(XPAR_AXI_IIC_0_BASEADDR,	/* Perform any required platform init */
					 XPAR_SCUTIMER_DEVICE_ID,	/* including hardware reset to HDMI devices */
					 XPAR_SCUGIC_SINGLE_DEVICE_ID,
					 XPAR_SCUTIMER_INTR);

	Xil_ExceptionEnable();

	/* Set the default values for 1080P 60Hz */
	CLKGEN_SetRate(148500000, 200000000);
	InitHdmiVideoPcore(1920,
					   1080,
					   280,
					   45,
					   44,
					   5,
					   88,
					   4);
	InitHdmiAudioPcore();

	APP_PrintRevisions();       /* Display S/W and H/W revisions */

	ADIAPI_TransmitterInit();   /* Initialize ADI repeater software and h/w */

	ADIAPI_TransmitterSetPowerMode(REP_POWER_UP);

	StartCount = HAL_GetCurrentMsCount();

	while(1)
	{
		if (ATV_GetElapsedMs (StartCount, NULL) >= HDMI_CALL_INTERVAL_MS)
		{
			StartCount = HAL_GetCurrentMsCount();
			if (APP_DriverEnabled())
			{
				ADIAPI_TransmitterMain();
			}
		}
	}

	Xil_DCacheDisable();
	Xil_ICacheDisable();

	return(0);
}
Пример #6
0
/***************************************************************************//**
 * @brief Main function.
 *
 * @return 0.
*******************************************************************************/
int main(){

    uint32_t mode;

    Xil_ICacheEnable();
    Xil_DCacheEnable();

    /* AD9467 Setup. */
    ad9467_setup(SPI_DEVICE_ID, 0);

    /* AD9517 Setup. */
    ad9517_setup(SPI_DEVICE_ID, 1);    // Initialize device.
    ad9517_power_mode(3, 0);                     // Set channel 3 for normal operation
    ad9517_frequency(3, 250000000);              // Set the channel 3 frequency to 250Mhz
    ad9517_update();                             // Update registers

    /* Read the device ID for AD9467 and AD9517. */
    xil_printf("\n\r********************************************************************\r\n");
    xil_printf("  ADI AD9467-FMC-EBZ Reference Design\n\r");
    xil_printf("  AD9467 CHIP ID: 0x%02x\n\r", ad9467_read(AD9467_REG_CHIP_ID));
    xil_printf("  AD9467 CHIP GRADE: 0x%02x\n\r", ad9467_read(AD9467_REG_CHIP_GRADE));
    xil_printf("  AD9517 CHIP ID: 0x%02x", ad9517_read(AD9517_REG_PART_ID));
    xil_printf("\n\r********************************************************************\r\n");

    /* AD9467 test. */
    adc_setup(0);

    for (mode = MIDSCALE; mode <= ONE_ZERO_TOGGLE; mode++)        // Data pattern checks
    {
        adc_test(mode, OFFSET_BINARY);       // Data format is offset binary
        adc_test(mode, TWOS_COMPLEMENT);     // Data format is twos complement
    }
    xil_printf("Testing done.\n\r");
    /* AD9467 Setup for data acquisition */
    ad9467_output_invert(0);    // Output invert Off
    ad9467_transfer();          // Synchronously update registers
    ad9467_output_format(0);    // Offset binary
    ad9467_transfer();          // Synchronously update registers
    ad9467_reset_PN9(0);        // Clear PN9 bit
    ad9467_transfer();          // Synchronously update registers
    ad9467_reset_PN23(0);       // Clear PN23 bit
    ad9467_transfer();          // Synchronously update registers
    ad9467_test_mode(0);        // Test mode Off
    ad9467_transfer();          // Synchronously update registers

    xil_printf("Start capturing data...\n\r");

    while(1)
    {
        adc_capture(1024, DDR_BASEADDR);
    }

    Xil_DCacheDisable();
    Xil_ICacheDisable();

    return 0;
}
Пример #7
0
void cleanup_platform()
{
#if __MICROBLAZE__ || __PPC__
        disable_caches();
#endif
#ifdef __arm__
        Xil_ICacheDisable();
        Xil_DCacheDisable();
#endif
}
Пример #8
0
//------------------------------------------------------------------------------
int main() 
{
  Xil_ICacheEnable();
  Xil_DCacheEnable();

  while(1){ main_loop(); }

  Xil_DCacheDisable();
  Xil_ICacheDisable();
  return 0;
}
Пример #9
0
void
disable_caches()
{
#ifdef __MICROBLAZE__
#ifdef XPAR_MICROBLAZE_USE_DCACHE
    Xil_DCacheDisable();
#endif
#ifdef XPAR_MICROBLAZE_USE_ICACHE
    Xil_ICacheDisable();
#endif
#endif
}
Пример #10
0
int main() 
{
   static XIntc intc;
   Xil_ICacheEnable();
   Xil_DCacheEnable();
   print("---Entering main---\n\r");
   

   //XIntc_DeviceInterruptHandler(XPAR_INTC_0_DEVICE_ID);
   //print (XPAR_INTC_0_DEVICE_ID);


   {
      int status;
      
      print("\r\n Running IntcSelfTestExample() for axi_intc_0...\r\n");
      
      status = IntcSelfTestExample(XPAR_AXI_INTC_0_DEVICE_ID);
      
      if (status == 0) {
         print("IntcSelfTestExample PASSED\r\n");
      }
      else {
         print("IntcSelfTestExample FAILED\r\n");
      }
   } 
	
   {
       int Status;

       Status = IntcInterruptSetup(&intc, XPAR_AXI_INTC_0_DEVICE_ID);
       if (Status == 0) {
          print("Intc Interrupt Setup PASSED\r\n");
       } 
       else {
         print("Intc Interrupt Setup FAILED\r\n");
      } 
   }
   
   /*
    * Peripheral SelfTest will not be run for axi_uartlite_0
    * because it has been selected as the STDOUT device
    */

   print("---Exiting main---\n\r");
   Xil_DCacheDisable();
   Xil_ICacheDisable();
   return 0;
}
int main (void) {


   /*
    * Enable and initialize cache
    */
   #if XPAR_MICROBLAZE_0_USE_ICACHE
      Xil_ICacheInvalidate();
      Xil_ICacheEnable();
   #endif

   #if XPAR_MICROBLAZE_0_USE_DCACHE
      Xil_DCacheInvalidate();
       Xil_DCacheEnable();
   #endif

   print("-- Entering main() --\r\n");

   /* 
    * MemoryTest routine will not be run for the memory at 
    * 0x84c00000 (FLASH_2Mx16)
    * because it is a read-only memory
    */


   /* 
    * MemoryTest routine will not be run for the memory at 
    * 0x00000000 (dlmb_cntlr)
    * because it is being used to hold a part of this application program
    */

   /*
    * Disable cache and reinitialize it so that other
    * applications can be run with no problems
    */
   #if XPAR_MICROBLAZE_0_USE_DCACHE
      Xil_DCacheDisable();
      Xil_DCacheInvalidate();
   #endif

   #if XPAR_MICROBLAZE_0_USE_ICACHE
      Xil_ICacheDisable();
      Xil_ICacheInvalidate();
   #endif


   print("-- Exiting main() --\r\n");
   return 0;
}
Пример #12
0
/***************************************************************************//**
 * @brief Main function.
 *
 * @return 0.
*******************************************************************************/
int main(){

	u32 mode;

	Xil_ICacheEnable();
    Xil_DCacheEnable();

    /* AD9467 Setup. */
    ad9467_setup(XPAR_AXI_SPI_0_BASEADDR, 1);

	/* AD9517 Setup. */
	ad9517_setup(XPAR_AXI_SPI_0_BASEADDR, 2);	// Initialize device.
	ad9517_power_mode(3, 0);					// Set channel 3 for normal operation
	ad9517_frequency(3, 250000000); 			// Set the channel 3 frequency to 250Mhz
	ad9517_update();							// Update registers

	/* Read the device ID for AD9467 and AD9517. */
	xil_printf("AD9467[REG_CHIP_ID]: %02x\n\r",
			   ad9467_read(AD9467_REG_CHIP_ID));
	xil_printf("AD9467[REG_CHIP_GRADE]: %02x\n\r",
			    ad9467_read(AD9467_REG_CHIP_GRADE));
	xil_printf("AD9517[REG_PART_ID]: %02x\n\r",
			    ad9517_read(AD9517_REG_PART_ID));

	/* AD9467 test. */
	adc_setup(0);
	for (mode = 0x01; mode <= 0x07; mode++)		// Data pattern checks
	{
		adc_test(mode, 0x0);    // Data format is offset binary
		adc_test(mode, 0x1);    // Data format is twos complement
	}
	ad9467_output_invert(0);    // Output invert Off
	ad9467_output_format(0);    // Offset binary
	ad9467_reset_PN9(0);        // Clear PN9 bit
	ad9467_reset_PN23(0);       // Clear PN23 bit
	ad9467_test_mode(0);        // Test mode Off
	ad9467_transfer();          // Synchronously update registers

	xil_printf("done\n\r");

	Xil_DCacheDisable();
	Xil_ICacheDisable();

	return 0;
}
Пример #13
0
/**
* @brief    Disable MPU for Cortex R5 processors. This function invalidates I
*           cache and flush the D Caches, and then disabes the MPU.
*
* @param	None.
*
* @return	None.
*
******************************************************************************/
void Xil_DisableMPU(void)
{
	u32 CtrlReg, Reg;
	s32 DCacheStatus=0, ICacheStatus=0;
	/* enable caches only if they are disabled */

#if defined (__GNUC__)
	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
#elif defined (__ICCARM__)
	mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
#endif
	if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) {
		DCacheStatus=1;
	}
	if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) {
		ICacheStatus=1;
	}

	if(DCacheStatus != 0) {
		Xil_DCacheDisable();
	}
	if(ICacheStatus != 0){
		Xil_ICacheDisable();
	}

	mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
#if defined (__GNUC__)
	Reg = mfcp(XREG_CP15_SYS_CONTROL);
#elif defined (__ICCARM__)
	mfcp(XREG_CP15_SYS_CONTROL,Reg);
#endif
	Reg &= ~(0x00000001U);
	dsb();
	mtcp(XREG_CP15_SYS_CONTROL, Reg);
	isb();
	/* enable caches only if they are disabled in routine*/
	if(DCacheStatus != 0) {
		Xil_DCacheEnable();
	}
	if(ICacheStatus != 0) {
		Xil_ICacheEnable();
	}
}
Пример #14
0
void platform_cache_disable() {
		Xil_DCacheDisable();
		Xil_ICacheDisable();
}
Пример #15
0
/* Program main loop. */
int main()
{
    int32_t ret;
    int32_t mode = 0;
    float retGain;
    uint64_t retFreqRx;
    uint64_t retFreqTx;
    int32_t fmcSel;
    int32_t i;
    int32_t valArray[17];
    XCOMM_Version boardVersion;
    XCOMM_DefaultInit defInit = {FMC_LPC,		//fmcPort
    							 XILINX_ML605,	//carrierBoard
                                 100000000,		//adcSamplingRate
                                 122880000,		//dacSamplingRate
								 10000,			//rxGain1000
								 2400000000ull, //rxFrequency
								 2400000000ull};//txFrequency

    Xil_ICacheEnable();
    Xil_DCacheEnable();

    xil_printf("Running XCOMM Test Program\n\r");

    if(defInit.carrierBoard == XILINX_ZC702)
    {
    	fmcSel = (defInit.fmcPort == FMC_LPC ? IICSEL_B0LPC_PS7 : IICSEL_B1HPC_PS7);
    }
    else
    {
        if(defInit.carrierBoard == XILINX_ZC706)
        {
        	fmcSel = (defInit.fmcPort == FMC_LPC ? IICSEL_B0LPC_PS7_ZC706 :
        										   IICSEL_B1HPC_PS7_ZC706);
        }
        else
        {
        	fmcSel = (defInit.fmcPort == FMC_LPC ? IICSEL_B0LPC_AXI : IICSEL_B1HPC_AXI);
        }
    }

    xil_printf("\n\rInitializing XCOMM I2C...\n\r");
    ret = XCOMM_InitI2C(&defInit);
	if(ret < 0)
	{
		xil_printf("XCOMM Init I2C Failed!\n\r");
		return 0;
	}
	else
	{
		xil_printf("XCOMM Init I2C OK!\n\r");
	}

    xil_printf("\n\rGetting XCOMM Revision...\n\r");
    boardVersion = XCOMM_GetBoardVersion(XCOMM_ReadMode_FromHW);
    if(boardVersion.error == -1)
    {
    	xil_printf("\n\rGetting XCOMM Revision Failed!\n\r");
    }
    else
    {
    	xil_printf("Board Version: %s\n\r", boardVersion.value);
    }

    xil_printf("\n\rInitializing XCOMM Components...\n\r");
    ret = XCOMM_Init(&defInit);
	if(ret < 0)
	{
		xil_printf("XCOMM Init Failed!\n\r");
		return 0;
	}
	else
	{
		xil_printf("XCOMM Init OK!\n\r");
	}

	xil_printf("\n\rInitializing the Rx path...\n\r");
	ret = XCOMM_InitRx(&defInit);
	if(ret < 0)
	{
		xil_printf("XCOMM Rx Init Failed!\n\r");
		return 0;
	}
	else
	{
		xil_printf("XCOMM Rx Init OK!\n\r");
	}

	xil_printf("\n\rInitializing the Tx path...\n\r");
	ret = XCOMM_InitTx(&defInit);
	if(ret < 0)
	{
		xil_printf("XCOMM Tx Init Failed!\n\r");
		return 0;
	}
	else
	{
		xil_printf("XCOMM Tx Init OK!\n\r");
	}

	xil_printf("\n\rADC sampling rate [Hz]: ");
	ret = XCOMM_GetAdcSamplingRate(XCOMM_ReadMode_FromHW);
	xil_printf("%d \n\r", ret);

	xil_printf("\n\rDAC sampling rate [Hz]: ");
	ret = XCOMM_GetDacSamplingRate(XCOMM_ReadMode_FromHW);
	xil_printf("%d \n\r", ret);

	xil_printf("\n\rDAC available interpolation frequencies [Hz]: ");
	XCOMM_GetDacAvailableInterpolationFreq(valArray);
	i = 0;
	while((valArray[i] != 0) && (i < 5))
	{
		xil_printf("%d ", valArray[i]);
		i++;
	}
	xil_printf("\n\r");

	xil_printf("\n\rDAC available center shift frequencies [Hz]: ");
	XCOMM_GetDacAvailableCenterShiftFreq(valArray);
	i = 0;
	while((valArray[i] != -1) && (i < 17))
	{
		xil_printf("%d ", valArray[i]);
		i++;
	}
	xil_printf("\n\r");

    xil_printf("\n\rTesting the ADC communication... \n\r");
    XCOMM_SetAdcTestMode(0x01, XCOMM_AdcChannel_All);
    adc_capture(fmcSel, 1024, DDR_BASEADDR);

	for (mode = 0x1; mode <= 0x7; mode++)
	{
		XCOMM_SetAdcTestMode(mode, XCOMM_AdcChannel_All);
		adc_test(fmcSel, mode, 0x1);
	}
    xil_printf("ADC test complete.\n\r");

    xil_printf("\n\rTesting the DAC communication... \n\r");
    dac_test(fmcSel);
    xil_printf("DAC test complete.\n\r");

	xil_printf("\n\rSetting the VGA gain to: %d.%d dB\n\r", (int)defInit.rxGain1000/1000, (int)((defInit.rxGain1000 - (int)(defInit.rxGain1000/1000)*1000)));
	retGain = (float)XCOMM_SetRxGain(defInit.rxGain1000) / 1000.0f;
	xil_printf("Actual set VGA gain: %d.%d dB\n\r", (int)retGain, (int)((retGain - (int)retGain) * 1000));

	xil_printf("\n\rSetting the Rx frequency to: %lld%06lld\n\r", defInit.rxFrequency/(uint64_t)1e6, defInit.rxFrequency%(uint64_t)1e6);
    retFreqRx = XCOMM_SetRxFrequency(defInit.rxFrequency);
    xil_printf("Actual set Rx frequency: %lld%06lld\n\r", retFreqRx/(uint64_t)1e6, retFreqRx%(uint64_t)1e6);

	xil_printf("\n\rSetting the Tx frequency to: %lld%06lld\n\r", defInit.txFrequency/(uint64_t)1e6, defInit.txFrequency%(uint64_t)1e6);
    retFreqTx = XCOMM_SetTxFrequency(defInit.txFrequency);
    xil_printf("Actual set Tx frequency: %lld%06lld\n\r", retFreqTx/(uint64_t)1e6, retFreqTx%(uint64_t)1e6);

    xil_printf("\n\rSetting up the DDS... \n\r");
    dds_setup(fmcSel, 5, 5);
    xil_printf("DDS setup complete.\n\r");

    xil_printf("\n\rReading data from air... \n\r");
    XCOMM_SetAdcTestMode(XCOMM_AdcTestMode_Off, XCOMM_AdcChannel_All);
    while(1)
    {
    	adc_capture(fmcSel, 1024, DDR_BASEADDR);
    }
    xil_printf("Read data from air complete. \n\r");

    xil_printf("\n\rFinished XCOMM Test Program\n\r");

    Xil_DCacheDisable();
    Xil_ICacheDisable();

    return 0;
}
Пример #16
0
int main() 
{

   static XIntc intc;
   static XSpi axi_spi_0_Spi;
   static XTmrCtr axi_timer_0_Timer;

   Xil_ICacheEnable();
   Xil_DCacheEnable();

   print("---Entering main---\n\r");

   

   {
      int status;
      
      print("\r\n Running IntcSelfTestExample() for microblaze_0_intc...\r\n");
      
      status = IntcSelfTestExample(XPAR_MICROBLAZE_0_INTC_DEVICE_ID);
      
      if (status == 0) {
         print("IntcSelfTestExample PASSED\r\n");
      }
      else {
         print("IntcSelfTestExample FAILED\r\n");
      }
   } 
	
   {
       int Status;

       Status = IntcInterruptSetup(&intc, XPAR_MICROBLAZE_0_INTC_DEVICE_ID);
       if (Status == 0) {
          print("Intc Interrupt Setup PASSED\r\n");
       } 
       else {
         print("Intc Interrupt Setup FAILED\r\n");
      } 
   }
   

   {
      XStatus status;
      
      print("\r\n Runnning SpiSelfTestExample() for axi_spi_0...\r\n");
      
      status = SpiSelfTestExample(XPAR_AXI_SPI_0_DEVICE_ID);
      
      if (status == 0) {
         print("SpiSelfTestExample PASSED\r\n");
      }
      else {
         print("SpiSelfTestExample FAILED\r\n");
      }
   }
    {
       XStatus Status;

       print("\r\n Running Interrupt Test for axi_spi_0...\r\n");

       Status = SpiIntrExample(&intc, &axi_spi_0_Spi, \
                                XPAR_AXI_SPI_0_DEVICE_ID, \
                                XPAR_MICROBLAZE_0_INTC_AXI_SPI_0_IP2INTC_IRPT_INTR);
      if (Status == 0) {
         print("Spi Interrupt Test PASSED\r\n");
      } 
      else {
         print("Spi Interrupt Test FAILED\r\n");
      }

    }
   

   {
      int status;
      
      print("\r\n Running TmrCtrSelfTestExample() for axi_timer_0...\r\n");
      
      status = TmrCtrSelfTestExample(XPAR_AXI_TIMER_0_DEVICE_ID, 0x0);
      
      if (status == 0) {
         print("TmrCtrSelfTestExample PASSED\r\n");
      }
      else {
         print("TmrCtrSelfTestExample FAILED\r\n");
      }
   }
   {
      int Status;

      print("\r\n Running Interrupt Test  for axi_timer_0...\r\n");
      
      Status = TmrCtrIntrExample(&intc, &axi_timer_0_Timer, \
                                 XPAR_AXI_TIMER_0_DEVICE_ID, \
                                 XPAR_MICROBLAZE_0_INTC_AXI_TIMER_0_INTERRUPT_INTR, 0);
	
      if (Status == 0) {
         print("Timer Interrupt Test PASSED\r\n");
      } 
      else {
         print("Timer Interrupt Test FAILED\r\n");
      }

   }
   

   {
      int status;
      
      print("\r\nRunning UartLiteSelfTestExample() for be2fe_console0...\r\n");
      status = UartLiteSelfTestExample(XPAR_BE2FE_CONSOLE0_DEVICE_ID);
      if (status == 0) {
         print("UartLiteSelfTestExample PASSED\r\n");
      }
      else {
         print("UartLiteSelfTestExample FAILED\r\n");
      }
   }
   

   {
      int status;
      
      print("\r\nRunning UartLiteSelfTestExample() for be2fe_console1...\r\n");
      status = UartLiteSelfTestExample(XPAR_BE2FE_CONSOLE1_DEVICE_ID);
      if (status == 0) {
         print("UartLiteSelfTestExample PASSED\r\n");
      }
      else {
         print("UartLiteSelfTestExample FAILED\r\n");
      }
   }
   
   /*
    * Peripheral SelfTest will not be run for debug_module
    * because it has been selected as the STDOUT device
    */


   print("---Exiting main---\n\r");

   Xil_DCacheDisable();
   Xil_ICacheDisable();

   return 0;
}
Пример #17
0
int main() 
{
   static XScuGic intc;
   static XEmacPs ps7_ethernet_0;
   static XGpio axi_btn_Gpio;
   static XScuTimer ps7_scutimer_0;
   static XScuWdt ps7_scuwdt_0;
   Xil_ICacheEnable();
   Xil_DCacheEnable();
   print("---Entering main---\n\r");
   

   {
      int Status;
      
      print("\r\n Running ScuGicSelfTestExample() for ps7_scugic_0...\r\n");
      
      Status = ScuGicSelfTestExample(XPAR_PS7_SCUGIC_0_DEVICE_ID);
      
      if (Status == 0) {
         print("ScuGicSelfTestExample PASSED\r\n");
      }
      else {
         print("ScuGicSelfTestExample FAILED\r\n");
      }
   } 
	
   {
       int Status;

       Status = ScuGicInterruptSetup(&intc, XPAR_PS7_SCUGIC_0_DEVICE_ID);
       if (Status == 0) {
          print("ScuGic Interrupt Setup PASSED\r\n");
       } 
       else {
         print("ScuGic Interrupt Setup FAILED\r\n");
      } 
   }
   

   {
      u32 status;
      
      print("\r\nRunning GpioOutputExample() for axi_led...\r\n");

      status = GpioOutputExample(XPAR_AXI_LED_DEVICE_ID,4);
      
      if (status == 0) {
         print("GpioOutputExample PASSED.\r\n");
      }
      else {
         print("GpioOutputExample FAILED.\r\n");
      }
   }
   

   {
      int Status;
      
      print("\r\n Running DcfgSelfTestExample() for ps7_dev_cfg_0...\r\n");
      
      Status = DcfgSelfTestExample(XPAR_PS7_DEV_CFG_0_DEVICE_ID);
      
      if (Status == 0) {
         print("DcfgSelfTestExample PASSED\r\n");
      }
      else {
         print("DcfgSelfTestExample FAILED\r\n");
      }
   }
   

   {
      int Status;
      
      print("\r\n Running XDmaPs_Example_W_Intr() for ps7_dma_s...\r\n");
      
      Status = XDmaPs_Example_W_Intr(&intc,XPAR_PS7_DMA_S_DEVICE_ID);
      
      if (Status == 0) {
         print("XDmaPs_Example_W_Intr PASSED\r\n");
      }
      else {
         print("XDmaPs_Example_W_Intr FAILED\r\n");
      }
   }
   
   {
      int Status;

      print("\r\n Running Interrupt Test  for ps7_ethernet_0...\r\n");
      
      Status = EmacPsDmaIntrExample(&intc, &ps7_ethernet_0, \
                                 XPAR_PS7_ETHERNET_0_DEVICE_ID, \
                                 XPAR_PS7_ETHERNET_0_INTR);
	
      if (Status == 0) {
         print("EmacPsDmaIntrExample PASSED\r\n");
      } 
      else {
         print("EmacPsDmaIntrExample FAILED\r\n");
      }

   }
   

   {
      int Status;
      
      print("\r\n Running IicPsSelfTestExample() for ps7_i2c_0...\r\n");
      
      Status = IicPsSelfTestExample(XPAR_PS7_I2C_0_DEVICE_ID);
      
      if (Status == 0) {
         print("IicPsSelfTestExample PASSED\r\n");
      }
      else {
         print("IicPsSelfTestExample FAILED\r\n");
      }
   }
   

   {
      int Status;
      
      print("\r\n Running QspiSelfTestExample() for ps7_qspi_0...\r\n");
      
      Status = QspiPsSelfTestExample(XPAR_PS7_QSPI_0_DEVICE_ID);
      
      if (Status == 0) {
         print("QspiPsSelfTestExample PASSED\r\n");
      }
      else {
         print("QspiPsSelfTestExample FAILED\r\n");
      }
   }
   

   {
      u32 status;
      
      print("\r\nRunning GpioInputExample() for axi_btn...\r\n");

      u32 DataRead;
      
      status = GpioInputExample(XPAR_AXI_BTN_DEVICE_ID, &DataRead);
      
      if (status == 0) {
         xil_printf("GpioInputExample PASSED. Read data:0x%X\r\n", DataRead);
      }
      else {
         print("GpioInputExample FAILED.\r\n");
      }
   }
   {
      
      int Status;
        
      u32 DataRead;
      
      print(" Press button to Generate Interrupt\r\n");
      
      Status = GpioIntrExample(&intc, &axi_btn_Gpio, \
                               XPAR_AXI_BTN_DEVICE_ID, \
                               XPAR_FABRIC_AXI_BTN_IP2INTC_IRPT_INTR, \
                               GPIO_CHANNEL1, &DataRead);
	
      if (Status == 0 ){
             if(DataRead == 0)
                print("No button pressed. \r\n");
             else
                print("Gpio Interrupt Test PASSED. \r\n"); 
      } 
      else {
         print("Gpio Interrupt Test FAILED.\r\n");
      }
	
   }
   

   {
      int Status;
      
      print("\r\n Running ScuTimerPolledExample() for ps7_scutimer_0...\r\n");
      
      Status = ScuTimerPolledExample(XPAR_PS7_SCUTIMER_0_DEVICE_ID);
      
      if (Status == 0) {
         print("ScuTimerPolledExample PASSED\r\n");
      }
      else {
         print("ScuTimerPolledExample FAILED\r\n");
      }
   }
   {
      int Status;

      print("\r\n Running Interrupt Test  for ps7_scutimer_0...\r\n");
      
      Status = ScuTimerIntrExample(&intc, &ps7_scutimer_0, \
                                 XPAR_PS7_SCUTIMER_0_DEVICE_ID, \
                                 XPAR_PS7_SCUTIMER_0_INTR);
	
      if (Status == 0) {
         print("ScuTimerIntrExample PASSED\r\n");
      } 
      else {
         print("ScuTimerIntrExample FAILED\r\n");
      }

   }
   
   {
      int Status;

      print("\r\n Running Interrupt Test  for ps7_scuwdt_0...\r\n");
      
      Status = ScuWdtIntrExample(&intc, &ps7_scuwdt_0, \
                                 XPAR_PS7_SCUWDT_0_DEVICE_ID, \
                                 XPAR_PS7_SCUWDT_0_INTR);
	
      if (Status == 0) {
         print("ScuWdtIntrExample PASSED\r\n");
      } 
      else {
         print("ScuWdtIntrExample FAILED\r\n");
      }

   }
   

   {
      int Status;
      
      print("\r\n Running SpiPsSelfTestExample() for ps7_spi_1...\r\n");
      
      Status = SpiPsSelfTestExample(XPAR_PS7_SPI_1_DEVICE_ID);
      
      if (Status == 0) {
         print("SpiPsSelfTestExample PASSED\r\n");
      }
      else {
         print("SpiPsSelfTestExample FAILED\r\n");
      }
   }
   
   /*
    * Peripheral Test will not be run for ps7_uart_1
    * because it has been selected as the STDOUT device
    */

   print("---Exiting main---\n\r");
   Xil_DCacheDisable();
   Xil_ICacheDisable();
   return 0;
}
Пример #18
0
int main(void)
{
	XIntc intc;
	XTmrCtr tmrctr;
	int Status;

	Xil_ICacheEnable();
	Xil_DCacheEnable();

	// Initialize the timer counter so that it's ready to use,
	// specify the device ID that is generated in xparameters.h
	Status = XTmrCtr_Initialize(&tmrctr, XPAR_TMRCTR_0_DEVICE_ID);
	if (Status != XST_SUCCESS) {
		return Status;
	}

	// Initialize the interrupt controller driver so that 
	// it's ready to use, specify the device ID that is generated in
	// xparameters.h
	Status = XIntc_Initialize(&intc, XPAR_INTC_0_DEVICE_ID);
	if (Status != XST_SUCCESS) {
		return Status;
	}

	// Connect a device driver handler that will be called when an interrupt
	// for the device occurs, the device driver handler performs the specific
	// interrupt processing for the device
	Status = XIntc_Connect(&intc, XPAR_INTC_0_TMRCTR_0_VEC_ID, 
			XTmrCtr_InterruptHandler, &tmrctr);
	if (Status != XST_SUCCESS) {
		return Status;
	}

	// Enable the interrupt for the timer counter
	XIntc_Enable(&intc, XPAR_INTC_0_TMRCTR_0_VEC_ID );

	// Start the interrupt controller such that interrupts are enabled for
	// all devices that cause interrupts, specific real mode so that
	// the timer counter can cause interrupts thru the interrupt controller.
	Status = XIntc_Start(&intc, XIN_REAL_MODE);
	if (Status != XST_SUCCESS) {
		return Status;
	}

	// Initialize the exception table.
	Xil_ExceptionInit();

	// Register the interrupt controller handler with the exception table.
	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
    	(Xil_ExceptionHandler)XIntc_InterruptHandler, &intc);

	// Enable non-critical exceptions.
	Xil_ExceptionEnable();

	// Setup the handler for the timer counter that will be called from the
	// interrupt context when the timer expires, specify a pointer to the
	// timer counter driver instance as the callback reference so the handler
	// is able to access the instance data
	XTmrCtr_SetHandler(&tmrctr, TimerCounterHandler, &tmrctr);

	// Enable the interrupt of the timer counter so interrupts will occur
	// and use auto reload mode such that the timer counter will reload
	// itself automatically and continue repeatedly, without this option
	// it would expire once only
	XTmrCtr_SetOptions(&tmrctr, 0, XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION
	| XTC_DOWN_COUNT_OPTION);

	// Set a reset value for the timer counter such that it will expire
	// when it rolls under to 0, the reset value is loaded
	// into the timer counter when it is started
	XTmrCtr_SetResetValue(&tmrctr, 0, XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ-1);

	// Start the timer counter 
	XTmrCtr_Start(&tmrctr, 0);

	while (1) {
	}
	
	Xil_DCacheDisable();
	Xil_ICacheDisable();

	return 0;
}
Пример #19
0
/***************************************************************************
*  This is the main thread that will do all initializations.
*  It will call configure functions for all subsystems and system level
*  peripherals
***************************************************************************/
int main(void)
{
  XPeriph *PeriphPtr;
  XVprocSs *VpssPtr;
  int status;
  u32 Timeout;
  static int Lock = FALSE;

  /* Bind instance pointer with definition */
  PeriphPtr = &PeriphInst;
  VpssPtr   = &VprocInst;

  /* Initialize ICache */
  Xil_ICacheInvalidate();
  Xil_ICacheEnable();

  /* Initialize DCache */
  Xil_DCacheInvalidate();
  Xil_DCacheEnable();


  xil_printf("\r\n--------------------------------------------------------\r\n");
  xil_printf("  Video Processing Subsystem Example Design %s\r\n", XVPROCSS_SW_VER);
  xil_printf("  (c) 2015 by Xilinx Inc.\r\n");
  xil_printf("--------------------------------------------------------\r\n");

  xil_printf("\r\nInitialize System Design...\r\n");
  status = XSys_Init(PeriphPtr, VpssPtr);
  if(status != XST_SUCCESS)
  {
	 xil_printf("CRITICAL ERR:: System Init Failed. Cannot recover from this error. Check HW\n\r");
  }

#if (VERBOSE_MODE == 1)
  xil_printf("\r\nINFO> Setting up VPSS AXIS In/Out\r\n");
#endif
  //Set TPG default parameters
  XPeriph_SetTpgParams(PeriphPtr,
		               1920,
		               1080,
		               XVIDC_CSF_RGB,
		               XTPG_BKGND_COLOR_BARS,
		               FALSE);

  //Set AXIS In to TPG settings
  XSys_SetStreamParam(VpssPtr,
		              XSYS_VPSS_STREAM_IN,
		              PeriphInst.TpgConfig.Width,
		              PeriphInst.TpgConfig.Height,
		              PeriphInst.TpgConfig.ColorFmt,
		              PeriphInst.TpgConfig.IsInterlaced);

  if(VpssPtr->Config.Topology == XVPROCSS_TOPOLOGY_SCALER_ONLY)
  {
	/* Only Scaling Ratio can be changed. Stream out color format
	 * must be same as stream in
	 */
    //Set AXIS Out
    XSys_SetStreamParam(VpssPtr,
		                XSYS_VPSS_STREAM_OUT,
		                3840,
		                2160,
		                PeriphInst.TpgConfig.ColorFmt,
		                FALSE);
  }
  else //FULL_FLEDGED
  {
	//Set AXIS Out
	XSys_SetStreamParam(VpssPtr,
	                    XSYS_VPSS_STREAM_OUT,
			            3840,
			            2160,
			            XVIDC_CSF_YCRCB_422,
			            FALSE);
  }

  //Configure video processing subsystem
  status = XVprocSs_SetSubsystemConfig(VpssPtr);

  //Query vpss configuration
  XVprocSs_ReportSubsystemConfig(VpssPtr);

  if(status == XST_SUCCESS)
  {
    //Configure VTC with output timing
	XPeriph_ConfigVtc(PeriphPtr,
			          &VpssPtr->VidOut,
			          VprocInst.Config.PixPerClock);

    //Config TPG for AXIS In
    XPeriph_ConfigTpg(PeriphPtr);

#if (VERBOSE_MODE == 1)
    XPeriph_TpgDbgReportStatus(PeriphPtr);
#endif

    /* vtc is running at 9Mhz essentially providing < 2fps frame rate
     * Need to wait for 3-4 frames (~2sec) for vidout to acquire lock
     */
    xil_printf("\r\nWaiting for output to lock: ");
    MB_Sleep(2000);

    /* check for output lock */
    Timeout = VIDEO_MONITOR_LOCK_TIMEOUT;
    while(!Lock && Timeout)
    {
      if(XPeriph_IsVideoLocked(PeriphPtr))
      {
        xil_printf("Locked\r\n");
        Lock = TRUE;
      }
      --Timeout;
    }

    if(!Timeout)
    {
      xil_printf("\r\nTEST FAILED\r\n");
    }
    else
    {
      xil_printf("\r\nTEST PASSED\r\n");
    }
  }
  else
  {
    xil_printf("\r\nERR:: VProcss Configuration Failed. \r\n");
	xil_printf("\r\nTEST FAILED\r\n");
  }

  while(1)
  {
	 //NOP
  }

  /* Clean up DCache. For writeback caches, the disable_dcache routine
  internally does the flush and invalidate. For write through caches,
  an explicit invalidation must be performed on the entire cache. */
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 0
  Xil_DCacheInvalidate ();
#endif

  Xil_DCacheDisable ();

  /* Clean up ICache */
  Xil_ICacheInvalidate ();
  Xil_ICacheDisable ();

  return 0;
}
Пример #20
0
/***************************************************************************//**
 * @brief main
*******************************************************************************/
int main(void)
{
#ifdef XILINX_PLATFORM
	Xil_ICacheEnable();
	Xil_DCacheEnable();
#endif

#ifdef ALTERA_PLATFORM
	if (altera_bridge_init()) {
		printf("Altera Bridge Init Error!\n");
		return -1;
	}
#endif

	// NOTE: The user has to choose the GPIO numbers according to desired
	// carrier board.
	default_init_param.gpio_resetb = GPIO_RESET_PIN;
#ifdef FMCOMMS5
	default_init_param.gpio_sync = GPIO_SYNC_PIN;
	default_init_param.gpio_cal_sw1 = GPIO_CAL_SW1_PIN;
	default_init_param.gpio_cal_sw2 = GPIO_CAL_SW2_PIN;
	default_init_param.rx1rx2_phase_inversion_en = 1;
#else
	default_init_param.gpio_sync = -1;
	default_init_param.gpio_cal_sw1 = -1;
	default_init_param.gpio_cal_sw2 = -1;
#endif

#ifdef LINUX_PLATFORM
	gpio_init(default_init_param.gpio_resetb);
#else
	gpio_init(GPIO_DEVICE_ID);
#endif
	gpio_direction(default_init_param.gpio_resetb, 1);

	spi_init(SPI_DEVICE_ID, 1, 0);

	if (AD9364_DEVICE)
		default_init_param.dev_sel = ID_AD9364;
	if (AD9363A_DEVICE)
		default_init_param.dev_sel = ID_AD9363A;

#if defined FMCOMMS5 || defined PICOZED_SDR || defined PICOZED_SDR_CMOS
	default_init_param.xo_disable_use_ext_refclk_enable = 1;
#endif

#ifdef PICOZED_SDR_CMOS
	default_init_param.swap_ports_enable = 1;
	default_init_param.lvds_mode_enable = 0;
	default_init_param.lvds_rx_onchip_termination_enable = 0;
	default_init_param.full_port_enable = 1;
	default_init_param.digital_interface_tune_fir_disable = 1;
#endif

	ad9361_init(&ad9361_phy, &default_init_param);

	ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
	ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);

#ifdef FMCOMMS5
#ifdef LINUX_PLATFORM
	gpio_init(default_init_param.gpio_sync);
#endif
	gpio_direction(default_init_param.gpio_sync, 1);
	default_init_param.id_no = 1;
	default_init_param.gpio_resetb = GPIO_RESET_PIN_2;
#ifdef LINUX_PLATFORM
	gpio_init(default_init_param.gpio_resetb);
#endif
	default_init_param.gpio_sync = -1;
	default_init_param.gpio_cal_sw1 = -1;
	default_init_param.gpio_cal_sw2 = -1;
	default_init_param.rx_synthesizer_frequency_hz = 2300000000UL;
	default_init_param.tx_synthesizer_frequency_hz = 2300000000UL;
	gpio_direction(default_init_param.gpio_resetb, 1);
	ad9361_init(&ad9361_phy_b, &default_init_param);

	ad9361_set_tx_fir_config(ad9361_phy_b, tx_fir_config);
	ad9361_set_rx_fir_config(ad9361_phy_b, rx_fir_config);
#endif

#ifndef AXI_ADC_NOT_PRESENT
#if defined XILINX_PLATFORM || defined LINUX_PLATFORM
#ifdef DAC_DMA
#ifdef FMCOMMS5
	dac_init(ad9361_phy_b, DATA_SEL_DMA, 0);
#endif
	dac_init(ad9361_phy, DATA_SEL_DMA, 1);
#else
#ifdef FMCOMMS5
	dac_init(ad9361_phy_b, DATA_SEL_DDS, 0);
#endif
	dac_init(ad9361_phy, DATA_SEL_DDS, 1);
#endif
#endif
#endif

#ifdef FMCOMMS5
	ad9361_do_mcs(ad9361_phy, ad9361_phy_b);
#endif

#ifndef AXI_ADC_NOT_PRESENT
#if defined XILINX_PLATFORM && defined CAPTURE_SCRIPT
    // NOTE: To prevent unwanted data loss, it's recommended to invalidate
    // cache after each adc_capture() call, keeping in mind that the
    // size of the capture and the start address must be alinged to the size
    // of the cache line.
	mdelay(1000);
    adc_capture(16384, ADC_DDR_BASEADDR);
    Xil_DCacheInvalidateRange(ADC_DDR_BASEADDR, 16384);
#endif
#endif

#ifdef CONSOLE_COMMANDS
	get_help(NULL, 0);

	while(1)
	{
		console_get_command(received_cmd);
		invalid_cmd = 0;
		for(cmd = 0; cmd < cmd_no; cmd++)
		{
			param_no = 0;
			cmd_type = console_check_commands(received_cmd, cmd_list[cmd].name,
											  param, &param_no);
			if(cmd_type == UNKNOWN_CMD)
			{
				invalid_cmd++;
			}
			else
			{
				cmd_list[cmd].function(param, param_no);
			}
		}
		if(invalid_cmd == cmd_no)
		{
			console_print("Invalid command!\n");
		}
	}
#endif

	printf("Done.\n");

#ifdef TDD_SWITCH_STATE_EXAMPLE
	uint32_t ensm_mode;
	if (!ad9361_phy->pdata->fdd) {
		if (ad9361_phy->pdata->ensm_pin_ctrl) {
			gpio_direction(GPIO_ENABLE_PIN, 1);
			gpio_direction(GPIO_TXNRX_PIN, 1);
			gpio_set_value(GPIO_ENABLE_PIN, 0);
			gpio_set_value(GPIO_TXNRX_PIN, 0);
			udelay(10);
			ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
			printf("TXNRX control - Alert: %s\n",
					ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
			mdelay(1000);

			if (ad9361_phy->pdata->ensm_pin_pulse_mode) {
				while(1) {
					gpio_set_value(GPIO_TXNRX_PIN, 0);
					udelay(10);
					gpio_set_value(GPIO_ENABLE_PIN, 1);
					udelay(10);
					gpio_set_value(GPIO_ENABLE_PIN, 0);
					ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
					printf("TXNRX Pulse control - RX: %s\n",
							ensm_mode == ENSM_MODE_RX ? "OK" : "Error");
					mdelay(1000);

					gpio_set_value(GPIO_ENABLE_PIN, 1);
					udelay(10);
					gpio_set_value(GPIO_ENABLE_PIN, 0);
					ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
					printf("TXNRX Pulse control - Alert: %s\n",
							ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
					mdelay(1000);

					gpio_set_value(GPIO_TXNRX_PIN, 1);
					udelay(10);
					gpio_set_value(GPIO_ENABLE_PIN, 1);
					udelay(10);
					gpio_set_value(GPIO_ENABLE_PIN, 0);
					ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
					printf("TXNRX Pulse control - TX: %s\n",
							ensm_mode == ENSM_MODE_TX ? "OK" : "Error");
					mdelay(1000);

					gpio_set_value(GPIO_ENABLE_PIN, 1);
					udelay(10);
					gpio_set_value(GPIO_ENABLE_PIN, 0);
					ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
					printf("TXNRX Pulse control - Alert: %s\n",
							ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
					mdelay(1000);
				}
			} else {
				while(1) {
					gpio_set_value(GPIO_TXNRX_PIN, 0);
					udelay(10);
					gpio_set_value(GPIO_ENABLE_PIN, 1);
					udelay(10);
					ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
					printf("TXNRX control - RX: %s\n",
							ensm_mode == ENSM_MODE_RX ? "OK" : "Error");
					mdelay(1000);

					gpio_set_value(GPIO_ENABLE_PIN, 0);
					udelay(10);
					ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
					printf("TXNRX control - Alert: %s\n",
							ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
					mdelay(1000);

					gpio_set_value(GPIO_TXNRX_PIN, 1);
					udelay(10);
					gpio_set_value(GPIO_ENABLE_PIN, 1);
					udelay(10);
					ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
					printf("TXNRX control - TX: %s\n",
							ensm_mode == ENSM_MODE_TX ? "OK" : "Error");
					mdelay(1000);

					gpio_set_value(GPIO_ENABLE_PIN, 0);
					udelay(10);
					ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
					printf("TXNRX control - Alert: %s\n",
							ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
					mdelay(1000);
				}
			}
		} else {
			while(1) {
				ad9361_set_en_state_machine_mode(ad9361_phy, ENSM_MODE_RX);
				ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
				printf("SPI control - RX: %s\n",
						ensm_mode == ENSM_MODE_RX ? "OK" : "Error");
				mdelay(1000);

				ad9361_set_en_state_machine_mode(ad9361_phy, ENSM_MODE_ALERT);
				ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
				printf("SPI control - Alert: %s\n",
						ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
				mdelay(1000);

				ad9361_set_en_state_machine_mode(ad9361_phy, ENSM_MODE_TX);
				ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
				printf("SPI control - TX: %s\n",
						ensm_mode == ENSM_MODE_TX ? "OK" : "Error");
				mdelay(1000);

				ad9361_set_en_state_machine_mode(ad9361_phy, ENSM_MODE_ALERT);
				ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
				printf("SPI control - Alert: %s\n",
						ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
				mdelay(1000);
			}
		}
	}
#endif

#ifdef XILINX_PLATFORM
	Xil_DCacheDisable();
	Xil_ICacheDisable();
#endif

#ifdef ALTERA_PLATFORM
	if (altera_bridge_uninit()) {
		printf("Altera Bridge Uninit Error!\n");
		return -1;
	}
#endif

	return 0;
}
int main()
{

    static XIntc intc;

    Xil_ICacheEnable();
    Xil_DCacheEnable();

    xil_printf("Testing UART output.\r\n");

    // Camera DMA Configuration
    XAxiDma_Config *dmaconf = XAxiDma_LookupConfig(XPAR_AXI_DMA_0_DEVICE_ID);
    XAxiDma dma;
    XAxiDma_CfgInitialize(&dma, dmaconf);
    XAxiDma_Resume(&dma);
    XAxiDma_Reset(&dma);
    while(!XAxiDma_ResetIsDone(&dma));

    // Initialize Video
    InitVideo();

    // Example camera DMA read
    // Note - transfer MUST be 4096B
    // Data format is 20-bit pixel number (stored in a 32 bit integer) followed by 16-bit RGB values
    // This will not work until you implement camera_stream.v.
    // (or at least, until you have it barely working)
    //int resdde = XAxiDma_SimpleTransfer(&dma, (u32)((unsigned char*)&camera), 4096, XAXIDMA_DEVICE_TO_DMA);
    //while(XAxiDma_Busy(&dma,XAXIDMA_DEVICE_TO_DMA));


    int Status;
    XEmacLite *EmacLiteInstPtr = &EmacLiteInstance;
    u32 PhyAddress = 0;
    RecvFrameLength = 0;
    XEmacLite_Config *ConfigPtr;

    /*
     * Initialize the EmacLite device.
     */
    ConfigPtr = XEmacLite_LookupConfig(XPAR_ETHERNET_LITE_DEVICE_ID);
    if (ConfigPtr == NULL) {
        return XST_FAILURE;
    }
    Status = XEmacLite_CfgInitialize(EmacLiteInstPtr,
                    ConfigPtr,
                    ConfigPtr->BaseAddress);
    if (Status != XST_SUCCESS) {
        return XST_FAILURE;
    }

    /*
     * Set the MAC address.
     */
    XEmacLite_SetMacAddress(EmacLiteInstPtr, LocalAddress);

    /*
     * Empty any existing receive frames.
     */
    XEmacLite_FlushReceive(EmacLiteInstPtr);

    /*
     * Check if there is a TX buffer available, if there isn't it is an
     * error.
     */
    if (XEmacLite_TxBufferAvailable(EmacLiteInstPtr) != TRUE) {
        return XST_FAILURE;
    }

    /*
     * Reset the receive frame length to zero.
     */
    RecvFrameLength = 0;

    // Example program that sends packets and changes the color of an on-screen box upon receiving a packet.
    unsigned char c = 0;
    unsigned char r=0xFF, g=0x0, b=0x0;

    while(1) {
        c++;
        if(XEmacLite_IsTxDone(ConfigPtr->BaseAddress)) {
            Status = EmacLiteSendFrame(EmacLiteInstPtr, EMACLITE_TEST_FRAME_SIZE);
            if (Status != XST_SUCCESS) {
                if (XEmacLite_IsMdioConfigured(EmacLiteInstPtr)) {
                    return XST_FAILURE;
                }
            }
        }
        else {
            RecvFrameLength = XEmacLite_Recv(EmacLiteInstPtr, (u8 *)RxFrame);
            if (RecvFrameLength > 0) {
            	xil_printf("Received a packet!\r\n");
                unsigned char oldr = r;
                r=g;
                g=b;
                b=oldr;
            }
            // Example of writing data to the screen
            int x, y;
            for (x = 0; x < 20; x++)
                for (y = 0; y < 20; y++)
                    if (t[y*20 + x]) {
                        fptr[y*640*4 + x*4] = b;
                        fptr[y*640*4 + x*4 + 1] = g;
                        fptr[y*640*4 + x*4 + 2] = r;
                    }
        }
    }

    Xil_DCacheDisable();
    Xil_ICacheDisable();

    return 0;
}
Пример #22
0
void cleanup_platform()
{
	Xil_ICacheDisable();
	Xil_DCacheDisable();
	return;
}
Пример #23
0
void system_disable_caches(void)
{
	Xil_DCacheDisable();
	Xil_ICacheDisable();
}
Пример #24
0
/**
 * @brief disable_caches() - Disable caches
 */
void disable_caches()
{
	Xil_DCacheDisable();
	Xil_ICacheDisable();
}
Пример #25
0
int main()
{
	ad77681_dev		*adc1_dev;
	ad77681_dev		*adc2_dev;
	spi_msg 		*msg;
	uint8_t			adc1_data[5];
	uint8_t			adc2_data[5];
	uint8_t 		*data;
	uint32_t 		i;

	Xil_ICacheEnable();
	Xil_DCacheEnable();

    ad77681_setup(&adc2_dev, ADC2_default_init_param);
    ad77681_setup(&adc1_dev, ADC1_default_init_param);

	if (SPI_ENGINE_OFFLOAD_EXAMPLE == 0) {
		while(1){
			ad77681_spi_read_adc_data(adc2_dev, adc2_data);
			printf("[ADC2 DATA]: 0x");
			for(i = 0; i < sizeof(adc2_data) / sizeof(uint8_t); i++) {
				printf("%x", adc2_data[i]);
			}
			printf("\r\n");
			mdelay(1000);

			ad77681_spi_read_adc_data(adc1_dev, adc1_data);
			printf("[ADC1 DATA]: 0x");
			for(i = 0; i < sizeof(adc1_data) / sizeof(uint8_t); i++) {
				printf("%x", adc1_data[i]);
			}
			printf("\r\n");
			mdelay(1000);
		}
	} else { // offload example
		msg = (spi_msg *)malloc(sizeof(*msg));
		if (!msg)
			return -1;

		msg->spi_msg_cmds = malloc(sizeof(spi_msg_cmds));
		msg->spi_msg_cmds = spi_msg_cmds;
		msg->rx_buf_addr = 0x800000;
		msg->tx_buf_addr = 0xA000000;
		msg->msg_cmd_len = sizeof(spi_msg_cmds) / sizeof(uint32_t);
		msg->tx_buf[0] = AD77681_REG_READ(AD77681_REG_ADC_DATA);
		msg->tx_buf[1] = 0x00;

		spi_eng_offload_load_msg(adc2_dev->spi_eng_dev, msg);
		spi_eng_transfer_multiple_msgs(adc2_dev->spi_eng_dev, 8);

		data = (uint8_t*)adc2_dev->spi_eng_dev->rx_dma_startaddr;

		mdelay(10000);

        for(i = 0; i < adc2_dev->spi_eng_dev->rx_length; i++) {
    		printf("%x\r\n", *data);
    		data += sizeof(uint8_t);
        }
        free(msg);
	}

	printf("Bye\n");

	Xil_DCacheDisable();
	Xil_ICacheDisable();

    return 0;
}
Пример #26
0
int main()
{
   Xil_ICacheEnable();
   Xil_DCacheEnable();
   
   
   print("---Entering main---\n\r");
   
   {
   	   printf("LEDs and switches\r\n");
   	    XGpio_Initialize(&inGpio,XPAR_AXI_GPIO_1_DEVICE_ID);
   	    XGpio_Initialize(&outGpio,XPAR_AXI_GPIO_0_DEVICE_ID);
   	    XGpio_DiscreteWrite(&outGpio,1,0); // leds off
      }

      {
   	   printf("Deca SPI test\r\n");

   	    if (0 != openspi()){
   	    	printf("Init SPI failed\r\n");
   	    } else {

   			// get switches
   			int sw = XGpio_DiscreteRead(&inGpio,1);
   			XGpio_DiscreteWrite(&outGpio,1,sw);
   			//printf("LED: %x\r\n",XGpio_DiscreteRead(&outGpio,1));

   			switch (sw & 0x7){

   			case 1:
   				printf("SS TWR INIT\r\n");
   				ssTwrInit();
   				break;
   			case 2:
   				printf("SS TWR RESP\r\n");
   				ssTwrResp();
   				break;
   			case 3:
   				printf("Simple TX\r\n");
   				simpleTx();
   				break;
   			case 4:
   				printf("Simple RX\r\n");
   				simpleRx();
   				break;
   			case 5:
   				printf("TX Wait\r\n");
   				txWait();
   				break;
   			case 6:
   				printf("RX Wait\r\n");
   				rxWait();
   				break;
   			default:

   			    /* Reset and initialise DW1000. */
   				reset_DW1000();
   				dwt_initialise(DWT_LOADNONE);
   				/* Configure DW1000. */
   				printf("UBW configuration sequence\r\n");
   				dwt_configure(&config);
   				dwt_configuretxrf(&txconfig);

   				/* Activate continuous wave mode. */
   				dwt_configcwmode(config.chan);

   				/* Wait for the wanted duration of the continuous wave transmission. */
   				printf("Waiting for UBW continuous wave transmission delay: %ds\r\n",CONT_WAVE_DURATION_MS/1000);
   				deca_sleep(CONT_WAVE_DURATION_MS);

   				/* Software reset of the DW1000 to deactivate continuous wave mode and go back to default state. Initialisation and configuration should be run
   				 * again if one wants to get the DW1000 back to normal operation. */
   				dwt_softreset();
   			}

   			printf("Deca test done. press any key\r\n");
   			getchar();
   	    }

      }


   print("---Exiting main---\n\r");
   Xil_DCacheDisable();
   Xil_ICacheDisable();
   return 0;
}
int main (void) {


   static XIntc intc;

   /*
    * Enable and initialize cache
    */
   #if XPAR_MICROBLAZE_0_USE_ICACHE
      Xil_ICacheInvalidate();
      Xil_ICacheEnable();
   #endif

   #if XPAR_MICROBLAZE_0_USE_DCACHE
      Xil_DCacheInvalidate();
       Xil_DCacheEnable();
   #endif

   static XLlTemac Hard_Ethernet_MAC_LlTemac;
   static XLlDma  Hard_Ethernet_MAC_LlDma;



   /* Initialize RS232_Uart_1 - Set baudrate and number of stop bits */
   XUartNs550_SetBaud(XPAR_RS232_UART_1_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, 9600);
   XUartNs550_SetLineControlReg(XPAR_RS232_UART_1_BASEADDR, XUN_LCR_8_DATA_BITS);
   static XUartNs550 RS232_Uart_2_UartNs550;
   static XTmrCtr xps_timer_0_Timer;
   print("-- Entering main() --\r\n");


   {
      int status;
      
      print("\r\n Running IntcSelfTestExample() for xps_intc_0...\r\n");
      
      status = IntcSelfTestExample(XPAR_XPS_INTC_0_DEVICE_ID);
      
      if (status == 0) {
         print("IntcSelfTestExample PASSED\r\n");
      }
      else {
         print("IntcSelfTestExample FAILED\r\n");
      }
   } 
	
   {
       int Status;

       Status = IntcInterruptSetup(&intc, XPAR_XPS_INTC_0_DEVICE_ID);
       if (Status == 0) {
          print("Intc Interrupt Setup PASSED\r\n");
       } 
       else {
         print("Intc Interrupt Setup FAILED\r\n");
      } 
   }


   {
      u32 status;
      
      print("\r\nRunning GpioOutputExample() for LEDs_8Bit...\r\n");

      status = GpioOutputExample(XPAR_LEDS_8BIT_DEVICE_ID,8);
      
      if (status == 0) {
         print("GpioOutputExample PASSED.\r\n");
      }
      else {
         print("GpioOutputExample FAILED.\r\n");
      }
   }


   {
      u32 status;
      
      print("\r\nRunning GpioOutputExample() for LEDs_Positions...\r\n");

      status = GpioOutputExample(XPAR_LEDS_POSITIONS_DEVICE_ID,5);
      
      if (status == 0) {
         print("GpioOutputExample PASSED.\r\n");
      }
      else {
         print("GpioOutputExample FAILED.\r\n");
      }
   }


   {
      u32 status;
      
      print("\r\nRunning GpioInputExample() for Push_Buttons_5Bit...\r\n");

      u32 DataRead;
      
      status = GpioInputExample(XPAR_PUSH_BUTTONS_5BIT_DEVICE_ID, &DataRead);
      
      if (status == 0) {
         xil_printf("GpioInputExample PASSED. Read data:0x%X\r\n", DataRead);
      }
      else {
         print("GpioInputExample FAILED.\r\n");
      }
   }


   {
      u32 status;
      
      print("\r\nRunning GpioInputExample() for DIP_Switches_8Bit...\r\n");

      u32 DataRead;
      
      status = GpioInputExample(XPAR_DIP_SWITCHES_8BIT_DEVICE_ID, &DataRead);
      
      if (status == 0) {
         xil_printf("GpioInputExample PASSED. Read data:0x%X\r\n", DataRead);
      }
      else {
         print("GpioInputExample FAILED.\r\n");
      }
   }


   {
      int status;
            
      
      print("\r\n Running IicSelfTestExample() for IIC_EEPROM...\r\n");
      
      status = IicSelfTestExample(XPAR_IIC_EEPROM_DEVICE_ID);
      
      if (status == 0) {
         print("IicSelfTestExample PASSED\r\n");
      }
      else {
         print("IicSelfTestExample FAILED\r\n");
      }
   }

   /* TemacPolledExample does not support SGDMA      
   {
      XStatus status;

      print("\r\n Running TemacPolledExample() for Hard_Ethernet_MAC...\r\n");

      status = TemacPolledExample( XPAR_HARD_ETHERNET_MAC_CHAN_0_DEVICE_ID,
                                   );

      if (status == 0) {
         print("TemacPolledExample PASSED\r\n");
      }
      else {
         print("TemacPolledExample FAILED\r\n");
      }

   }
   */

   {
      XStatus Status;

      print("\r\nRunning TemacSgDmaIntrExample() for Hard_Ethernet_MAC...\r\n");

      Status = TemacSgDmaIntrExample(&intc, &Hard_Ethernet_MAC_LlTemac,
                     &Hard_Ethernet_MAC_LlDma,
                     XPAR_HARD_ETHERNET_MAC_CHAN_0_DEVICE_ID,
                     XPAR_XPS_INTC_0_HARD_ETHERNET_MAC_TEMACINTC0_IRPT_INTR,
                     XPAR_LLTEMAC_0_LLINK_CONNECTED_DMARX_INTR,
                     XPAR_LLTEMAC_0_LLINK_CONNECTED_DMATX_INTR);

      if (Status == 0) {
         print("Temac Interrupt Test PASSED.\r\n");
      } 
      else {
         print("Temac Interrupt Test FAILED.\r\n");
      }

   }


   {
      int status;
      
      print("\r\nRunning SysAceSelfTestExample() for SysACE_CompactFlash...\r\n");
      status = SysAceSelfTestExample(XPAR_SYSACE_COMPACTFLASH_DEVICE_ID);
      if (status == 0) {
         print("SysAceSelfTestExample PASSED\r\n");
      }
      else {
         print("SysAceSelfTestExample FAILED\r\n");
      }
   }

   /*
    * Peripheral SelfTest will not be run for RS232_Uart_1
    * because it has been selected as the STDOUT device
    */



   {
      XStatus status;

      print("\r\nRunning UartNs550SelfTestExample() for RS232_Uart_2...\r\n");
      status = UartNs550SelfTestExample(XPAR_RS232_UART_2_DEVICE_ID);
      if (status == 0) {
         print("UartNs550SelfTestExample PASSED\r\n");
      }
      else {
         print("UartNs550SelfTestExample FAILED\r\n");
      }
   }
   {
      XStatus Status;

      print("\r\n Running Interrupt Test for RS232_Uart_2...\r\n");
      
      Status = UartNs550IntrExample(&intc, &RS232_Uart_2_UartNs550, \
                                  XPAR_RS232_UART_2_DEVICE_ID, \
                                  XPAR_XPS_INTC_0_RS232_UART_2_IP2INTC_IRPT_INTR);
	
      if (Status == 0) {
         print("UartNs550 Interrupt Test PASSED\r\n");
      } 
      else {
         print("UartNs550 Interrupt Test FAILED\r\n");
      }

   }


   {
      int status;
      
      print("\r\n Running TmrCtrSelfTestExample() for xps_timer_0...\r\n");
      
      status = TmrCtrSelfTestExample(XPAR_XPS_TIMER_0_DEVICE_ID, 0x0);
      
      if (status == 0) {
         print("TmrCtrSelfTestExample PASSED\r\n");
      }
      else {
         print("TmrCtrSelfTestExample FAILED\r\n");
      }
   }
   {
      int Status;

      print("\r\n Running Interrupt Test  for xps_timer_0...\r\n");
      
      Status = TmrCtrIntrExample(&intc, &xps_timer_0_Timer, \
                                 XPAR_XPS_TIMER_0_DEVICE_ID, \
                                 XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR, 0);
	
      if (Status == 0) {
         print("Timer Interrupt Test PASSED\r\n");
      } 
      else {
         print("Timer Interrupt Test FAILED\r\n");
      }

   }


   {
      int status;
      
      print("\r\nRunning UartLiteSelfTestExample() for mdm_0...\r\n");
      status = UartLiteSelfTestExample(XPAR_MDM_0_DEVICE_ID);
      if (status == 0) {
         print("UartLiteSelfTestExample PASSED\r\n");
      }
      else {
         print("UartLiteSelfTestExample FAILED\r\n");
      }
   }
   /*
    * Disable cache and reinitialize it so that other
    * applications can be run with no problems
    */
   #if XPAR_MICROBLAZE_0_USE_DCACHE
      Xil_DCacheDisable();
      Xil_DCacheInvalidate();
   #endif

   #if XPAR_MICROBLAZE_0_USE_ICACHE
      Xil_ICacheDisable();
      Xil_ICacheInvalidate();
   #endif


   print("-- Exiting main() --\r\n");
   return 0;
}
Пример #28
0
int main (void) {


   Xil_ICacheEnableRegion(0x80000000);
   Xil_DCacheEnableRegion(0x80000000);
   print("-- Entering main() --\r\n");

   /*
    * Peripheral SelfTest will not be run for RS232
    * because it has been selected as the STDOUT device
    */



   {
      int status;
      
      print("\r\nRunning UartLiteSelfTestExample() for RS232_USB...\r\n");
      status = UartLiteSelfTestExample(XPAR_RS232_USB_DEVICE_ID);
      if (status == 0) {
         print("UartLiteSelfTestExample PASSED\r\n");
      }
      else {
         print("UartLiteSelfTestExample FAILED\r\n");
      }
   }


   {
      u32 status;
      
      print("\r\nRunning GpioOutputExample() for LEDs_8Bit...\r\n");

      status = GpioOutputExample(XPAR_LEDS_8BIT_DEVICE_ID,8);
      
      if (status == 0) {
         print("GpioOutputExample PASSED.\r\n");
      }
      else {
         print("GpioOutputExample FAILED.\r\n");
      }
   }


   {
      u32 status;
      
      print("\r\nRunning GpioInputExample() for DIP_Switches_8Bit...\r\n");

      u32 DataRead;
      
      status = GpioInputExample(XPAR_DIP_SWITCHES_8BIT_DEVICE_ID, &DataRead);
      
      if (status == 0) {
         xil_printf("GpioInputExample PASSED. Read data:0x%X\r\n", DataRead);
      }
      else {
         print("GpioInputExample FAILED.\r\n");
      }
   }


   {
      u32 status;
      
      print("\r\nRunning GpioInputExample() for Push_Buttons_3Bit...\r\n");

      u32 DataRead;
      
      status = GpioInputExample(XPAR_PUSH_BUTTONS_3BIT_DEVICE_ID, &DataRead);
      
      if (status == 0) {
         xil_printf("GpioInputExample PASSED. Read data:0x%X\r\n", DataRead);
      }
      else {
         print("GpioInputExample FAILED.\r\n");
      }
   }


   {
      int status;
      
      print("\r\nRunning EmacLitePolledExample() for Ethernet_MAC...\r\n");
      status = EmacLitePolledExample(XPAR_ETHERNET_MAC_DEVICE_ID);
      if (status == 0) {
         print("EmacLite Polled Example PASSED\r\n");
      }
      else {
         print("EmacLite Polled Example FAILED\r\n");
      }
   }


   {
      int status;
      
      print("\r\nRunning SysAceSelfTestExample() for SysACE_CompactFlash...\r\n");
      status = SysAceSelfTestExample(XPAR_SYSACE_COMPACTFLASH_DEVICE_ID);
      if (status == 0) {
         print("SysAceSelfTestExample PASSED\r\n");
      }
      else {
         print("SysAceSelfTestExample FAILED\r\n");
      }
   }

   print("-- Exiting main() --\r\n");
   Xil_DCacheDisable();
   Xil_ICacheDisable();
   return 0;
}
Пример #29
0
/***************************************************************************//**
 * @brief main
 *******************************************************************************/
int initAd9361(void) {

	int Status;
	uint64_t Value;
	uint8_t en_dis;

	/*
	 * NOTE: The user has to choose the GPIO numbers according to desired
	 * carrier board. The following configuration is valid for boards other
	 * than the Fmcomms5.
	 */
	default_init_param.gpio_resetb = GPIO_RESET_PIN;
	default_init_param.gpio_sync = -1;
	default_init_param.gpio_cal_sw1 = -1;
	default_init_param.gpio_cal_sw2 = -1;

	/*
	 * Initialize the GPIO
	 */
	gpio_init(GPIO_DEVICE_ID);
	gpio_direction(default_init_param.gpio_resetb, 1);

	/*
	 * Initialize the SPI
	 */
	spi_init(SPI_DEVICE_ID, 1, 0);

	/*
	 * Initialize AD9361
	 */
	Status = ad9361_init(&ad9361_phy, &default_init_param);
	if (Status != 0) {
		xil_printf("Could not initialize AD9361\r\n");
		xil_printf("Status\t%d\r\n", Status);
		return 1;
	}

	/*
	 * Sampling frequency
	 */
	Status = ad9361_set_tx_sampling_freq(ad9361_phy, SAMPLING_FREQ);
	if (Status != 0) {
		xil_printf("Could not set Tx sampling freq.\r\n");
		return 1;
	}
	Status = ad9361_set_rx_sampling_freq(ad9361_phy, SAMPLING_FREQ);
	if (Status != 0) {
		xil_printf("Could not set Rx sampling freq.\r\n");
		return 1;
	}
	/*
	 * Set Tx and Rx FIR
	 */
	Status = ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
	if (Status != 0) {
		xil_printf("Could not set Tx FIR\r\n");
		return 1;
	}
	Status = ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);
	if (Status != 0) {
		xil_printf("Could not set Rx FIR\r\n");
		return 1;
	}
	// Enable both at the same time
	Status = ad9361_set_trx_fir_en_dis(ad9361_phy, 1);
	if (Status != 0) {
		xil_printf("Could not enable Tx and Rx FIR\r\n");
		return 1;
	}
	// Check status
	Status = ad9361_get_tx_fir_en_dis(ad9361_phy, &en_dis);
	if (Status == 0) {
		xil_printf("Tx FIR status\t %d\r\n", en_dis);
	} else {
		xil_printf("Could not get Tx FIR enable\r\n");
		return 1;
	}
	Status = ad9361_get_rx_fir_en_dis(ad9361_phy, &en_dis);
	if (Status == 0) {
		xil_printf("Rx FIR status\t %d\r\n", en_dis);
	} else {
		xil_printf("Could not get Rx FIR enable\r\n");
		return 1;
	}
	/*
	 * Rf bandwidth
	 */
	Status = ad9361_set_tx_rf_bandwidth(ad9361_phy, RF_BW);
	if (Status != 0) {
		xil_printf("Could not set Tx Rf bandwidth\r\n");
		return 1;
	}
	Status = ad9361_set_rx_rf_bandwidth(ad9361_phy, RF_BW);
	if (Status != 0) {
		xil_printf("Could not set Rx Rf bandwidth\r\n");
		return 1;
	}
	/*
	 * Gain control mode
	 */
	Status = ad9361_set_rx_gain_control_mode(ad9361_phy, 0,
			RF_GAIN_SLOWATTACK_AGC);
	if (Status != 0) {
		xil_printf("Could not set Rx gain control mode for channel 0\r\n");
		return 1;
	}
	/*
	 * Hardware gains
	 */
	Status = ad9361_set_rx_rf_gain(ad9361_phy, 0, -10);
	if (Status != 0) {
		xil_printf("Could not set Rx gain for channel 0\r\n");
		return 1;
	}

	Status = ad9361_get_rx_lo_freq(ad9361_phy, &Value);
	if (Status == 0) {
		xil_printf("LO Frequency\t %u \r\n", Value);
	} else {
		xil_printf("Could not get current LO frequency\r\n");
		return 1;
	}

#if ROE_CPRI_SINK == ROE_SINK_DAC
	dac_init(ad9361_phy, DATA_SEL_DMA, 1);
#endif

#ifndef AXI_ADC_NOT_PRESENT
#if defined XILINX_PLATFORM && defined CAPTURE_SCRIPT
	// NOTE: To prevent unwanted data loss, it's recommended to invalidate
	// cache after each adc_capture() call, keeping in mind that the
	// size of the capture and the start address must be alinged to the size
	// of the cache line.
	mdelay(1000);
	adc_capture(16384, ADC_DDR_BASEADDR);
	Xil_DCacheInvalidateRange(ADC_DDR_BASEADDR, 16384);
#endif
#endif

#ifdef CONSOLE_COMMANDS
	get_help(NULL, 0);

	while (1)
	{
		console_get_command(received_cmd);
		invalid_cmd = 0;
		for (cmd = 0; cmd < cmd_no; cmd++)
		{
			param_no = 0;
			cmd_type = console_check_commands(received_cmd, cmd_list[cmd].name,
					param, &param_no);
			if (cmd_type == UNKNOWN_CMD)
			{
				invalid_cmd++;
			}
			else
			{
				cmd_list[cmd].function(param, param_no);
			}
		}
		if (invalid_cmd == cmd_no)
		{
			console_print("Invalid command!\n");
		}
	}
#endif

	printf("AD9361 Initialization Done.\n");

#ifdef XILINX_PLATFORM
	Xil_DCacheDisable();
	Xil_ICacheDisable();
#endif

	return 0;
}
Пример #30
0
int main() 
{

   static XIntc intc;
   static XGpio dip_switches_4bits_Gpio;
   static XTmrCtr axi_timer_0_Timer;

   Xil_ICacheEnable();
   Xil_DCacheEnable();

   print("---Entering main---\n\r");

   

   {
      int status;
      
      print("\r\n Running IntcSelfTestExample() for microblaze_0_intc...\r\n");
      
      status = IntcSelfTestExample(XPAR_MICROBLAZE_0_INTC_DEVICE_ID);
      
      if (status == 0) {
         print("IntcSelfTestExample PASSED\r\n");
      }
      else {
         print("IntcSelfTestExample FAILED\r\n");
      }
   } 
	
   {
       int Status;

       Status = IntcInterruptSetup(&intc, XPAR_MICROBLAZE_0_INTC_DEVICE_ID);
       if (Status == 0) {
          print("Intc Interrupt Setup PASSED\r\n");
       } 
       else {
         print("Intc Interrupt Setup FAILED\r\n");
      } 
   }
   

   {
      int status;
      
      print("\r\nRunning UartLiteSelfTestExample() for debug_module...\r\n");
      status = UartLiteSelfTestExample(XPAR_DEBUG_MODULE_DEVICE_ID);
      if (status == 0) {
         print("UartLiteSelfTestExample PASSED\r\n");
      }
      else {
         print("UartLiteSelfTestExample FAILED\r\n");
      }
   }
   
   /*
    * Peripheral SelfTest will not be run for usb_uart
    * because it has been selected as the STDOUT device
    */

   

   {
      u32 status;
      
      print("\r\nRunning GpioInputExample() for dip_switches_4bits...\r\n");

      u32 DataRead;
      
      status = GpioInputExample(XPAR_DIP_SWITCHES_4BITS_DEVICE_ID, &DataRead);
      
      if (status == 0) {
         xil_printf("GpioInputExample PASSED. Read data:0x%X\r\n", DataRead);
      }
      else {
         print("GpioInputExample FAILED.\r\n");
      }
   }
   {
      
      int Status;
        
      u32 DataRead;
      
      print(" Press button to Generate Interrupt\r\n");
      
      Status = GpioIntrExample(&intc, &dip_switches_4bits_Gpio, \
                               XPAR_DIP_SWITCHES_4BITS_DEVICE_ID, \
                               XPAR_MICROBLAZE_0_INTC_DIP_SWITCHES_4BITS_IP2INTC_IRPT_INTR, \
                               GPIO_CHANNEL1, &DataRead);
	
      if (Status == 0 ){
             if(DataRead == 0)
                print("No button pressed. \r\n");
             else
                print("Gpio Interrupt Test PASSED. \r\n"); 
      } 
      else {
         print("Gpio Interrupt Test FAILED.\r\n");
      }
	
   }
   

   {
      u32 status;
      
      print("\r\nRunning GpioOutputExample() for leds_4bits...\r\n");

      status = GpioOutputExample(XPAR_LEDS_4BITS_DEVICE_ID,4);
      
      if (status == 0) {
         print("GpioOutputExample PASSED.\r\n");
      }
      else {
         print("GpioOutputExample FAILED.\r\n");
      }
   }
   

   {
      int status;
      
      print("\r\nRunning EmacLitePolledExample() for ethernet_mac...\r\n");
      status = EmacLitePolledExample(XPAR_ETHERNET_MAC_DEVICE_ID);
      if (status == 0) {
         print("EmacLite Polled Example PASSED\r\n");
      }
      else {
         print("EmacLite Polled Example FAILED\r\n");
      }
   }
   

   {
      int status;
      
      print("\r\n Running TmrCtrSelfTestExample() for axi_timer_0...\r\n");
      
      status = TmrCtrSelfTestExample(XPAR_AXI_TIMER_0_DEVICE_ID, 0x0);
      
      if (status == 0) {
         print("TmrCtrSelfTestExample PASSED\r\n");
      }
      else {
         print("TmrCtrSelfTestExample FAILED\r\n");
      }
   }
   {
      int Status;

      print("\r\n Running Interrupt Test  for axi_timer_0...\r\n");
      
      Status = TmrCtrIntrExample(&intc, &axi_timer_0_Timer, \
                                 XPAR_AXI_TIMER_0_DEVICE_ID, \
                                 XPAR_MICROBLAZE_0_INTC_AXI_TIMER_0_INTERRUPT_INTR, 0);
	
      if (Status == 0) {
         print("Timer Interrupt Test PASSED\r\n");
      } 
      else {
         print("Timer Interrupt Test FAILED\r\n");
      }

   }
   

   {
      XStatus status;
      
      print("\r\n Runnning SpiSelfTestExample() for spi_flash...\r\n");
      
      status = SpiSelfTestExample(XPAR_SPI_FLASH_DEVICE_ID);
      
      if (status == 0) {
         print("SpiSelfTestExample PASSED\r\n");
      }
      else {
         print("SpiSelfTestExample FAILED\r\n");
      }
   }

   print("---Exiting main---\n\r");

   Xil_DCacheDisable();
   Xil_ICacheDisable();

   return 0;
}