Пример #1
0
void cec_enable_irq(void)
{
    aml_write_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_STAT_CLR, aml_read_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_STAT_CLR) & ~(1 << 23));
    aml_write_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_MASK, aml_read_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_MASK) | (1 << 23));

    hdmi_print(INF, CEC "enable:int mask:0x%x\n", aml_read_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_MASK));
}
Пример #2
0
static void set_control_lvds(Lcd_Config_t *pConf)
{
	PRINT_INFO("%s\n", __FUNCTION__);

	if (lvds_repack_flag)
		lvds_repack = (pConf->lvds_mlvds_config.lvds_config->lvds_repack) & 0x1;
	pn_swap = (pConf->lvds_mlvds_config.lvds_config->pn_swap) & 0x1;
	dual_port = (pConf->lvds_mlvds_config.lvds_config->dual_port) & 0x1;
	if (port_reverse_flag)
		port_reverse = (pConf->lvds_mlvds_config.lvds_config->port_reverse) & 0x1;

	if (bit_num_flag) {
		switch (pConf->lcd_basic.lcd_bits) {
			case 10: bit_num=0; break;
			case 8: bit_num=1; break;
			case 6: bit_num=2; break;
			case 4: bit_num=3; break;
			default: bit_num=1; break;
		}
	}

	aml_write_reg32(P_MLVDS_CONTROL,  (aml_read_reg32(P_MLVDS_CONTROL) & ~(1 << 0)));  //disable mlvds
	aml_write_reg32(P_LVDS_PACK_CNTL_ADDR,
					( lvds_repack<<0 ) | // repack
					( port_reverse?(0<<2):(1<<2)) | // odd_even
					( 0<<3 ) | // reserve
					( 0<<4 ) | // lsb first
					( pn_swap<<5 ) | // pn swap
					( dual_port<<6 ) | // dual port
					( 0<<7 ) | // use tcon control
					( bit_num<<8 ) | // 0:10bits, 1:8bits, 2:6bits, 3:4bits.
					( 0<<10 ) | //r_select  //0:R, 1:G, 2:B, 3:0
					( 1<<12 ) | //g_select  //0:R, 1:G, 2:B, 3:0
					( 2<<14 ));  //b_select  //0:R, 1:G, 2:B, 3:0;
}
Пример #3
0
static inline void _enable_vsync_interrupt(void)
{
	if ((aml_read_reg32(P_ENCT_VIDEO_EN) & 1) || (aml_read_reg32(P_ENCL_VIDEO_EN) & 1)) {
		aml_write_reg32(P_VENC_INTCTRL, 0x200);
	}else {
		aml_write_reg32(P_VENC_INTCTRL, 0x2);
	}
}
Пример #4
0
void enable_watchdog(void)
{
	printk(KERN_INFO "** enable watchdog\n");
    aml_write_reg32(P_WATCHDOG_RESET, 0);
    aml_write_reg32(P_WATCHDOG_TC, 1 << WATCHDOG_ENABLE_BIT | 0x1FFFFF);//about 20sec
    
    aml_write_reg32(P_AO_RTI_STATUS_REG1, MESON_NORMAL_BOOT);
}
Пример #5
0
static void set_pll_lvds(Lcd_Config_t *pConf)
{
	PRINT_INFO("%s\n", __FUNCTION__);

	vclk_set_encl_lvds(pDev->lcd_info.mode, pConf->lvds_mlvds_config.lvds_config->dual_port);
	aml_write_reg32( P_HHI_VIID_DIVIDER_CNTL, ((aml_read_reg32(P_HHI_VIID_DIVIDER_CNTL) & ~(0x7 << 8)) | (2 << 8) | (0<<10)) );
	aml_write_reg32(P_LVDS_GEN_CNTL, (aml_read_reg32(P_LVDS_GEN_CNTL)| (1 << 3) | (3<< 0)));
}
Пример #6
0
void cec_disable_irq(void)
{
    //Disable irq
    aml_write_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_MASK, aml_read_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_MASK) & ~(1 << 23));
    //Clear the interrupt
    aml_write_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_STAT_CLR, aml_read_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_STAT_CLR) | (1 << 23));
    hdmi_print(INF, CEC "disable:int mask:0x%x\n", aml_read_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_MASK));
}
void hdmi_wr_only_reg(unsigned long addr, unsigned long data)
{
    check_cts_hdmi_sys_clk_status();
//    WRITE_APB_REG(HDMI_ADDR_PORT, addr);
//    WRITE_APB_REG(HDMI_ADDR_PORT, addr);
//    
//    WRITE_APB_REG(HDMI_DATA_PORT, data);
    aml_write_reg32(P_HDMI_ADDR_PORT, addr);
    aml_write_reg32(P_HDMI_ADDR_PORT, addr);
    
    aml_write_reg32(P_HDMI_DATA_PORT, data);
}
Пример #8
0
static void hpll_load_en(void)
{
//hdmi load gen
    aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 1, 19, 1);
    aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 7, 0 , 3);
    aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 1, 16, 3);  // tmp use fclk_div4
    aml_write_reg32(P_ENCL_VIDEO_EN, 0x1);
    msleep(20);
    aml_write_reg32(P_ENCL_VIDEO_EN, 0x0);
    msleep(20);
//    printk("read Addr: 0x%x[0x%x]  Data: 0x%x\n", P_HHI_HDMI_PLL_CNTL, (P_HHI_HDMI_PLL_CNTL & 0xffff) >> 2, aml_read_reg32(P_HHI_HDMI_PLL_CNTL));
    aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 0, 16, 3);  // use vid_pll
}
unsigned long hdmi_rd_reg(unsigned long addr)
{
    unsigned long data;
    check_cts_hdmi_sys_clk_status();
//    WRITE_APB_REG(HDMI_ADDR_PORT, addr);
//    WRITE_APB_REG(HDMI_ADDR_PORT, addr);
    aml_write_reg32(P_HDMI_ADDR_PORT, addr);
    aml_write_reg32(P_HDMI_ADDR_PORT, addr);
    
//    data = READ_APB_REG(HDMI_DATA_PORT);
    data = aml_read_reg32(P_HDMI_DATA_PORT);
    
    return (data);
}
Пример #10
0
void hdmi_wr_reg(unsigned int addr, unsigned int data)
{
    unsigned long flags, fiq_flag;
    spin_lock_irqsave(&reg_lock, flags);
    raw_local_save_flags(fiq_flag);
    local_fiq_disable();

    check_cts_hdmi_sys_clk_status();
    aml_write_reg32(P_HDMI_ADDR_PORT, addr);
    aml_write_reg32(P_HDMI_ADDR_PORT, addr);
    aml_write_reg32(P_HDMI_DATA_PORT, data);
    raw_local_irq_restore(fiq_flag);
    spin_unlock_irqrestore(&reg_lock, flags);
}
static void backlight_power_ctrl(Bool_t status)
{ 
	PRINT_INFO("%s(): bl_status=%s, data_status=%s, bl_level=%u\n", __FUNCTION__, (bl_status ? "ON" : "OFF"), (data_status ? "ON" : "OFF"), bl_level);
    if( status == ON ){
		if ((bl_status == ON) || (data_status == OFF) || (bl_level == 0))
			return;
        aml_set_reg32_bits(P_LED_PWM_REG0, 1, 12, 2);
        mdelay(20); 
		
#if (BL_CTL==BL_CTL_GPIO)
		//BL_EN -> GPIOD_1: 1
		gpio_out(PAD_GPIOD_1, 1);
#elif (BL_CTL==BL_CTL_PWM)
		aml_set_reg32_bits(P_PWM_MISC_REG_CD, PWM_PRE_DIV, 16, 7);
		aml_set_reg32_bits(P_PWM_MISC_REG_CD, 1, 23, 1);
		aml_set_reg32_bits(P_PWM_MISC_REG_CD, 1, 1, 1);  //enable pwm_d		
		aml_write_reg32(P_PERIPHS_PIN_MUX_2, aml_read_reg32(P_PERIPHS_PIN_MUX_2) | (1<<3));  //enable pwm pinmux
#endif
    }
    else{
		if (bl_status == OFF)
			return;
#if (BL_CTL==BL_CTL_GPIO)		
		gpio_out(PAD_GPIOD_1, 0);		
#elif (BL_CTL==BL_CTL_PWM)		
		aml_set_reg32_bits(P_PWM_MISC_REG_CD, 0, 1, 1);	//disable pwm_d		
#endif		
    }
	bl_status = status;
	printk(KERN_INFO "%s() Power %s\n", __FUNCTION__, (status ? "ON" : "OFF"));
}
Пример #12
0
void cec_hw_reset(void)
{
    //unsigned long data32;
    // Assert SW reset AO_CEC
    //data32  = 0;
    //data32 |= 0 << 1;   // [2:1]    cntl_clk: 0=Disable clk (Power-off mode); 1=Enable gated clock (Normal mode); 2=Enable free-run clk (Debug mode).
    //data32 |= 1 << 0;   // [0]      sw_reset: 1=Reset
    aml_write_reg32(P_AO_CEC_GEN_CNTL, 0x1);
    // Enable gated clock (Normal mode).
    aml_set_reg32_bits(P_AO_CEC_GEN_CNTL, 1, 1, 1);
    // Release SW reset
    aml_set_reg32_bits(P_AO_CEC_GEN_CNTL, 0, 0, 1);

    // Enable all AO_CEC interrupt sources
    if (!cec_int_disable_flag)
        aml_set_reg32_bits(P_AO_CEC_INTR_MASKN, 0x6, 0, 3);

    aocec_wr_reg(CEC_LOGICAL_ADDR0, (0x1 << 4) | cec_global_info.my_node_index);

    //Cec arbitration 3/5/7 bit time set.
    cec_arbit_bit_time_set(3, 0x118, 0);
    cec_arbit_bit_time_set(5, 0x000, 0);
    cec_arbit_bit_time_set(7, 0x2aa, 0);

    hdmi_print(INF, CEC "hw reset :logical addr:0x%x\n", aocec_rd_reg(CEC_LOGICAL_ADDR0));

}
static void set_backlight_level(unsigned level)
{
    PRINT_INFO(KERN_INFO "set_backlight_level: %u, last level: %u\n", level, bl_level);
	level = (level > BL_MAX_LEVEL ? BL_MAX_LEVEL : (level < BL_MIN_LEVEL ? 0 : level));	
	bl_level = level;    

	if (level == 0) {
		backlight_power_ctrl(OFF);		
	}
	else {	
		if (level > BL_MID_LEVEL) {
			level = ((level - BL_MID_LEVEL)*(BL_MAX_LEVEL-BL_MAPPED_MID_LEVEL))/(BL_MAX_LEVEL - BL_MID_LEVEL) + BL_MAPPED_MID_LEVEL; 
		} else {
			//level = (level*BL_MAPPED_MID_LEVEL)/BL_MID_LEVEL;
			level = ((level - BL_MIN_LEVEL)*(BL_MAPPED_MID_LEVEL - BL_MIN_LEVEL))/(BL_MID_LEVEL - BL_MIN_LEVEL) + BL_MIN_LEVEL; 
		}
#if (BL_CTL==BL_CTL_GPIO)
		level = DIM_MIN - ((level - BL_MIN_LEVEL) * (DIM_MIN - DIM_MAX)) / (BL_MAX_LEVEL - BL_MIN_LEVEL);	
		aml_set_reg32_bits(P_LED_PWM_REG0, level, 0, 4);	
#elif (BL_CTL==BL_CTL_PWM)
		level = (PWM_MAX - PWM_MIN) * (level - BL_MIN_LEVEL) / (BL_MAX_LEVEL - BL_MIN_LEVEL) + PWM_MIN;	
		aml_write_reg32(P_PWM_PWM_D, (level << 16) | (PWM_CNT - level));  //pwm	duty	
#endif
		if (bl_status == OFF) 
			backlight_power_ctrl(ON);		
	} 
}
Пример #14
0
void tx_irq_handle(void)
{
    unsigned tx_status = aocec_rd_reg(CEC_TX_MSG_STATUS);
    switch (tx_status)
    {
        case TX_DONE:
            aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
            break;
        case TX_BUSY:
            aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT);
            aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
            break;
        case TX_ERROR:
            if (cec_msg_dbg_en  == 1)
                hdmi_print(INF, CEC "TX ERROR!!!\n");
            if (RX_ERROR == aocec_rd_reg(CEC_RX_MSG_STATUS))
            {
                cec_hw_reset();
            }
            else
            {
                aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
            }
            //aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
            break;
        default:
        break;
    }
    aml_write_reg32(P_AO_CEC_INTR_CLR, aml_read_reg32(P_AO_CEC_INTR_CLR) | (1 << 1));
    //aml_write_reg32(P_AO_CEC_INTR_MASKN, aml_read_reg32(P_AO_CEC_INTR_MASKN) | (1 << 2));
}
Пример #15
0
void meson_common_restart(char mode,const char *cmd)
{
    u32 reboot_reason = MESON_NORMAL_BOOT;
    if (cmd) {
        if (strcmp(cmd, "charging_reboot") == 0)
            reboot_reason = MESON_CHARGING_REBOOT;
        else if (strcmp(cmd, "update") == 0)
            reboot_reason = MESON_UPDATE_REBOOT;
        else if (strcmp(cmd, "report_crash") == 0)
            reboot_reason = MESON_CRASH_REBOOT;
        else if (strcmp(cmd, "factory_testl_reboot") == 0)
            reboot_reason = MESON_FACTORY_TEST_REBOOT;
        else if (strcmp(cmd, "switch_system") == 0)
            reboot_reason = MESON_SYSTEM_SWITCH_REBOOT;
        else if (strcmp(cmd, "safe_mode") == 0)
            reboot_reason = MESON_SAFE_REBOOT;
        else if (strcmp(cmd, "lock_system") == 0)
            reboot_reason = MESON_LOCK_REBOOT;
        else if (strcmp(cmd, "usb_burner_reboot") == 0)
            reboot_reason = MESON_USB_BURNER_REBOOT;
        else if (strcmp(cmd, "uboot_suspend") == 0)
            reboot_reason = MESON_UBOOT_SUSPEND;
        else if (strcmp(cmd, "androidv2") == 0)
           reboot_reason  = MESON_REBOOT_ANDROIDV2;
	}
    aml_write_reg32(P_AO_RTI_STATUS_REG1, reboot_reason);
    printk("reboot_reason(0x%x) = 0x%x\n", P_AO_RTI_STATUS_REG1, aml_read_reg32(P_AO_RTI_STATUS_REG1));
	arch_reset(mode,cmd);
}
Пример #16
0
static void set_backlight_level(unsigned level)
{
	mutex_lock(&bl_level_mutex);
	PRINT_INFO(KERN_INFO "set_backlight_level: %u, last level: %u\n", level, bl_level);
	level = (level > BL_MAX_LEVEL ? BL_MAX_LEVEL : (level < BL_MIN_LEVEL ? 0 : level));	
	bl_level = level;    

	if ((level == 0) && (bl_status == ON)) {
		_power_off_backlight();		
	}
	else {	
		if (level > BL_MID_LEVEL) {
			level = ((level - BL_MID_LEVEL)*(BL_MAX_LEVEL-BL_MAPPED_MID_LEVEL))/(BL_MAX_LEVEL - BL_MID_LEVEL) + BL_MAPPED_MID_LEVEL; 
		} else {
			//level = (level*BL_MAPPED_MID_LEVEL)/BL_MID_LEVEL;
			level = ((level - BL_MIN_LEVEL)*(BL_MAPPED_MID_LEVEL - BL_MIN_LEVEL))/(BL_MID_LEVEL - BL_MIN_LEVEL) + BL_MIN_LEVEL; 
		}
#if (BL_CTL==BL_CTL_GPIO)
		level = DIM_MIN - ((level - BL_MIN_LEVEL) * (DIM_MIN - DIM_MAX)) / (BL_MAX_LEVEL - BL_MIN_LEVEL);	
		aml_set_reg32_bits(P_LED_PWM_REG0, level, 0, 4);	
#elif (BL_CTL==BL_CTL_PWM)
		level = (PWM_MAX - PWM_MIN) * (level - BL_MIN_LEVEL) / (BL_MAX_LEVEL - BL_MIN_LEVEL) + PWM_MIN;	
		aml_write_reg32(P_PWM_PWM_D, (level << 16) | (PWM_CNT - level));  //pwm	duty	
#endif
		if (bl_status == ON) 
			_power_on_backlight();		
	} 
	PRINT_INFO(KERN_INFO "set_backlight_level finished\n");
	mutex_unlock(&bl_level_mutex);
}
Пример #17
0
int reset_rdma(void)
{
	item_count=0;
	memset(rdma_table, 0x0, TABLE_SIZE);
	aml_write_reg32(END_ADDR,(table_paddr + item_count*8-1));
	return 0;
}
Пример #18
0
/*as use the spin_lock,
 *1--there is no sleep,
 *2--it is better to shorter the time,
 */
int amcsi_isr(struct tvin_frontend_s *fe, unsigned int hcnt)
{
        struct amcsi_dev_s *devp = container_of(fe, amcsi_dev_t, frontend);
        unsigned data1 = 0;
        unsigned data2 = 0;
        am_csi2_frame_t frame;

        frame.w = aml_get_reg32_bits( P_CSI2_PIC_SIZE_STAT, 0, 16);
        frame.h = aml_get_reg32_bits( P_CSI2_PIC_SIZE_STAT, 16,16);
        frame.err = aml_read_reg32( P_CSI2_ERR_STAT0 );
        data1 = aml_read_reg32( P_CSI2_DATA_TYPE_IN_MEM);
        data2 = aml_read_reg32( P_CSI2_GEN_STAT0);

        if(frame.err){
                mipi_error("%s,error---pixel cnt:%d, line cnt:%d. error state:0x%x.mem type:0x%x, status:0x%x\n",
                                __func__, frame.w, frame.h, frame.err, data1, data2);
                devp->overflow_cnt ++;
                aml_write_reg32( P_CSI2_ERR_STAT0, 0);
        }
        if( devp->overflow_cnt > 4){
                DPRINT("should reset mipi\n");
                devp->overflow_cnt = 0;
                return 0;
        }
        devp->reset = 0;

        return 0;
}
Пример #19
0
static  inline void  setup_color_mode(const color_bit_define_t *color,u32  reg)
{
	u32  data32;

	data32 = aml_read_reg32(reg)&(~(0xf<<8));
	data32 |=  color->hw_blkmode<< 8; /* osd_blk_mode */
	aml_write_reg32(reg, data32);
}
Пример #20
0
int set_hpll_pll(int hpll_clk, int hpll_od,int hdmi_pll_cntl5)
{
//===============================
//out off pll clock
//===============================
	aml_write_reg32(P_HHI_HDMI_PLL_CNTL, hpll_clk);
	aml_write_reg32(P_HHI_HDMI_PLL_CNTL2,hpll_od);
	aml_write_reg32(P_HHI_HDMI_PLL_CNTL5,hdmi_pll_cntl5);

	aml_write_reg32(P_HHI_HDMI_PLL_CNTL, hpll_clk & (~(1<<28)));
	//aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL2,od1,18,2); //no used ,bit[18:19]

	//printf("Wait 10us for phy_clk stable!\n");
	udelay(10); // delay 10uS to wait clock is stable

	return 0;
}
Пример #21
0
int cec_ll_rx( unsigned char *msg, unsigned char *len)
{
    int i;
    int ret = -1;
    int pos;

    if ((RX_DONE != aocec_rd_reg(CEC_RX_MSG_STATUS)) || (1 != aocec_rd_reg(CEC_RX_NUM_MSG)))
    {
        //cec_rx_buf_check();
        aml_write_reg32(P_AO_CEC_INTR_CLR, aml_read_reg32(P_AO_CEC_INTR_CLR) | (1 << 2));
        aocec_wr_reg(CEC_RX_MSG_CMD,  RX_ACK_CURRENT);
        aocec_wr_reg(CEC_RX_MSG_CMD,  RX_NO_OP);
        return ret;
    }

    *len = aocec_rd_reg(CEC_RX_MSG_LENGTH) + 1;

    for (i = 0; i < (*len) && i < MAX_MSG; i++)
    {
        msg[i]= aocec_rd_reg(CEC_RX_MSG_0_HEADER +i);
    }

    ret = aocec_rd_reg(CEC_RX_MSG_STATUS);

    if (cec_msg_dbg_en  == 1)
    {
        pos = 0;
        pos += sprintf(msg_log_buf + pos, "CEC: rx msg len: %d   dat: ", *len);
        for (i = 0; i < (*len); i++)
        {
            pos += sprintf(msg_log_buf + pos, "%02x ", msg[i]);
        }
        pos += sprintf(msg_log_buf + pos, "\n");
        msg_log_buf[pos] = '\0';
        hdmi_print(INF, CEC "%s", msg_log_buf);
    }

    //cec_rx_buf_check();
    aml_write_reg32(P_AO_CEC_INTR_CLR, aml_read_reg32(P_AO_CEC_INTR_CLR) | (1 << 2));
    aocec_wr_reg(CEC_RX_MSG_CMD,  RX_ACK_CURRENT);
    aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
    //aml_write_reg32(P_AO_CEC_INTR_CLR, aml_read_reg32(P_AO_CEC_INTR_CLR) | (1 << 2));

    return ret;
}
Пример #22
0
static int aml_wtd_reboot_notify(struct notifier_block *nb, unsigned long event,
                                 void *dummy)
{
    if (event == SYS_POWER_OFF) {
        printk("set watch dog shut down timeout %d seconds\n",awdtv->suspend_timeout);
        aml_write_reg32(P_AO_RTI_STATUS_REG1, MESON_CHARGING_REBOOT);
    }
    return NOTIFY_OK;
}
Пример #23
0
static inline void _disable_display_driver(Lcd_Config_t *pConf)
{
	int vclk_sel;

	vclk_sel = 0;//((pConf->lcd_timing.clk_ctrl) >>4) & 0x1;

	aml_set_reg32_bits(P_HHI_VIID_DIVIDER_CNTL, 0, 11, 1);	//close lvds phy clk gate: 0x104c[11]

	aml_write_reg32(P_ENCT_VIDEO_EN, 0);	//disable enct
	aml_write_reg32(P_ENCL_VIDEO_EN, 0);	//disable encl

	if (vclk_sel)
		aml_set_reg32_bits(P_HHI_VIID_CLK_CNTL, 0, 0, 5);		//close vclk2 gate: 0x104b[4:0]
	else
		aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 0, 0, 5);		//close vclk1 gate: 0x105f[4:0]

	printf("disable lcd display driver.\n");
}
Пример #24
0
// DON'T EDID BELOW TWO FUNCTIONS
void config_tv_enc(tvmode_t tvmode)
{
    int i;
    const struct enc_reg_set *reg;
    for(i = 0; i < sizeof(enc_regs_array) / sizeof(struct enc_reg_map); i++) {
        if(tvmode == enc_regs_array[i].tvmode) {
            reg = enc_regs_array[i].set;
            while(reg->addr != MREG_END_MARKER) {
                aml_write_reg32(reg->addr, reg->val);
                reg ++;
            }
            aml_write_reg32(P_VENC_VDAC_SETTING, 0xff);     // turn off vdac, hdmitx no need this
            return;
        }
    }
    aml_write_reg32(P_VENC_VDAC_SETTING, 0xff);     // turn off vdac, hdmitx no need this
    printk("not find output_type %d\n", tvmode);
} /* config_tv_enc */
Пример #25
0
void vclk_set_encl_lvds(vmode_t vmode, int lvds_ports)
{
	int hdmi_clk_out;
	//int hdmi_vx1_clk_od1;
	int vx1_phy_div;
	int encl_div;
	unsigned int xd;
	//no used, od2 must >= od3.
	//hdmi_vx1_clk_od1 = 1; //OD1 always 1

	if (lvds_ports<2) {
		//pll_video.pl 3500 pll_out
		switch (vmode) {
			case VMODE_1080P: //total: 2200x1125 pixel clk = 148.5MHz,phy_clk(s)=(pclk*7)= 1039.5 = 2079/2
			case VMODE_1080P_50HZ:
				hdmi_clk_out = 2079;
				vx1_phy_div  = 2/2;
				encl_div     = vx1_phy_div*7;
				break;
			default:
				printf("Error video format!\n");
				return;
		}
		//if(set_hdmi_dpll(hdmi_clk_out,hdmi_vx1_clk_od1)) {
		if (set_hdmi_dpll(hdmi_clk_out,0)) {
			printf("Unsupported HDMI_DPLL out frequency!\n");
			return;
		}

		if (lvds_ports == 1) //dual port
			vx1_phy_div = vx1_phy_div*2;
	}else if (lvds_ports >= 2) {
		printf("Quad-LVDS is not supported!\n");
		return;
	}

	//configure vid_clk_div_top
	if ((encl_div%14) == 0) {//7*even
		clocks_set_vid_clk_div(CLK_UTIL_VID_PLL_DIV_14);
		xd = encl_div/14;
	}else if ((encl_div%7) == 0) { //7*odd
		clocks_set_vid_clk_div(CLK_UTIL_VID_PLL_DIV_7);
		xd = encl_div/7;
	}else { //3.5*odd
		clocks_set_vid_clk_div(CLK_UTIL_VID_PLL_DIV_3p5);
		xd = encl_div/3.5;
	}
	//for lvds phy clock and enable decoupling FIFO
	aml_write_reg32(P_HHI_LVDS_TX_PHY_CNTL1,((3<<6)|((vx1_phy_div-1)<<1)|1)<<24);

	//config lvds phy
	lvds_phy_config(0);
	//configure crt_video
	set_crt_video_enc(0,0,xd);  //configure crt_video V1: inSel=vid_pll_clk(0),DivN=xd)
	enable_crt_video_encl(1,0); //select and enable the output
}
Пример #26
0
static int stop_rdma(char channel)
{
	char intr_bit=8*channel;
	u32 data32 = 0x0;

	data32  = aml_read_reg32(P_RDMA_ACCESS_AUTO);
	data32 &= ~(0x1 << intr_bit);   // [23: 16] interrupt inputs enable mask for auto-start 1: vsync int bit 0
	aml_write_reg32(P_RDMA_ACCESS_AUTO, data32);
	return 0;
}
Пример #27
0
static void set_tcon_vbyone(Lcd_Config_t *pConf)
{
	//Lcd_Timing_t *tcon_adr = &(pConf->lcd_timing);
	vpp_set_matrix_ycbcr2rgb(2, 0);
	aml_write_reg32(P_ENCL_VIDEO_RGBIN_CTRL, 3);
	aml_write_reg32(P_L_RGB_BASE_ADDR, 0);
	aml_write_reg32(P_L_RGB_COEFF_ADDR, 0x400);
	//aml_write_reg32(P_L_POL_CNTL_ADDR,  3)
	//aml_write_reg32(P_L_DUAL_PORT_CNTL_ADDR, (0x1 << LCD_TTL_SEL));
	//	if(pConf->lcd_basic.lcd_bits == 8)
	//		aml_write_reg32(P_L_DITH_CNTL_ADDR,  0x400);
	//	else if(pConf->lcd_basic.lcd_bits == 6)
	//		aml_write_reg32(P_L_DITH_CNTL_ADDR,  0x600);
	//	else
	//		aml_write_reg32(P_L_DITH_CNTL_ADDR,  0);
	//PRINT_INFO("final LVDS_FIFO_CLK = %d\n", clk_util_clk_msr(24));
	//PRINT_INFO("final cts_encl_clk = %d\n", clk_util_clk_msr(9));
	aml_write_reg32(P_VPP_MISC, aml_read_reg32(P_VPP_MISC) & ~(VPP_OUT_SATURATE));
}
void hdmi_wr_reg(unsigned long addr, unsigned long data)
{
    unsigned long rd_data;
    
    check_cts_hdmi_sys_clk_status();
//    WRITE_APB_REG(HDMI_ADDR_PORT, addr);
//    WRITE_APB_REG(HDMI_ADDR_PORT, addr);
//    
//    WRITE_APB_REG(HDMI_DATA_PORT, data);
    aml_write_reg32(P_HDMI_ADDR_PORT, addr);
    aml_write_reg32(P_HDMI_ADDR_PORT, addr);
    
    aml_write_reg32(P_HDMI_DATA_PORT, data);
    rd_data = hdmi_rd_reg (addr);
    if (rd_data != data) 
    {
        //printk("hdmi_wr_reg(%x,%x) fails to write: %x\n",addr, data, rd_data);
       //while(1){};      
    }
}
Пример #29
0
static int  update_table_item(u32 addr,u32 val)
{
	if(item_count > (MAX_TABLE_ITEM-1)) return -1;

	//new comer,then add it .
	rdma_table[item_count].addr=addr;
	rdma_table[item_count].val=val;
	item_count++;
	aml_write_reg32(END_ADDR,(table_paddr + item_count*8-1));
	return 0;
}