static int
ata_via_ch_attach(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
/* newer SATA chips has resources in one BAR for each channel */
if (ctlr->chip->cfg2 & VIABAR) {
struct resource *r_io;
int i, rid;
ata_pci_dmainit(dev);
rid = PCIR_BAR(ch->unit);
if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
SYS_RES_IOPORT,
&rid, RF_ACTIVE)))
return ENXIO;
for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
ch->r_io[i].res = r_io;
ch->r_io[i].offset = i;
}
ch->r_io[ATA_CONTROL].res = r_io;
ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
ch->r_io[ATA_IDX_ADDR].res = r_io;
ata_default_registers(dev);
for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
ch->r_io[i].res = ctlr->r_res1;
ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
}
ata_pci_hw(dev);
if (ch->unit >= 2)
return 0;
}
else {
/* setup the usual register normal pci style */
if (ata_pci_ch_attach(dev))
return ENXIO;
}
ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
ch->r_io[ATA_SERROR].res = ctlr->r_res2;
ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
ch->hw.status = ata_via_status;
ch->flags |= ATA_NO_SLAVE;
ch->flags |= ATA_SATA;
ch->flags |= ATA_PERIODIC_POLL;
ata_sata_scr_write(ch, -1, ATA_SERROR, 0xffffffff);
return 0;
}
static int
ata_sii_ch_attach(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
int i;
for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
ch->r_io[i].res = ctlr->r_res2;
ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
}
ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
ata_default_registers(dev);
ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
if (ctlr->chip->max_dma >= ATA_SA150) {
ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
ch->r_io[ATA_SERROR].res = ctlr->r_res2;
ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
ch->flags |= ATA_NO_SLAVE;
ch->flags |= ATA_SATA;
ch->flags |= ATA_KNOWN_PRESENCE;
/* enable PHY state change interrupt */
ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
}
if (ctlr->chip->cfg2 & SII_BUG) {
/* work around errata in early chips */
ch->dma.boundary = 8192;
ch->dma.segsize = 15 * DEV_BSIZE;
}
ata_pci_hw(dev);
ch->hw.status = ata_sii_status;
if (ctlr->chip->cfg2 & SII_SETCLK)
ch->flags |= ATA_CHECKS_CABLE;
ata_pci_dmainit(dev);
return 0;
}
static int
ata_via_ch_attach(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
/* newer SATA chips has resources in one BAR for each channel */
if (ctlr->chip->cfg2 & VIABAR) {
struct resource *r_io;
int i, rid;
ata_pci_dmainit(dev);
rid = PCIR_BAR(ch->unit);
if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
SYS_RES_IOPORT,
&rid, RF_ACTIVE)))
return ENXIO;
for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
ch->r_io[i].res = r_io;
ch->r_io[i].offset = i;
}
ch->r_io[ATA_CONTROL].res = r_io;
ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
ch->r_io[ATA_IDX_ADDR].res = r_io;
ata_default_registers(dev);
for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
ch->r_io[i].res = ctlr->r_res1;
ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
}
ata_pci_hw(dev);
if (ch->unit >= 2)
return 0;
}
else {
/* setup the usual register normal pci style */
if (ata_pci_ch_attach(dev))
return ENXIO;
}
ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
ch->r_io[ATA_SERROR].res = ctlr->r_res2;
ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
ch->flags |= ATA_NO_SLAVE;
ch->flags |= ATA_SATA;
/* XXX SOS PHY hotplug handling missing in VIA chip ?? */
/* XXX SOS unknown how to enable PHY state change interrupt */
return 0;
}
static int
ata_ali_sata_ch_attach(device_t dev)
{
device_t parent = device_get_parent(dev);
struct ata_pci_controller *ctlr = device_get_softc(parent);
struct ata_channel *ch = device_get_softc(dev);
struct ali_sata_resources *res;
struct resource *io = NULL, *ctlio = NULL;
int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
int i;
res = ctlr->chipset_data;
if (unit01) {
io = res->bars[2];
ctlio = res->bars[3];
} else {
io = res->bars[0];
ctlio = res->bars[1];
}
ata_pci_dmainit(dev);
for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
ch->r_io[i].res = io;
ch->r_io[i].offset = i + (unit10 ? 8 : 0);
}
ch->r_io[ATA_CONTROL].res = ctlio;
ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
ch->r_io[ATA_IDX_ADDR].res = io;
ata_default_registers(dev);
if (ctlr->r_res1) {
for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
ch->r_io[i].res = ctlr->r_res1;
ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
}
}
ch->flags |= ATA_NO_SLAVE;
ch->flags |= ATA_SATA;
/* XXX SOS PHY handling awkward in ALI chip not supported yet */
ata_pci_hw(dev);
return 0;
}
int
ata_pci_ch_attach(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
struct resource *io = NULL, *ctlio = NULL;
int i, rid;
rid = ATA_IOADDR_RID;
if (!(io = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE)))
return ENXIO;
rid = ATA_CTLADDR_RID;
if (!(ctlio = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,RF_ACTIVE))){
bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io);
return ENXIO;
}
ata_pci_dmainit(dev);
for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
ch->r_io[i].res = io;
ch->r_io[i].offset = i;
}
ch->r_io[ATA_CONTROL].res = ctlio;
ch->r_io[ATA_CONTROL].offset = ctlr->legacy ? 0 : 2;
ch->r_io[ATA_IDX_ADDR].res = io;
ata_default_registers(dev);
if (ctlr->r_res1) {
for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
ch->r_io[i].res = ctlr->r_res1;
ch->r_io[i].offset = (i - ATA_BMCMD_PORT) + (ch->unit*ATA_BMIOSIZE);
}
}
ata_pci_hw(dev);
return 0;
}
static int
imx_ata_ch_attach(device_t dev)
{
struct ata_pci_controller *ctrl;
struct ata_channel *ch;
int i;
ctrl = device_get_softc(device_get_parent(dev));
ch = device_get_softc(dev);
for (i = ATA_DATA; i < ATA_MAX_RES; i++)
ch->r_io[i].res = ctrl->r_res1;
bus_write_2(ctrl->r_res1, 0x24, 0x80);
DELAY(100);
bus_write_2(ctrl->r_res1, 0x24, 0xc0);
DELAY(100);
/* Write TIME_OFF/ON/1/2W */
bus_write_1(ctrl->r_res1, 0x00, 3);
bus_write_1(ctrl->r_res1, 0x01, 3);
bus_write_1(ctrl->r_res1, 0x02, (25 + 15) / 15);
bus_write_1(ctrl->r_res1, 0x03, (70 + 15) / 15);
/* Write TIME_2R/AX/RDX/4 */
bus_write_1(ctrl->r_res1, 0x04, (70 + 15) / 15);
bus_write_1(ctrl->r_res1, 0x05, (50 + 15) / 15 + 2);
bus_write_1(ctrl->r_res1, 0x06, 1);
bus_write_1(ctrl->r_res1, 0x07, (10 + 15) / 15);
/* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */
bus_write_1(ctrl->r_res1, 0x08, (10 + 15) / 15);
bus_write_2(ctrl->r_res1, 0x24, 0xc1);
DELAY(30000);
/* setup ATA registers */
ch->r_io[ATA_DATA ].offset = 0xa0;
ch->r_io[ATA_FEATURE].offset = 0xa4;
ch->r_io[ATA_ERROR ].offset = 0xa4;
ch->r_io[ATA_COUNT ].offset = 0xa8;
ch->r_io[ATA_SECTOR ].offset = 0xac;
ch->r_io[ATA_CYL_LSB].offset = 0xb0;
ch->r_io[ATA_CYL_MSB].offset = 0xb4;
ch->r_io[ATA_DRIVE ].offset = 0xb8;
ch->r_io[ATA_COMMAND].offset = 0xbc;
ch->r_io[ATA_STATUS ].offset = 0xbc;
ch->r_io[ATA_ALTSTAT].offset = 0xd8;
ch->r_io[ATA_CONTROL].offset = 0xd8;
ata_pci_hw(dev);
ch->flags |= ATA_NO_SLAVE;
ch->flags |= ATA_USE_16BIT;
ch->flags |= ATA_CHECKS_CABLE;
ch->flags |= ATA_KNOWN_PRESENCE;
/* Clear pending interrupts. */
bus_write_2(ctrl->r_res1, 0x28, 0xf8);
/* Enable all, but Idle interrupts. */
bus_write_2(ctrl->r_res1, 0x2c, 0x88);
return 0;
}