void au1000_halt(void) { #if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550) /* Power off system */ printk(KERN_NOTICE "\n** Powering off...\n"); au_writew(au_readw(0xAF00001C) | (3 << 14), 0xAF00001C); au_sync(); while (1); /* should not get here */ #else printk(KERN_NOTICE "\n** You can safely turn off the power\n"); #ifdef CONFIG_MIPS_MIRAGE au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT); #endif #ifdef CONFIG_MIPS_DB1200 au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C); #endif #ifdef CONFIG_PM au_sleep(); /* Should not get here */ printk(KERN_ERR "Unable to put CPU in sleep mode\n"); while (1); #else while (1) __asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0"); #endif #endif /* defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550) */ }
static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask) { u32 val = au_readl(HOST_CONFIG(host)); val &= ~mask; au_writel(val, HOST_CONFIG(host)); au_sync(); }
static void au1xxx_stop_hc(struct platform_device *dev) { printk(KERN_DEBUG __FILE__ ": stopping Au1xxx OHCI USB Controller\n"); /* Disable clock */ au_writel(readl((void *)USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG); }
void __init board_setup(void) { u32 pin_func; /* Enable PSC1 SYNC for AC97. Normaly done in audio driver, * but it is board specific code, so put it here. */ pin_func = au_readl(SYS_PINFUNC); au_sync(); pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; au_writel(pin_func, SYS_PINFUNC); au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */ au_sync(); printk("AMD Alchemy Pb1550 Board\n"); }
void __init board_setup(void) { #ifdef CONFIG_SERIAL_8250_CONSOLE char *argptr; argptr = prom_getcmdline(); argptr = strstr(argptr, "console="); if (argptr == NULL) { argptr = prom_getcmdline(); strcat(argptr, " console=ttyS0,115200"); } #endif alchemy_gpio2_enable(); #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) /* Enable USB power switch */ alchemy_gpio_direction_output(204, 0); #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ #ifdef CONFIG_PCI #if defined(__MIPSEB__) au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); #else au_writel(0xf, Au1500_PCI_CFG); #endif #endif /* Initialize sys_pinfunc */ au_writel(SYS_PF_NI2, SYS_PINFUNC); /* Initialize GPIO */ au_writel(0xFFFFFFFF, SYS_TRIOUTCLR); alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */ alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */ alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */ alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */ /* Enable LED and set it to green */ alchemy_gpio_direction_output(211, 1); /* green on */ alchemy_gpio_direction_output(212, 0); /* red off */ board_pci_idsel = mtx1_pci_idsel; printk(KERN_INFO "4G Systems MTX-1 Board\n"); }
static void mtx1_wdt_start(void) { if (!mtx1_wdt_device.queue) { mtx1_wdt_device.queue = 1; au_writel (au_readl(GPIO2_DIR) | (u32)(1<<15), GPIO2_DIR); mod_timer(&mtx1_wdt_device.timer, jiffies + MTX1_WDT_INTERVAL); } mtx1_wdt_device.running++; }
/* init button hardware */ static int button_hw_init(void) { unsigned int ipinfunc=0; printk("au1200_ibutton.c: Initializing buttons hardware\n"); // initialize GPIO pin function assignments ipinfunc = au_readl(SYS_PINFUNC); ipinfunc &= ~(SYS_PINFUNC_DMA | SYS_PINFUNC_S0A | SYS_PINFUNC_S0B); au_writel( ipinfunc ,SYS_PINFUNC); ipinfunc |= (SYS_PINFUNC_S0C); au_writel( ipinfunc ,SYS_PINFUNC); return 0; }
static void au1xmmc_send_pio(struct au1xmmc_host *host) { struct mmc_data *data = 0; int sg_len, max, count = 0; unsigned char *sg_ptr; u32 status = 0; struct scatterlist *sg; data = host->mrq->data; if (!(host->flags & HOST_F_XMIT)) return; /* This is the pointer to the data buffer */ sg = &data->sg[host->pio.index]; sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset; /* This is the space left inside the buffer */ sg_len = data->sg[host->pio.index].length - host->pio.offset; /* Check to if we need less then the size of the sg_buffer */ max = (sg_len > host->pio.len) ? host->pio.len : sg_len; if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER; for(count = 0; count < max; count++ ) { unsigned char val; status = au_readl(HOST_STATUS(host)); if (!(status & SD_STATUS_TH)) break; val = *sg_ptr++; au_writel((unsigned long) val, HOST_TXPORT(host)); au_sync(); } host->pio.len -= count; host->pio.offset += count; if (count == sg_len) { host->pio.index++; host->pio.offset = 0; } if (host->pio.len == 0) { IRQ_OFF(host, SD_CONFIG_TH); if (host->flags & HOST_F_STOP) SEND_STOP(host); tasklet_schedule(&host->data_task); } }
static int __devexit au1xpsc_i2s_drvremove(struct platform_device *pdev) { struct au1xpsc_audio_data *wd = platform_get_drvdata(pdev); struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0); snd_soc_unregister_dai(&pdev->dev); au_writel(0, I2S_CFG(wd)); au_sync(); au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); au_sync(); iounmap(wd->mmio); release_mem_region(r->start, resource_size(r)); kfree(wd); return 0; }
static int xxs1500_pcmcia_configure_socket(const struct pcmcia_configure *configure) { if(configure->sock > PCMCIA_MAX_SOCK) return -1; DEBUG("Vcc %dV Vpp %dV, reset %d\n", configure->vcc, configure->vpp, configure->reset); switch(configure->vcc){ case 33: /* Vcc 3.3V */ /* turn on power */ DEBUG("turn on power\n"); au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<14))|(1<<30), GPIO2_OUTPUT); au_sync_delay(100); break; case 50: /* Vcc 5V */ default: /* what's this ? */ printk(KERN_ERR "au1x00_cs: unsupported VCC\n"); case 0: /* Vcc 0 */ /* turn off power */ au_sync_delay(100); au_writel(au_readl(GPIO2_PINSTATE) | (1<<14)|(1<<30), GPIO2_OUTPUT); break; } if (!configure->reset) { DEBUG("deassert reset\n"); au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<4))|(1<<20), GPIO2_OUTPUT); au_sync_delay(100); au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<5))|(1<<21), GPIO2_OUTPUT); } else { DEBUG("assert reset\n"); au_writel(au_readl(GPIO2_PINSTATE) | (1<<4)|(1<<20), GPIO2_OUTPUT); } au_sync_delay(100); return 0; }
/* * We read the real processor speed from the PLL. This is important * because it is more accurate than computing it from the 32KHz * counter, if it exists. If we don't have an accurate processor * speed, all of the peripherals that derive their clocks based on * this advertised speed will introduce error and sometimes not work * properly. This function is futher convoluted to still allow configurations * to do that in case they have really, really old silicon with a * write-only PLL register, that we need the 32KHz when power management * "wait" is enabled, and we need to detect if the 32KHz isn't present * but requested......got it? :-) -- Dan */ unsigned long cal_r4koff(void) { unsigned long cpu_speed; unsigned long flags; unsigned long counter; spin_lock_irqsave(&time_lock, flags); /* Power management cares if we don't have a 32KHz counter. */ no_au1xxx_32khz = 0; counter = au_readl(SYS_COUNTER_CNTRL); if (counter & SYS_CNTRL_E0) { int trim_divide = 16; au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); /* RTC now ticks at 32.768/16 kHz */ au_writel(trim_divide-1, SYS_RTCTRIM); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); au_writel (0, SYS_TOYWRITE); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; } else { /* The 32KHz oscillator isn't running, so assume there * isn't one and grab the processor speed from the PLL. * NOTE: some old silicon doesn't allow reading the PLL. */ cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; no_au1xxx_32khz = 1; } mips_hpt_frequency = cpu_speed; // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16)); spin_unlock_irqrestore(&time_lock, flags); return (cpu_speed / HZ); }
static int au1xpsc_ac97_resume(struct snd_soc_dai *dai) { au_writel(au1xpsc_ac97_workdata->pm[0] | PSC_SEL_PS_AC97MODE, PSC_SEL(au1xpsc_ac97_workdata)); au_sync(); return 0; }
/* This is just for debugging to set the timer for a sleep delay. */ void wakeup_counter0_set(int ticks) { unsigned long pc0; pc0 = au_readl(SYS_TOYREAD); last_pc0 = pc0; au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2); au_sync(); }
static void au1xxx_start_hc(struct platform_device *dev) { printk(KERN_DEBUG __FILE__ ": starting Au1xxx OHCI USB Controller\n"); /* enable host controller */ au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG); udelay(1000); au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG); udelay(1000); /* wait for reset complete (read register twice; see au1500 errata) */ while (au_readl(USB_HOST_CONFIG), !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD)) udelay(1000); printk(KERN_DEBUG __FILE__ ": Clock to USB host has been enabled \n"); }
int mtx1_pci_idsel(unsigned int devsel, int assert) { #define MTX_IDSEL_ONLY_0_AND_3 0 #if MTX_IDSEL_ONLY_0_AND_3 if (devsel != 0 && devsel != 3) { printk(KERN_ERR "*** not 0 or 3\n"); return 0; } #endif if (assert && devsel != 0) /* Suppress signal to Cardbus */ au_writel(0x00000002, SYS_OUTPUTCLR); /* set EXT_IO3 OFF */ else au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */ au_sync_udelay(1); return 1; }
static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) { struct mmc_request *mrq = host->mrq; struct mmc_data *data; u32 crc; WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP); if (host->mrq == NULL) return; data = mrq->cmd->data; if (status == 0) status = au_readl(HOST_STATUS(host)); /* The transaction is really over when the SD_STATUS_DB bit is clear */ while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB)) status = au_readl(HOST_STATUS(host)); data->error = MMC_ERR_NONE; dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir); /* Process any errors */ crc = (status & (SD_STATUS_WC | SD_STATUS_RC)); if (host->flags & HOST_F_XMIT) crc |= ((status & 0x07) == 0x02) ? 0 : 1; if (crc) data->error = MMC_ERR_BADCRC; /* Clear the CRC bits */ au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host)); data->bytes_xfered = 0; if (data->error == MMC_ERR_NONE) { if (host->flags & HOST_F_DMA) { u32 chan = DMA_CHANNEL(host); chan_tab_t *c = *((chan_tab_t **) chan); au1x_dma_chan_t *cp = c->chan_ptr; data->bytes_xfered = cp->ddma_bytecnt; } else data->bytes_xfered = (data->blocks * (1 << data->blksz_bits)) - host->pio.len; } au1xmmc_finish_request(host); }
static void auide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); switch (drive->dma_mode) { #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA case XFER_MW_DMA_2: mem_sttime = SBC_IDE_TIMING(MDMA2); /* set configuration for RCS2# */ mem_stcfg &= ~TS_MASK; mem_stcfg &= ~TCSOE_MASK; mem_stcfg &= ~TOECS_MASK; mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS; break; case XFER_MW_DMA_1: mem_sttime = SBC_IDE_TIMING(MDMA1); /* set configuration for RCS2# */ mem_stcfg &= ~TS_MASK; mem_stcfg &= ~TCSOE_MASK; mem_stcfg &= ~TOECS_MASK; mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS; break; case XFER_MW_DMA_0: mem_sttime = SBC_IDE_TIMING(MDMA0); /* set configuration for RCS2# */ mem_stcfg |= TS_MASK; mem_stcfg &= ~TCSOE_MASK; mem_stcfg &= ~TOECS_MASK; mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS; break; #endif } au_writel(mem_sttime,MEM_STTIME2); au_writel(mem_stcfg,MEM_STCFG2); }
static void au1xxx_stop_ohc(struct platform_device *dev) { printk(KERN_DEBUG __FILE__ ": stopping Au1xxx OHCI USB Controller\n"); #ifndef CONFIG_SOC_AU1200 /* Disable clock */ au_writel(au_readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG); #else /* Au1200 */ /* Disable mem */ au_writel(~USBH_DISABLE & au_readl(USB_HOST_CONFIG), USB_HOST_CONFIG); udelay(1000); /* Disable clock */ au_writel(~USBH_ENABLE_CE & au_readl(USB_HOST_CONFIG), USB_HOST_CONFIG); au_readl(USB_HOST_CONFIG); #endif /* Au1200 */ }
static inline void mask_and_ack_level_irq(unsigned int irq_nr) { local_disable_irq(irq_nr); au_sync(); #if defined(CONFIG_MIPS_PB1000) if (irq_nr == AU1000_GPIO_15) { au_writel(0x8000, PB1000_MDR); /* ack int */ au_sync(); } #endif }
static void au1xmmc_send_pio(struct au1xmmc_host *host) { struct mmc_data *data; int sg_len, max, count; unsigned char *sg_ptr, val; u32 status; struct scatterlist *sg; data = host->mrq->data; if (!(host->flags & HOST_F_XMIT)) return; sg = &data->sg[host->pio.index]; sg_ptr = sg_virt(sg) + host->pio.offset; sg_len = data->sg[host->pio.index].length - host->pio.offset; max = (sg_len > host->pio.len) ? host->pio.len : sg_len; if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER; for (count = 0; count < max; count++) { status = au_readl(HOST_STATUS(host)); if (!(status & SD_STATUS_TH)) break; val = *sg_ptr++; au_writel((unsigned long)val, HOST_TXPORT(host)); au_sync(); } host->pio.len -= count; host->pio.offset += count; if (count == sg_len) { host->pio.index++; host->pio.offset = 0; } if (host->pio.len == 0) { IRQ_OFF(host, SD_CONFIG_TH); if (host->flags & HOST_F_STOP) SEND_STOP(host); tasklet_schedule(&host->data_task); } }
static int mtx1_wdt_stop(void) { if (mtx1_wdt_device.queue) { mtx1_wdt_device.queue = 0; au_writel (au_readl(GPIO2_DIR) & ~((u32)(1<<15)), GPIO2_DIR); } ticks = mtx1_wdt_device.default_ticks; return 0; }
static void au1xxx_start_ohc(struct platform_device *dev) { printk(KERN_DEBUG __FILE__ ": starting Au1xxx OHCI USB Controller\n"); /* enable host controller */ #ifndef CONFIG_SOC_AU1200 au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG); udelay(1000); au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG); udelay(1000); #else /* Au1200 */ /* write HW defaults again in case Yamon cleared them */ if (au_readl(USB_HOST_CONFIG) == 0) { au_writel(0x00d02000, USB_HOST_CONFIG); au_readl(USB_HOST_CONFIG); udelay(1000); } au_writel(USBH_ENABLE_CE | au_readl(USB_HOST_CONFIG), USB_HOST_CONFIG); au_readl(USB_HOST_CONFIG); udelay(1000); au_writel(USBH_ENABLE_INIT | au_readl(USB_HOST_CONFIG), USB_HOST_CONFIG); au_readl(USB_HOST_CONFIG); udelay(1000); #endif /* Au1200 */ #ifndef CONFIG_SOC_AU1200 /* wait for reset complete (read register twice; see au1500 errata) */ while (au_readl(USB_HOST_CONFIG), !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD)) #endif udelay(1000); printk(KERN_DEBUG __FILE__ ": Clock to USB host has been enabled \n"); }
static void end_irq(unsigned int irq_nr) { if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) { local_enable_irq(irq_nr); } #if defined(CONFIG_MIPS_PB1000) if (irq_nr == AU1000_GPIO_15) { au_writel(0x4000, PB1000_MDR); /* enable int */ au_sync(); } #endif }
static int au1xtoy_rtc_probe(struct platform_device *pdev) { struct rtc_device *rtcdev; unsigned long t; int ret; t = au_readl(SYS_COUNTER_CNTRL); if (!(t & CNTR_OK)) { dev_err(&pdev->dev, "counters not working; aborting.\n"); ret = -ENODEV; goto out_err; } ret = -ETIMEDOUT; /* set counter0 tickrate to 1Hz if necessary */ if (au_readl(SYS_TOYTRIM) != 32767) { /* wait until hardware gives access to TRIM register */ t = 0x00100000; while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S) && --t) msleep(1); if (!t) { /* timed out waiting for register access; assume * counters are unusable. */ dev_err(&pdev->dev, "timeout waiting for access\n"); goto out_err; } /* set 1Hz TOY tick rate */ au_writel(32767, SYS_TOYTRIM); au_sync(); } /* wait until the hardware allows writes to the counter reg */ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S) msleep(1); rtcdev = devm_rtc_device_register(&pdev->dev, "rtc-au1xxx", &au1xtoy_rtc_ops, THIS_MODULE); if (IS_ERR(rtcdev)) { ret = PTR_ERR(rtcdev); goto out_err; } platform_set_drvdata(pdev, rtcdev); return 0; out_err: return ret; }
static void au1xxx_start_ehc(struct platform_device *dev) { pr_debug(__FILE__ ": starting Au1xxx EHCI USB Controller\n"); /* write HW defaults again in case Yamon cleared them */ if (au_readl(USB_HOST_CONFIG) == 0) { au_writel(0x00d02000, USB_HOST_CONFIG); au_readl(USB_HOST_CONFIG); udelay(1000); } /* enable host controller */ au_writel(USBH_ENABLE_CE | au_readl(USB_HOST_CONFIG), USB_HOST_CONFIG); au_readl(USB_HOST_CONFIG); udelay(1000); au_writel(USBH_ENABLE_INIT | au_readl(USB_HOST_CONFIG), USB_HOST_CONFIG); au_readl(USB_HOST_CONFIG); udelay(1000); pr_debug(__FILE__ ": Clock to USB host has been enabled\n"); }
static int au1x_rtcmatch2_set_next_event(unsigned long delta, struct clock_event_device *cd) { delta += au_readl(SYS_RTCREAD); /* wait for register access */ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21) ; au_writel(delta, SYS_RTCMATCH2); au_sync(); return 0; }
int mtx1_pci_idsel(unsigned int devsel, int assert) { #define MTX_IDSEL_ONLY_0_AND_3 0 #if MTX_IDSEL_ONLY_0_AND_3 if (devsel != 0 && devsel != 3) { printk("*** not 0 or 3\n"); return 0; } #endif if (assert && devsel != 0) { // suppress signal to cardbus au_writel( 0x00000002, SYS_OUTPUTCLR ); // set EXT_IO3 OFF } else { au_writel( 0x00000002, SYS_OUTPUTSET ); // set EXT_IO3 ON } au_sync_udelay(1); return 1; }
void __init board_setup(void) { u32 pin_func; pm_power_off = xxs1500_power_off; _machine_halt = xxs1500_power_off; _machine_restart = xxs1500_reset; alchemy_gpio1_input_enable(); alchemy_gpio2_enable(); /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */ pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3; pin_func |= SYS_PF_UR3; au_writel(pin_func, SYS_PINFUNC); /* Enable UART */ au_writel(0x01, UART3_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */ mdelay(10); au_writel(0x03, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */ mdelay(10); /* Enable DTR = USB power up */ au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */ #ifdef CONFIG_PCI #if defined(__MIPSEB__) au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); #else au_writel(0xf, Au1500_PCI_CFG); #endif #endif }
/* * Figure out the r4k offset, the amount to increment the compare * register for each time tick. * Use the Programmable Counter 1 to do this. */ unsigned long cal_r4koff(void) { unsigned long count; unsigned long cpu_speed; unsigned long start, end; unsigned long counter; int trim_divide = 16; unsigned long flags; spin_lock_irqsave(&time_lock, flags); counter = au_readl(SYS_COUNTER_CNTRL); au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); au_writel(trim_divide-1, SYS_RTCTRIM); /* RTC now ticks at 32.768/16 kHz */ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); au_writel (0, SYS_TOYWRITE); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); start = au_readl(SYS_RTCREAD); start += 2; /* wait for the beginning of a new tick */ while (au_readl(SYS_RTCREAD) < start); /* Start r4k counter. */ write_c0_count(0); end = start + (32768 / trim_divide)/2; /* wait 0.5 seconds */ while (end > au_readl(SYS_RTCREAD)); count = read_c0_count(); cpu_speed = count * 2; mips_counter_frequency = count; set_au1x00_uart_baud_base(((cpu_speed) / 4) / 16); spin_unlock_irqrestore(&time_lock, flags); return (cpu_speed / HZ); }
static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) { struct mmc_request *mrq = host->mrq; struct mmc_data *data; u32 crc; WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP)); if (host->mrq == NULL) return; data = mrq->cmd->data; if (status == 0) status = au_readl(HOST_STATUS(host)); while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB)) status = au_readl(HOST_STATUS(host)); data->error = 0; dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir); crc = (status & (SD_STATUS_WC | SD_STATUS_RC)); if (host->flags & HOST_F_XMIT) crc |= ((status & 0x07) == 0x02) ? 0 : 1; if (crc) data->error = -EILSEQ; au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host)); data->bytes_xfered = 0; if (!data->error) { if (host->flags & HOST_F_DMA) { #ifdef CONFIG_SOC_AU1200 u32 chan = DMA_CHANNEL(host); chan_tab_t *c = *((chan_tab_t **)chan); au1x_dma_chan_t *cp = c->chan_ptr; data->bytes_xfered = cp->ddma_bytecnt; #endif } else data->bytes_xfered = (data->blocks * data->blksz) - host->pio.len; } au1xmmc_finish_request(host); }