static noinline __noreturn void tqmls1046a_r_entry(unsigned long memsize) { unsigned long membase = LS1046A_DDR_SDRAM_BASE; if (get_pc() >= membase) { if (memsize + membase >= 0x100000000) memsize = 0x100000000 - membase; barebox_arm_entry(membase, 0x80000000, __dtb_fsl_tqmls1046a_mbls10xxa_start); } arm_cpu_lowlevel_init(); debug_ll_init(); ls1046a_init_lowlevel(); memsize = fsl_ddr_sdram(&ls1046a_info); ls1046a_errata_post_ddr(); ls1046a_esdhc_start_image(memsize, 0, 0); pr_err("Booting failed\n"); while (1); }
/** * @brief The basic entry point for board initialization. * * This is called as part of machine init (after arch init). * This is again called with stack in SRAM, so not too many * constructs possible here. * * @return void */ static noinline void pcm051_board_init(void) { unsigned long sdram = 0x80000000, fdt; /* WDT1 is already running when the bootloader gets control * Disable it to avoid "random" resets */ writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_303); am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd, &MT41J256M8HX15E_2x256M8_regs, &MT41J256M8HX15E_2x256M8_data); am33xx_uart0_soft_reset(); am33xx_enable_uart0_pin_mux(); omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE); putc_ll('>'); /* * Copy the devicetree blob to sdram so that the barebox code finds it * inside valid SDRAM instead of SRAM. */ memcpy((void *)sdram, __dtb_am335x_phytec_phycore_start, __dtb_am335x_phytec_phycore_end - __dtb_am335x_phytec_phycore_start); fdt = sdram; barebox_arm_entry(sdram, SZ_512M, fdt); }
/** * @brief The basic entry point for board initialization. * * This is called as part of machine init (after arch init). * This is again called with stack in SRAM, so not too many * constructs possible here. * * @return void */ static noinline int gf_sram_init(void) { void *fdt; fdt = __dtb_z_am335x_afi_gf_start; /* WDT1 is already running when the bootloader gets control * Disable it to avoid "random" resets */ __raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); __raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); /* Setup the PLLs and the clocks for the peripherals */ am33xx_pll_init(MPUPLL_M_500, DDRPLL_M_200); board_config_ddr(); /* * FIXME configure CAN pinmux early to avoid driving the bus * with the low by default pins. */ configure_module_pin_mux(board_can_pin_mux); am33xx_uart_soft_reset((void *)AM33XX_UART2_BASE); am33xx_enable_uart2_pin_mux(); omap_uart_lowlevel_init((void *)AM33XX_UART2_BASE); putc_ll('>'); barebox_arm_entry(0x80000000, SZ_256M, fdt); }
void __naked __bare_init reset(void) { u32 tmp; common_reset(); /* Setup base clock */ writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3); asm("nop"); /* Setup PLL */ writel(PLL_VALUE, PLLW); asm("nop"); /* CLKEN select, SDRAM width=32 */ writel(SYSCON2_CLKENSL, SYSCON2); /* Enable SDQM pins */ tmp = readl(SYSCON3); tmp &= ~SYSCON3_ENPD67; writel(tmp, SYSCON3); /* Setup Refresh Rate (64ms 8K Blocks) */ writel(SDRAM_REFRESH_RATE, SDRFPR); /* Setup SDRAM (32MB, 16Bit*2, CAS=3) */ writel(SDCONF_CASLAT_3 | SDCONF_SIZE_256 | SDCONF_WIDTH_16 | SDCONF_CLKCTL | SDCONF_ACTIVE, SDCONF); barebox_arm_entry(SDRAM0_BASE, SZ_32M, 0); }
/** * @brief The basic entry point for board initialization. * * This is called as part of machine init (after arch init). * This is again called with stack in SRAM, so not too many * constructs possible here. * * @return void */ static noinline void pcm051_board_init(void) { void *fdt; /* WDT1 is already running when the bootloader gets control * Disable it to avoid "random" resets */ writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_303); am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd, &MT41J256M8HX15E_2x256M8_regs, &MT41J256M8HX15E_2x256M8_data); am33xx_uart0_soft_reset(); am33xx_enable_uart0_pin_mux(); omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE); putc_ll('>'); fdt = __dtb_am335x_phytec_phycore_start - get_runtime_offset(); barebox_arm_entry(0x80000000, SZ_512M, fdt); }
static noinline void socrates_entry(void) { int ret; arm_early_mmu_cache_invalidate(); relocate_to_current_adr(); setup_c(); socfpga_lowlevel_init(&cm_default_cfg, sys_mgr_init_table, ARRAY_SIZE(sys_mgr_init_table)); puts_ll("lowlevel init done\n"); puts_ll("SDRAM setup...\n"); socfpga_sdram_mmr_init(); puts_ll("SDRAM calibration...\n"); ret = socfpga_sdram_calibration(inst_rom_init, inst_rom_init_size, ac_rom_init, ac_rom_init_size); if (ret) hang(); puts_ll("done\n"); barebox_arm_entry(0x0, SZ_1G, 0); }
static noinline void warp7_start(void) { void __iomem *iomuxbase = IOMEM(MX7_IOMUXC_BASE_ADDR); void __iomem *uart = IOMEM(MX7_UART1_BASE_ADDR); void __iomem *ccmbase = IOMEM(MX7_CCM_BASE_ADDR); void *fdt; /* CCM_CCGR148_CLR, uart1 */ writel(0x3, ccmbase + 0x4000 + 16 * 148 + 0x8); /* CCM_TARGET_ROOT95 = UART1_CLK_ROOT */ writel(0x10000000, ccmbase + 0x8000 + 128 * 95); /* CCM_CCGR148_SET, uart1 */ writel(0x3, ccmbase + 0x4000 + 16 * 148 + 0x4); /* MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX without daisy chaining */ writel(0x0, iomuxbase + 0x128); /* MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX */ writel(0x0, iomuxbase + 0x12c); imx7_uart_setup(uart); pbl_set_putc(imx_uart_putc, uart); pr_debug("Element14 i.MX7 Warp\n"); fdt = __dtb_imx7s_warp_start + get_runtime_offset(); barebox_arm_entry(0x80000000, SZ_512M, fdt); }
void __naked barebox_arm_reset_vector(void) { arm_cpu_lowlevel_init(); beaglebone_board_init(); barebox_arm_entry(0x80000000, SZ_256M, 0); }
void __naked __bare_init barebox_arm_reset_vector(void) { arm_cpu_lowlevel_init(); arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16); barebox_arm_entry(SAMA5_DDRCS, at91sama5_get_ddram_size(), 0); }
ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1, r2) { void *fdt; fdt = __dtb_am335x_phytec_phycore_start - get_runtime_offset(); barebox_arm_entry(0x80000000, SZ_512M, fdt); }
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); arm_setup_stack(AT91SAM9N12_SRAM_BASE + AT91SAM9N12_SRAM_SIZE - 16); barebox_arm_entry(AT91_CHIPSELECT_1, at91sam9n12_get_ddram_size(), NULL); }
ENTRY_FUNCTION(start_imx6dl_hummingboard, r0, r1, r2) { uint32_t fdt; arm_cpu_lowlevel_init(); fdt = (uint32_t)__dtb_imx6dl_hummingboard_start - get_runtime_offset(); barebox_arm_entry(0x10000000, SZ_512M, fdt); }
ENTRY_FUNCTION(start_imx6_gk802, r0, r1, r2) { uint32_t fdt; arm_cpu_lowlevel_init(); fdt = (uint32_t)__dtb_imx6q_gk802_start - get_runtime_offset(); barebox_arm_entry(0x10000000, SZ_1G, fdt); }
void __naked __bare_init barebox_arm_reset_vector(void) { arm_cpu_lowlevel_init(); arm_setup_stack(AT91SAM9G45_SRAM_BASE + AT91SAM9G45_SRAM_SIZE - 16); barebox_arm_entry(AT91_CHIPSELECT_6, at91sam9g45_get_ddram_size(1), NULL); }
void __naked __bare_init barebox_arm_reset_vector(uint32_t *data) { omap3_save_bootinfo(data); arm_cpu_lowlevel_init(); omap3_evm_board_init(); barebox_arm_entry(0x80000000, SZ_128M, 0); }
ENTRY_FUNCTION(start_imx6q_sabrelite, r0, r1, r2) { void *fdt; imx6_cpu_lowlevel_init(); fdt = __dtb_imx6q_sabrelite_start - get_runtime_offset(); barebox_arm_entry(0x10000000, SZ_1G, fdt); }
ENTRY_FUNCTION(start_barebox_duckbill, r0, r1, r2) { void *fdt; pr_debug("here we are!\n"); fdt = __dtb_imx28_duckbill_start - get_runtime_offset(); barebox_arm_entry(IMX_MEMORY_BASE, SZ_128M, fdt); }
void __naked __bare_init barebox_arm_reset_vector(void) { arm_cpu_lowlevel_init(); arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16); barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)), NULL); }
ENTRY_FUNCTION(start_am33xx_afi_gf_sdram, r0, r1, r2) { void *fdt; fdt = __dtb_z_am335x_afi_gf_start - get_runtime_offset(); putc_ll('>'); barebox_arm_entry(0x80000000, SZ_256M, fdt); }
ENTRY_FUNCTION(start_imx6dl_nitrogen6x_2g, r0, r1, r2) { void *fdt; imx6_cpu_lowlevel_init(); fdt = __dtb_imx6dl_nitrogen6x_start - get_runtime_offset(); barebox_arm_entry(0x10000000, SZ_2G, fdt); }
ENTRY_FUNCTION(start_socfpga_socrates, r0, r1, r2) { uint32_t fdt; arm_cpu_lowlevel_init(); fdt = (uint32_t)__dtb_socfpga_cyclone5_socrates_start - get_runtime_offset(); barebox_arm_entry(0x0, SZ_1G, fdt); }
void barebox_arm_reset_vector(void) { arm_cpu_lowlevel_init(); if (get_pc() > 0x80000000) goto out; arm_setup_stack(0x4030d000); pcm049_init_lowlevel(); out: barebox_arm_entry(0x80000000, SZ_512M, 0); }
ENTRY_FUNCTION(start_imx6sx_sabresdb, r0, r1, r2) { void *fdt; imx6_cpu_lowlevel_init(); if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); fdt = __dtb_imx6sx_sdb_start + get_runtime_offset(); barebox_arm_entry(0x80000000, SZ_1G, fdt); }
ENTRY_FUNCTION(start_ccxmx51, r0, r1, r2) { extern char __dtb_imx51_ccxmx51_start[]; void *fdt; imx5_cpu_lowlevel_init(); arm_setup_stack(0x20000000 - 16); fdt = __dtb_imx51_ccxmx51_start + get_runtime_offset(); barebox_arm_entry(MX51_CSD0_BASE_ADDR, SZ_128M, fdt); }
void __bare_init at91sam9261_lowlevel_init(void) { struct at91sam926x_lowlevel_cfg cfg; cfg.pio = IOMEM(AT91SAM9261_BASE_PIOC); cfg.sdramc = IOMEM(AT91SAM9261_BASE_SDRAMC); cfg.ebi_pio_is_peripha = false; cfg.matrix_csa = AT91_MATRIX_EBICSA; at91sam926x_lowlevel_init(&cfg); barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc), NULL); }
ENTRY_FUNCTION(start_phytec_pbab01_4gib, r0, r1, r2) { uint32_t fdt; __barebox_arm_head(); arm_cpu_lowlevel_init(); arm_setup_stack(0x00920000 - 8); fdt = (uint32_t)__dtb_imx6q_phytec_pbab01_start - get_runtime_offset(); barebox_arm_entry(0x10000000, 0xEFFFFFF8, fdt); }
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) { omap4_save_bootinfo(data); arm_cpu_lowlevel_init(); if (get_pc() > 0x80000000) goto out; arm_setup_stack(0x4030d000); pcaaxl2_init_lowlevel(); out: barebox_arm_entry(0x80000000, SZ_512M, 0); }
ENTRY_FUNCTION(start_phytec_pbab01_2gib, r0, r1, r2) { uint32_t fdt; arm_cpu_lowlevel_init(); arm_setup_stack(0x00920000 - 8); if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); fdt = (uint32_t)__dtb_imx6q_phytec_pbab01_start - get_runtime_offset(); barebox_arm_entry(0x10000000, SZ_2G, fdt); }
static void __noreturn start_imx6q_phytec_pbaa03_common(uint32_t size) { void *fdt; arm_cpu_lowlevel_init(); arm_setup_stack(0x00920000 - 8); if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); fdt = __dtb_imx6q_phytec_pbaa03_start - get_runtime_offset(); barebox_arm_entry(0x10000000, size, fdt); }
ENTRY_FUNCTION(start_variscite_custom, r0, r1, r2) { void *fdt; imx6_cpu_lowlevel_init(); arm_setup_stack(0x00920000 - 8); if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); fdt = __dtb_imx6q_var_custom_start + get_runtime_offset(); barebox_arm_entry(0x10000000, SZ_1G, fdt); }