int board_eth_init(bd_t *bis) { int error; #ifdef CONFIG_FSL_MC_ENET struct memac_mdio_info *memac_mdio0_info; struct memac_mdio_info *memac_mdio1_info; unsigned int i; initialize_dpmac_to_slot(); memac_mdio0_info = (struct memac_mdio_info *)malloc( sizeof(struct memac_mdio_info)); memac_mdio0_info->regs = (struct memac_mdio_controller *) CONFIG_SYS_FSL_WRIOP1_MDIO1; memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME; /* Register the real MDIO1 bus */ fm_memac_mdio_init(bis, memac_mdio0_info); memac_mdio1_info = (struct memac_mdio_info *)malloc( sizeof(struct memac_mdio_info)); memac_mdio1_info->regs = (struct memac_mdio_controller *) CONFIG_SYS_FSL_WRIOP1_MDIO2; memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME; /* Register the real MDIO2 bus */ fm_memac_mdio_init(bis, memac_mdio1_info); /* Register the muxing front-ends to the MDIO buses */ ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1); ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2); ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3); ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4); ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5); ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6); ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2); for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { switch (wriop_get_enet_if(i)) { case PHY_INTERFACE_MODE_QSGMII: break; case PHY_INTERFACE_MODE_SGMII: ls2085a_handle_phy_interface_sgmii(i); break; case PHY_INTERFACE_MODE_XGMII: ls2085a_handle_phy_interface_xsgmii(i); break; default: break; } } error = cpu_eth_init(bis); #endif error = pci_eth_init(bis); return error; }
int board_eth_init(bd_t *bis) { if (ethernet_present()) return cpu_eth_init(bis); return -1; }
int board_eth_init(bd_t *bis) { setup_iomux_enet(); setup_pcie(); return cpu_eth_init(bis); }
int board_eth_init(bd_t *bis) { ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR; struct fsl_pq_mdio_info dtsec_mdio_info; /* * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting * is not correct. */ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1); dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fsl_pq_mdio_init(bis, &dtsec_mdio_info); fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); fm_info_set_mdio(FM1_DTSEC1, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); fm_info_set_mdio(FM1_DTSEC2, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); #ifdef CONFIG_FMAN_ENET cpu_eth_init(bis); #endif return pci_eth_init(bis); }
static void eth_common_init(void) { bootstage_mark(BOOTSTAGE_ID_NET_ETH_START); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) miiphy_init(); #endif #ifdef CONFIG_PHYLIB phy_init(); #endif /* * If board-specific initialization exists, call it. * If not, call a CPU-specific one */ if (board_eth_init != __def_eth_init) { if (board_eth_init(gd->bd) < 0) printf("Board Net Initialization Failed\n"); } else if (cpu_eth_init != __def_eth_init) { if (cpu_eth_init(gd->bd) < 0) printf("CPU Net Initialization Failed\n"); } else { #ifndef CONFIG_DM_ETH printf("Net Initialization Skipped\n"); #endif } }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FEC_MXC struct ventana_board_info *info = &ventana_info; if (test_bit(EECONFIG_ETH0, info->config)) { setup_iomux_enet(GP_PHY_RST); cpu_eth_init(bis); } #endif #ifdef CONFIG_E1000 e1000_initialize(bis); #endif #ifdef CONFIG_CI_UDC /* For otg ethernet*/ usb_eth_initialize(bis); #endif /* default to the first detected enet dev */ if (!env_get("ethprime")) { struct eth_device *dev = eth_get_dev_by_index(0); if (dev) { env_set("ethprime", dev->name); printf("set ethprime to %s\n", env_get("ethprime")); } } return 0; }
int board_eth_init(bd_t *bis) { int ret; struct eth_device *dev; ret = cpu_eth_init(bis); if (ret) { printf("FEC MXS: Unable to init FEC clocks\n"); return ret; } ret = fecmxc_initialize(bis); if (ret) { printf("FEC MXS: Unable to init FEC\n"); return ret; } dev = eth_get_dev_by_name("FEC"); if (!dev) { printf("FEC MXS: Unable to get FEC device entry\n"); return -EINVAL; } ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); if (ret) { printf("FEC MXS: Unable to register FEC MII postcall\n"); return ret; } return ret; }
int board_eth_init(bd_t *bis) { struct eth_device *dev; int ret; ret = cpu_eth_init(bis); if (ret) { printf("FEC MXC: %s:failed\n", __func__); return ret; } dev = eth_get_dev_by_name("FEC"); if (!dev) { printf("FEC MXC: Unable to get FEC device entry\n"); return -EINVAL; } ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); if (ret) { printf("FEC MXC: Unable to register FEC mii postcall\n"); return ret; } return 0; }
int board_eth_init(bd_t *bis) { setup_iomux_enet(); enable_enet_clk(1); return cpu_eth_init(bis); }
int board_eth_init(bd_t *bis) { imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); setup_fec(); return cpu_eth_init(bis); }
int board_eth_init(bd_t *bis) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; struct eth_device *dev; int ret; ret = cpu_eth_init(bis); /* MX28EVK uses ENET_CLK PAD to drive FEC clock */ writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, &clkctrl_regs->hw_clkctrl_enet); /* Power-on FECs */ gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0); /* Reset FEC PHYs */ gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); udelay(200); gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); if (ret) { puts("FEC MXS: Unable to init FEC0\n"); return ret; } ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE); if (ret) { puts("FEC MXS: Unable to init FEC1\n"); return ret; } dev = eth_get_dev_by_name("FEC0"); if (!dev) { puts("FEC MXS: Unable to get FEC0 device entry\n"); return -EINVAL; } ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); if (ret) { puts("FEC MXS: Unable to register FEC0 mii postcall\n"); return ret; } dev = eth_get_dev_by_name("FEC1"); if (!dev) { puts("FEC MXS: Unable to get FEC1 device entry\n"); return -EINVAL; } ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); if (ret) { puts("FEC MXS: Unable to register FEC1 mii postcall\n"); return ret; } return ret; }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct memac_mdio_info memac_mdio_info; unsigned int i; int phy_addr = 0; printf("Initializing Fman\n"); memac_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the real 1G MDIO bus */ fm_memac_mdio_init(bis, &memac_mdio_info); /* * Program on board RGMII, SGMII PHY addresses. */ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { #ifdef CONFIG_T1040RDB case PHY_INTERFACE_MODE_SGMII: /* T1040RDB only supports SGMII on DTSEC3 */ fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_SGMII1_PHY_ADDR); break; #endif case PHY_INTERFACE_MODE_RGMII: if (FM1_DTSEC4 == i) phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; if (FM1_DTSEC5 == i) phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR; fm_info_set_phy_address(i, phy_addr); break; case PHY_INTERFACE_MODE_QSGMII: fm_info_set_phy_address(i, 0); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); break; default: printf("Fman1: DTSEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } fm_info_set_mdio(i, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); } cpu_eth_init(bis); #endif return pci_eth_init(bis); }
static inline int cm_t3517_init_emac(bd_t *bis) { int ret = cpu_eth_init(bis); if (ret > 0) return ret; printf("Failed initializing EMAC! "); return 0; }
int board_eth_init(bd_t *bis) { int error = 0; #ifdef CONFIG_FSL_MC_ENET error = cpu_eth_init(bis); #endif error = pci_eth_init(bis); return error; }
int board_eth_init(bd_t *bis) { int ret; setup_iomux_enet(); ret = cpu_eth_init(bis); if (ret) printf("FEC MXC: %s:failed\n", __func__); return 0; }
int board_eth_init(bd_t *bis) { int error = 0; #ifdef CONFIG_SMC91111 error = smc91111_initialize(0, CONFIG_SMC91111_BASE); #endif #ifdef CONFIG_FSL_MC_ENET error = cpu_eth_init(bis); #endif return error; }
int board_eth_init(bd_t *bis) { int rv, n = 0; rv = cpu_eth_init(bis); if (rv > 0) n += rv; rv = usb_eth_initialize(bis); if (rv > 0) n += rv; return n; }
int board_eth_init(bd_t *bis) { int res = handle_mac_address(); if (res) puts("No MAC address found\n"); SETUP_IOMUX_PADS(enet_pads); /* phy reset */ gpio_direction_output(CM_FX6_ENET_NRST, 0); udelay(500); gpio_set_value(CM_FX6_ENET_NRST, 1); enable_enet_clk(1); return cpu_eth_init(bis); }
int board_eth_init(bd_t *bis) { struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret = enable_fec_anatop_clock(ENET_25MHZ); if (ret) return ret; /* set gpr1[ENET_CLK_SEL] */ setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); setup_iomux_enet(); return cpu_eth_init(bis); }
int board_eth_init(bd_t *bis) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret; /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); ret = enable_fec_anatop_clock(0, ENET_50MHZ); if (ret) return ret; setup_iomux_enet(); return cpu_eth_init(bis); }
int board_eth_init(bd_t *bis) { int ret; imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); /* Reset LAN8742 PHY */ ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset"); if (!ret) gpio_direction_output(ENET_PHY_RESET_GPIO , 0); mdelay(10); gpio_set_value(ENET_PHY_RESET_GPIO, 1); mdelay(10); return cpu_eth_init(bis); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct fsl_pq_mdio_info dtsec_mdio_info; unsigned int i; printf("Initializing Fman\n"); /* Register the real 1G MDIO bus */ dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; fsl_pq_mdio_init(bis, &dtsec_mdio_info); fm_info_set_phy_address(FIRST_PORT, FIRST_PORT_ADDR); fm_info_set_mdio(FIRST_PORT, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); fm_info_set_phy_address(SECOND_PORT, SECOND_PORT_ADDR); fm_info_set_mdio(SECOND_PORT, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); /* Never disable DTSEC1 - it controls MDIO */ for (i = FM1_DTSEC2; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { if (!IS_VALID_PORT(i)) fm_disable_port(i); } #ifdef CONFIG_PPC_P5040 for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { if (!IS_VALID_PORT(i)) fm_disable_port(i); } #endif cpu_eth_init(bis); cyrus_phy_tuning(FIRST_PORT_ADDR); cyrus_phy_tuning(SECOND_PORT_ADDR); #endif return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { int rv, num_if = 0; /* Initialize TSECs first */ rv = cpu_eth_init(bis); if (rv >= 0) num_if += rv; else printf("ERROR: failed to initialize TSECs.\n"); rv = pci_eth_init(bis); if (rv >= 0) num_if += rv; else printf("ERROR: failed to initialize PCI Ethernet.\n"); return num_if; }
int board_eth_init(bd_t *bis) { int err; err = handle_mac_address(); if (err) puts("No MAC address found\n"); SETUP_IOMUX_PADS(enet_pads); /* phy reset */ err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst"); if (err) printf("Etnernet NRST gpio request failed: %d\n", err); gpio_direction_output(CM_FX6_ENET_NRST, 0); udelay(500); gpio_set_value(CM_FX6_ENET_NRST, 1); enable_enet_clk(1); return cpu_eth_init(bis); }
int board_eth_init(bd_t *bis) { int err; if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS)) printf(NO_MAC_ADDR, "primary NIC"); if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS)) printf(NO_MAC_ADDR, "secondary NIC"); SETUP_IOMUX_PADS(enet_pads); /* phy reset */ err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst"); if (err) printf("Etnernet NRST gpio request failed: %d\n", err); gpio_direction_output(CM_FX6_ENET_NRST, 0); udelay(500); gpio_set_value(CM_FX6_ENET_NRST, 1); enable_enet_clk(1); return cpu_eth_init(bis); }
int board_eth_init(bd_t *bis) { u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR; ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR; struct fsl_pq_mdio_info dtsec_mdio_info; /* * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting * is not correct. */ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1); dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fsl_pq_mdio_init(bis, &dtsec_mdio_info); fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); fm_info_set_mdio(FM1_DTSEC1, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); fm_info_set_mdio(FM1_DTSEC2, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); /* Make SERDES connected to SGMII by cleaing bcsr19[7] */ if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII) clrbits_8(&bcsr[19], BCSR19_SGMII_SEL_L); #ifdef CONFIG_FMAN_ENET cpu_eth_init(bis); #endif return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { cpu_eth_init(bis); return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct memac_mdio_info memac_mdio_info; unsigned int i; #ifdef CONFIG_VSC9953 int lane; int phy_addr; phy_interface_t phy_int; struct mii_dev *bus; #endif printf("Initializing Fman\n"); set_brdcfg9_for_gtx_clk(); initialize_lane_to_slot(); /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) mdio_mux[i] = EMI_NONE; memac_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the real 1G MDIO bus */ fm_memac_mdio_init(bis, &memac_mdio_info); /* Register the muxing front-ends to the MDIO buses */ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); /* * Program on board RGMII PHY addresses. If the SGMII Riser * card used, we'll override the PHY address later. For any DTSEC that * is RGMII, we'll also override its PHY address later. We assume that * DTSEC4 and DTSEC5 are used for RGMII. */ fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_QSGMII: fm_info_set_mdio(i, NULL); break; case PHY_INTERFACE_MODE_SGMII: t1040_handle_phy_interface_sgmii(i); break; case PHY_INTERFACE_MODE_RGMII: /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ t1040_handle_phy_interface_rgmii(i); break; default: break; } } #ifdef CONFIG_VSC9953 for (i = 0; i < VSC9953_MAX_PORTS; i++) { lane = -1; phy_addr = 0; phy_int = PHY_INTERFACE_MODE_NONE; switch (i) { case 0: case 1: case 2: case 3: lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A); /* PHYs connected over QSGMII */ if (lane >= 0) { phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i; phy_int = PHY_INTERFACE_MODE_QSGMII; break; } lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_SW1_MAC1 + i); if (lane < 0) break; /* PHYs connected over QSGMII */ if (i != 3 || lane_to_slot[lane] == 7) phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + i; else phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR; phy_int = PHY_INTERFACE_MODE_SGMII; break; case 4: case 5: case 6: case 7: lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B); /* PHYs connected over QSGMII */ if (lane >= 0) { phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i - 4; phy_int = PHY_INTERFACE_MODE_QSGMII; break; } lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_SW1_MAC1 + i); /* PHYs connected over SGMII */ if (lane >= 0) { phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + i - 3; phy_int = PHY_INTERFACE_MODE_SGMII; } break; case 8: if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0) /* FM1@DTSEC1 is connected to SW1@PORT8 */ vsc9953_port_enable(i); break; case 9: if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) { /* Enable L2 On MAC2 using SCFG */ struct ccsr_scfg *scfg = (struct ccsr_scfg *) CONFIG_SYS_MPC85xx_SCFG; out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) | (0x80000000)); vsc9953_port_enable(i); } break; } if (lane >= 0) { bus = mii_dev_for_muxval(lane_to_slot[lane]); vsc9953_port_info_set_mdio(i, bus); vsc9953_port_enable(i); } vsc9953_port_info_set_phy_address(i, phy_addr); vsc9953_port_info_set_phy_int(i, phy_int); } #endif cpu_eth_init(bis); #endif return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { cpu_eth_init(bis); /* Intialize TSECs first */ return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { cpu_eth_init(bis); /* Built in FEC comes first */ return pci_eth_init(bis); }