/* Return various strings for glGetString().
*/
static const GLubyte *r200GetString( GLcontext *ctx, GLenum name )
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
static char buffer[128];
unsigned offset;
GLuint agp_mode = (rmesa->radeon.radeonScreen->card_type == RADEON_CARD_PCI)? 0 :
rmesa->radeon.radeonScreen->AGPMode;
switch ( name ) {
case GL_VENDOR:
return (GLubyte *)"Tungsten Graphics, Inc.";
case GL_RENDERER:
offset = driGetRendererString( buffer, "R200", DRIVER_DATE,
agp_mode );
sprintf( & buffer[ offset ], " %sTCL",
!(rmesa->radeon.TclFallback & R200_TCL_FALLBACK_TCL_DISABLE)
? "" : "NO-" );
return (GLubyte *)buffer;
default:
return NULL;
}
}
static const GLubyte *
intelGetString(struct gl_context * ctx, GLenum name)
{
const struct brw_context *const brw = brw_context(ctx);
const char *chipset;
static char buffer[128];
switch (name) {
case GL_VENDOR:
return (GLubyte *) "Intel Open Source Technology Center";
break;
case GL_RENDERER:
switch (brw->intelScreen->deviceID) {
#undef CHIPSET
#define CHIPSET(id, symbol, str) case id: chipset = str; break;
#include "pci_ids/i965_pci_ids.h"
default:
chipset = "Unknown Intel Chipset";
break;
}
(void) driGetRendererString(buffer, chipset, 0);
return (GLubyte *) buffer;
default:
return NULL;
}
}
/* Return various strings for glGetString().
*/
static const GLubyte *r128DDGetString( GLcontext *ctx, GLenum name )
{
r128ContextPtr rmesa = R128_CONTEXT(ctx);
static char buffer[128];
unsigned offset;
const char * card_name = "Rage 128";
GLuint agp_mode = rmesa->r128Screen->IsPCI ? 0 :
rmesa->r128Screen->AGPMode;
switch ( name ) {
case GL_VENDOR:
return (GLubyte *)"VA Linux Systems, Inc.";
case GL_RENDERER:
/* Select the spefic chipset.
*/
if ( R128_IS_PRO( rmesa ) ) {
card_name = "Rage 128 Pro";
}
else if ( R128_IS_MOBILITY( rmesa ) ) {
card_name = "Rage 128 Mobility";
}
offset = driGetRendererString( buffer, card_name, DRIVER_DATE,
agp_mode );
return (GLubyte *)buffer;
default:
return NULL;
}
}
static const GLubyte *savageDDGetString( struct gl_context *ctx, GLenum name )
{
static char *cardNames[S3_LAST] = {
"Unknown",
"Savage3D",
"Savage/MX/IX",
"Savage4",
"ProSavage",
"Twister",
"ProSavageDDR",
"SuperSavage",
"Savage2000"
};
static char buffer[128];
savageContextPtr imesa = SAVAGE_CONTEXT(ctx);
savageScreenPrivate *screen = imesa->savageScreen;
enum S3CHIPTAGS chipset = screen->chipset;
unsigned offset;
if (chipset < S3_SAVAGE3D || chipset >= S3_LAST)
chipset = S3_UNKNOWN; /* should not happen */
switch (name) {
case GL_VENDOR:
return (GLubyte *)"S3 Graphics Inc.";
case GL_RENDERER:
offset = driGetRendererString( buffer, cardNames[chipset], DRIVER_DATE,
screen->agpMode );
return (GLubyte *)buffer;
default:
return 0;
}
}
/* glGetString */
static const GLubyte *nouveauGetString( GLcontext *ctx, GLenum name )
{
nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
static char buffer[128];
const char * card_name = "Unknown";
GLuint agp_mode = 0;
switch ( name ) {
case GL_VENDOR:
return (GLubyte *)DRIVER_AUTHOR;
case GL_RENDERER:
card_name=nmesa->screen->card->name;
switch(nmesa->screen->bus_type)
{
case NV_PCI:
case NV_PCIE:
default:
agp_mode=0;
break;
case NV_AGP:
agp_mode=nmesa->screen->agp_mode;
break;
}
driGetRendererString( buffer, card_name, DRIVER_DATE,
agp_mode );
return (GLubyte *)buffer;
default:
return NULL;
}
}
const char *
nouveau_get_renderer_string(unsigned chipset)
{
char hardware_name[32];
static char buffer[128];
snprintf(hardware_name, sizeof(hardware_name), "nv%02X", chipset);
driGetRendererString(buffer, hardware_name, 0);
return buffer;
}
/* KW: Put the word Mesa in the render string because quakeworld
* checks for this rather than doing a glGet(GL_MAX_TEXTURE_SIZE).
* Why?
*/
static const GLubyte *tdfxDDGetString( GLcontext *ctx, GLenum name )
{
tdfxContextPtr fxMesa = (tdfxContextPtr) ctx->DriverCtx;
switch (name) {
case GL_RENDERER:
{
/* The renderer string must be per-context state to handle
* multihead correctly.
*/
char *const buffer = fxMesa->rendererString;
char hardware[64];
LOCK_HARDWARE(fxMesa);
strncpy(hardware, fxMesa->Glide.grGetString(GR_HARDWARE),
sizeof(hardware));
hardware[sizeof(hardware) - 1] = '\0';
UNLOCK_HARDWARE(fxMesa);
if ((strncmp(hardware, "Voodoo3", 7) == 0)
|| (strncmp(hardware, "Voodoo4", 7) == 0)
|| (strncmp(hardware, "Voodoo5", 7) == 0)) {
hardware[7] = '\0';
}
else if (strncmp(hardware, "Voodoo Banshee", 14) == 0) {
strcpy(&hardware[6], "Banshee");
}
else {
/* unexpected result: replace spaces with hyphens */
int i;
for (i = 0; hardware[i] && (i < sizeof(hardware)); i++) {
if (hardware[i] == ' ' || hardware[i] == '\t') {
hardware[i] = '-';
}
}
}
(void) driGetRendererString(buffer, hardware, DRIVER_DATE, 0);
return (const GLubyte *) buffer;
}
case GL_VENDOR:
return (const GLubyte *)"VA Linux Systems, Inc.";
default:
return NULL;
}
}
const char *
brw_get_renderer_string(unsigned deviceID)
{
const char *chipset;
static char buffer[128];
switch (deviceID) {
#undef CHIPSET
#define CHIPSET(id, symbol, str) case id: chipset = str; break;
#include "pci_ids/i965_pci_ids.h"
default:
chipset = "Unknown Intel Chipset";
break;
}
(void) driGetRendererString(buffer, chipset, 0);
return buffer;
}
static const GLubyte *
nouveau_get_string(GLcontext *ctx, GLenum name)
{
static char buffer[128];
char hardware_name[32];
switch (name) {
case GL_VENDOR:
return (GLubyte *)"Nouveau";
case GL_RENDERER:
sprintf(hardware_name, "nv%02X", context_chipset(ctx));
driGetRendererString(buffer, hardware_name, DRIVER_DATE, 0);
return (GLubyte *)buffer;
default:
return NULL;
}
}
/* Return various strings for glGetString().
*/
static const GLubyte *
sisGetString( GLcontext *ctx, GLenum name )
{
sisContextPtr smesa = SIS_CONTEXT(ctx);
static char buffer[128];
unsigned offset;
GLuint agp_mode = (smesa->AGPSize > 0);
switch ( name )
{
case GL_VENDOR:
return (GLubyte *)"Eric Anholt";
case GL_RENDERER:
offset = driGetRendererString( buffer, "SiS", DRIVER_DATE, agp_mode );
return (GLubyte *)buffer;
default:
return NULL;
}
}
/* Return various strings for glGetString().
*/
static const GLubyte *mach64DDGetString( GLcontext *ctx, GLenum name )
{
mach64ContextPtr mmesa = MACH64_CONTEXT(ctx);
static char buffer[128];
unsigned offset;
const char * card_name = "Mach64 [Rage Pro]";
GLuint agp_mode = mmesa->mach64Screen->IsPCI ? 0 :
mmesa->mach64Screen->AGPMode;
switch ( name ) {
case GL_VENDOR:
return (GLubyte*)"Gareth Hughes, Leif Delgass, José Fonseca";
case GL_RENDERER:
offset = driGetRendererString( buffer, card_name, DRIVER_DATE,
agp_mode );
return (GLubyte *)buffer;
default:
return NULL;
}
}
static const GLubyte *mgaGetString( GLcontext *ctx, GLenum name )
{
mgaContextPtr mmesa = MGA_CONTEXT( ctx );
static char buffer[128];
unsigned offset;
switch ( name ) {
case GL_VENDOR:
return (GLubyte *) "VA Linux Systems Inc.";
case GL_RENDERER:
offset = driGetRendererString( buffer,
MGA_IS_G400(mmesa) ? "G400" :
MGA_IS_G200(mmesa) ? "G200" : "MGA",
DRIVER_DATE,
mmesa->mgaScreen->agpMode );
return (GLubyte *)buffer;
default:
return NULL;
}
}
static const GLubyte *
intelGetString(GLcontext * ctx, GLenum name)
{
const struct intel_context *const intel = intel_context(ctx);
const char *chipset;
static char buffer[128];
switch (name) {
case GL_VENDOR:
return (GLubyte *) "Tungsten Graphics, Inc";
break;
case GL_RENDERER:
switch (intel->intelScreen->deviceID) {
case PCI_CHIP_845_G:
chipset = "Intel(R) 845G";
break;
case PCI_CHIP_I830_M:
chipset = "Intel(R) 830M";
break;
case PCI_CHIP_I855_GM:
chipset = "Intel(R) 852GM/855GM";
break;
case PCI_CHIP_I865_G:
chipset = "Intel(R) 865G";
break;
case PCI_CHIP_I915_G:
chipset = "Intel(R) 915G";
break;
case PCI_CHIP_E7221_G:
chipset = "Intel (R) E7221G (i915)";
break;
case PCI_CHIP_I915_GM:
chipset = "Intel(R) 915GM";
break;
case PCI_CHIP_I945_G:
chipset = "Intel(R) 945G";
break;
case PCI_CHIP_I945_GM:
chipset = "Intel(R) 945GM";
break;
case PCI_CHIP_I945_GME:
chipset = "Intel(R) 945GME";
break;
case PCI_CHIP_G33_G:
chipset = "Intel(R) G33";
break;
case PCI_CHIP_Q35_G:
chipset = "Intel(R) Q35";
break;
case PCI_CHIP_Q33_G:
chipset = "Intel(R) Q33";
break;
case PCI_CHIP_IGD_GM:
case PCI_CHIP_IGD_G:
chipset = "Intel(R) IGD";
break;
case PCI_CHIP_I965_Q:
chipset = "Intel(R) 965Q";
break;
case PCI_CHIP_I965_G:
case PCI_CHIP_I965_G_1:
chipset = "Intel(R) 965G";
break;
case PCI_CHIP_I946_GZ:
chipset = "Intel(R) 946GZ";
break;
case PCI_CHIP_I965_GM:
chipset = "Intel(R) 965GM";
break;
case PCI_CHIP_I965_GME:
chipset = "Intel(R) 965GME/GLE";
break;
case PCI_CHIP_GM45_GM:
chipset = "Mobile Intel® GM45 Express Chipset";
break;
case PCI_CHIP_IGD_E_G:
chipset = "Intel(R) Integrated Graphics Device";
break;
case PCI_CHIP_G45_G:
chipset = "Intel(R) G45/G43";
break;
case PCI_CHIP_Q45_G:
chipset = "Intel(R) Q45/Q43";
break;
case PCI_CHIP_G41_G:
chipset = "Intel(R) G41";
break;
case PCI_CHIP_B43_G:
chipset = "Intel(R) B43";
break;
case PCI_CHIP_ILD_G:
chipset = "Intel(R) Ironlake Desktop";
break;
case PCI_CHIP_ILM_G:
chipset = "Intel(R) Ironlake Mobile";
break;
default:
chipset = "Unknown Intel Chipset";
break;
}
(void) driGetRendererString(buffer, chipset, DRIVER_DATE_GEM, 0);
return (GLubyte *) buffer;
default:
return NULL;
}
}
static const GLubyte *
intelGetString(struct gl_context * ctx, GLenum name)
{
const struct intel_context *const intel = intel_context(ctx);
const char *chipset;
static char buffer[128];
switch (name) {
case GL_VENDOR:
return (GLubyte *) "Intel Open Source Technology Center";
break;
case GL_RENDERER:
switch (intel->intelScreen->deviceID) {
case PCI_CHIP_845_G:
chipset = "Intel(R) 845G";
break;
case PCI_CHIP_I830_M:
chipset = "Intel(R) 830M";
break;
case PCI_CHIP_I855_GM:
chipset = "Intel(R) 852GM/855GM";
break;
case PCI_CHIP_I865_G:
chipset = "Intel(R) 865G";
break;
case PCI_CHIP_I915_G:
chipset = "Intel(R) 915G";
break;
case PCI_CHIP_E7221_G:
chipset = "Intel (R) E7221G (i915)";
break;
case PCI_CHIP_I915_GM:
chipset = "Intel(R) 915GM";
break;
case PCI_CHIP_I945_G:
chipset = "Intel(R) 945G";
break;
case PCI_CHIP_I945_GM:
chipset = "Intel(R) 945GM";
break;
case PCI_CHIP_I945_GME:
chipset = "Intel(R) 945GME";
break;
case PCI_CHIP_G33_G:
chipset = "Intel(R) G33";
break;
case PCI_CHIP_Q35_G:
chipset = "Intel(R) Q35";
break;
case PCI_CHIP_Q33_G:
chipset = "Intel(R) Q33";
break;
case PCI_CHIP_IGD_GM:
case PCI_CHIP_IGD_G:
chipset = "Intel(R) IGD";
break;
case PCI_CHIP_I965_Q:
chipset = "Intel(R) 965Q";
break;
case PCI_CHIP_I965_G:
case PCI_CHIP_I965_G_1:
chipset = "Intel(R) 965G";
break;
case PCI_CHIP_I946_GZ:
chipset = "Intel(R) 946GZ";
break;
case PCI_CHIP_I965_GM:
chipset = "Intel(R) 965GM";
break;
case PCI_CHIP_I965_GME:
chipset = "Intel(R) 965GME/GLE";
break;
case PCI_CHIP_GM45_GM:
chipset = "Mobile Intel® GM45 Express Chipset";
break;
case PCI_CHIP_IGD_E_G:
chipset = "Intel(R) Integrated Graphics Device";
break;
case PCI_CHIP_G45_G:
chipset = "Intel(R) G45/G43";
break;
case PCI_CHIP_Q45_G:
chipset = "Intel(R) Q45/Q43";
break;
case PCI_CHIP_G41_G:
chipset = "Intel(R) G41";
break;
case PCI_CHIP_B43_G:
case PCI_CHIP_B43_G1:
chipset = "Intel(R) B43";
break;
case PCI_CHIP_ILD_G:
chipset = "Intel(R) Ironlake Desktop";
break;
case PCI_CHIP_ILM_G:
chipset = "Intel(R) Ironlake Mobile";
break;
case PCI_CHIP_SANDYBRIDGE_GT1:
case PCI_CHIP_SANDYBRIDGE_GT2:
case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
chipset = "Intel(R) Sandybridge Desktop";
break;
case PCI_CHIP_SANDYBRIDGE_M_GT1:
case PCI_CHIP_SANDYBRIDGE_M_GT2:
case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
chipset = "Intel(R) Sandybridge Mobile";
break;
case PCI_CHIP_SANDYBRIDGE_S:
chipset = "Intel(R) Sandybridge Server";
break;
case PCI_CHIP_IVYBRIDGE_GT1:
case PCI_CHIP_IVYBRIDGE_GT2:
chipset = "Intel(R) Ivybridge Desktop";
break;
case PCI_CHIP_IVYBRIDGE_M_GT1:
case PCI_CHIP_IVYBRIDGE_M_GT2:
chipset = "Intel(R) Ivybridge Mobile";
break;
case PCI_CHIP_IVYBRIDGE_S_GT1:
case PCI_CHIP_IVYBRIDGE_S_GT2:
chipset = "Intel(R) Ivybridge Server";
break;
case PCI_CHIP_HASWELL_GT1:
case PCI_CHIP_HASWELL_GT2:
case PCI_CHIP_HASWELL_GT2_PLUS:
case PCI_CHIP_HASWELL_SDV_GT1:
case PCI_CHIP_HASWELL_SDV_GT2:
case PCI_CHIP_HASWELL_SDV_GT2_PLUS:
case PCI_CHIP_HASWELL_ULT_GT1:
case PCI_CHIP_HASWELL_ULT_GT2:
case PCI_CHIP_HASWELL_ULT_GT2_PLUS:
case PCI_CHIP_HASWELL_CRW_GT1:
case PCI_CHIP_HASWELL_CRW_GT2:
case PCI_CHIP_HASWELL_CRW_GT2_PLUS:
chipset = "Intel(R) Haswell Desktop";
break;
case PCI_CHIP_HASWELL_M_GT1:
case PCI_CHIP_HASWELL_M_GT2:
case PCI_CHIP_HASWELL_M_GT2_PLUS:
case PCI_CHIP_HASWELL_SDV_M_GT1:
case PCI_CHIP_HASWELL_SDV_M_GT2:
case PCI_CHIP_HASWELL_SDV_M_GT2_PLUS:
case PCI_CHIP_HASWELL_ULT_M_GT1:
case PCI_CHIP_HASWELL_ULT_M_GT2:
case PCI_CHIP_HASWELL_ULT_M_GT2_PLUS:
case PCI_CHIP_HASWELL_CRW_M_GT1:
case PCI_CHIP_HASWELL_CRW_M_GT2:
case PCI_CHIP_HASWELL_CRW_M_GT2_PLUS:
chipset = "Intel(R) Haswell Mobile";
break;
case PCI_CHIP_HASWELL_S_GT1:
case PCI_CHIP_HASWELL_S_GT2:
case PCI_CHIP_HASWELL_S_GT2_PLUS:
case PCI_CHIP_HASWELL_SDV_S_GT1:
case PCI_CHIP_HASWELL_SDV_S_GT2:
case PCI_CHIP_HASWELL_SDV_S_GT2_PLUS:
case PCI_CHIP_HASWELL_ULT_S_GT1:
case PCI_CHIP_HASWELL_ULT_S_GT2:
case PCI_CHIP_HASWELL_ULT_S_GT2_PLUS:
case PCI_CHIP_HASWELL_CRW_S_GT1:
case PCI_CHIP_HASWELL_CRW_S_GT2:
case PCI_CHIP_HASWELL_CRW_S_GT2_PLUS:
chipset = "Intel(R) Haswell Server";
break;
default:
chipset = "Unknown Intel Chipset";
break;
}
(void) driGetRendererString(buffer, chipset, 0);
return (GLubyte *) buffer;
default:
return NULL;
}
}
