static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
{
struct rockchip_spi_platdata *plat = bus->platdata;
struct rockchip_spi_priv *priv = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
int ret;
plat->base = dev_get_addr(bus);
ret = clk_get_by_index(bus, 0, &priv->clk);
if (ret < 0) {
debug("%s: Could not get clock for %s: %d\n", __func__,
bus->name, ret);
return ret;
}
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
50000000);
plat->deactivate_delay_us = fdtdec_get_int(blob, node,
"spi-deactivate-delay", 0);
plat->activate_delay_us = fdtdec_get_int(blob, node,
"spi-activate-delay", 0);
debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
__func__, (uint)plat->base, plat->frequency,
plat->deactivate_delay_us);
return 0;
}
static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
{
struct arasan_sdhci_priv *priv = dev_get_priv(dev);
priv->host = calloc(1, sizeof(struct sdhci_host));
if (priv->host == NULL)
return -1;
priv->host->name = dev->name;
priv->host->ioaddr = (void *)dev_get_addr(dev);
priv->deviceid = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"xlnx,device_id", -1);
priv->bank = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"xlnx,mio_bank", -1);
if (fdt_get_property(gd->fdt_blob, dev->of_offset, "no-1-8-v", NULL))
priv->no_1p8 = 1;
else
priv->no_1p8 = 0;
if (fdt_get_property(gd->fdt_blob, dev->of_offset, "mmc-pwrseq", NULL))
priv->pwrseq = true;
return 0;
}
static int atmel_hlcdc_ofdata_to_platdata(struct udevice *dev)
{
struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
priv->regs = (struct atmel_hlcd_regs *)devfdt_get_addr(dev);
if (!priv->regs) {
debug("%s: No display controller address\n", __func__);
return -EINVAL;
}
if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
0, &priv->timing)) {
debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL;
}
if (priv->timing.hactive.typ > LCD_MAX_WIDTH)
priv->timing.hactive.typ = LCD_MAX_WIDTH;
if (priv->timing.vactive.typ > LCD_MAX_HEIGHT)
priv->timing.vactive.typ = LCD_MAX_HEIGHT;
priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0);
if (!priv->vl_bpix) {
debug("%s: Failed to get bits per pixel\n", __func__);
return -EINVAL;
}
priv->output_mode = fdtdec_get_int(blob, node, "atmel,output-mode", 24);
priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1);
return 0;
}
static int zynqmp_qspi_ofdata_to_platdata(struct udevice *bus)
{
struct zynqmp_qspi_platdata *plat = bus->platdata;
int is_dual;
debug("%s\n", __func__);
plat->regs = (struct zynqmp_qspi_regs *)(devfdt_get_addr(bus) +
GQSPI_REG_OFFSET);
plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
(devfdt_get_addr(bus) + GQSPI_DMA_REG_OFFSET);
is_dual = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), "is-dual", -1);
if (is_dual < 0)
plat->is_dual = SF_SINGLE_FLASH;
else if (is_dual == 1)
plat->is_dual = SF_DUAL_PARALLEL_FLASH;
else
if (fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
"is-stacked", -1) < 0)
plat->is_dual = SF_SINGLE_FLASH;
else
plat->is_dual = SF_DUAL_STACKED_FLASH;
plat->io_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(bus),
"has-io-mode");
return 0;
}
static int tegra30_spi_ofdata_to_platdata(struct udevice *bus)
{
struct tegra_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
plat->base = fdtdec_get_addr(blob, node, "reg");
plat->periph_id = clock_decode_periph_id(blob, node);
if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id %d\n", __func__,
plat->periph_id);
return -FDT_ERR_NOTFOUND;
}
/* Use 500KHz as a suitable default */
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
500000);
plat->deactivate_delay_us = fdtdec_get_int(blob, node,
"spi-deactivate-delay", 0);
debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
__func__, plat->base, plat->periph_id, plat->frequency,
plat->deactivate_delay_us);
return 0;
}
static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
host->name = dev->name;
host->ioaddr = (void *)dev_get_addr(dev);
host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"bus-width", 4);
host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
host->priv = dev;
/* use non-removeable as sdcard and emmc as judgement */
if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "non-removable"))
host->dev_index = 0;
else
host->dev_index = 1;
priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"fifo-depth", 0);
if (priv->fifo_depth < 0)
return -EINVAL;
priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
"fifo-mode");
if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
"clock-freq-min-max", priv->minmax, 2))
return -EINVAL;
#endif
return 0;
}
static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
{
struct ti_qspi_priv *priv = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
fdt_addr_t mmap_addr;
fdt_addr_t mmap_size;
priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
priv->base = map_physmem(devfdt_get_addr(bus),
sizeof(struct ti_qspi_regs), MAP_NOCACHE);
mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
priv->mmap_size = mmap_size;
priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
if (priv->max_hz < 0) {
debug("Error: Max frequency missing\n");
return -ENODEV;
}
priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
(int)priv->base, priv->max_hz);
return 0;
}
static int emaclite_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct xemaclite *emaclite = dev_get_priv(dev);
int offset = 0;
pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
0x10000);
emaclite->phyaddr = -1;
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"phy-handle");
if (offset > 0)
emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
"reg", -1);
emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"xlnx,tx-ping-pong", 0);
emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"xlnx,rx-ping-pong", 0);
printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
return 0;
}
static int mvneta_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct mvneta_port *pp = dev_get_priv(dev);
void *blob = (void *)gd->fdt_blob;
int node = dev->of_offset;
struct mii_dev *bus;
unsigned long addr;
void *bd_space;
/*
* Allocate buffer area for descs and rx_buffers. This is only
* done once for all interfaces. As only one interface can
* be active. Make this area DMA save by disabling the D-cache
*/
if (!buffer_loc.tx_descs) {
/* Align buffer area for descs and rx_buffers to 1MiB */
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
DCACHE_OFF);
buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
buffer_loc.rx_descs = (struct mvneta_rx_desc *)
((phys_addr_t)bd_space +
MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc));
buffer_loc.rx_buffers = (phys_addr_t)
(bd_space +
MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) +
MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc));
}
pp->base = (void __iomem *)pdata->iobase;
/* Configure MBUS address windows */
if (of_device_is_compatible(dev, "marvell,armada-3700-neta"))
mvneta_bypass_mbus_windows(pp);
else
mvneta_conf_mbus_windows(pp);
/* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
pp->phy_interface = pdata->phy_interface;
/* Now read phyaddr from DT */
addr = fdtdec_get_int(blob, node, "phy", 0);
addr = fdt_node_offset_by_phandle(blob, addr);
pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate MDIO bus\n");
return -ENOMEM;
}
bus->read = mvneta_mdio_read;
bus->write = mvneta_mdio_write;
snprintf(bus->name, sizeof(bus->name), dev->name);
bus->priv = (void *)pp;
pp->bus = bus;
return mdio_register(bus);
}
static int ftsdc010_mmc_ofdata_to_platdata(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct ftsdc_priv *priv = dev_get_priv(dev);
struct ftsdc010_chip *chip = &priv->chip;
chip->name = dev->name;
chip->ioaddr = (void *)devfdt_get_addr(dev);
chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"bus-width", 4);
chip->priv = dev;
priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"fifo-depth", 0);
priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"fifo-mode");
if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
"clock-freq-min-max", priv->minmax, 2)) {
int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"max-frequency", -EINVAL);
if (val < 0)
return val;
priv->minmax[0] = 400000; /* 400 kHz */
priv->minmax[1] = val;
} else {
debug("%s: 'clock-freq-min-max' property was deprecated.\n",
__func__);
}
#endif
chip->sclk = priv->minmax[1];
chip->regs = chip->ioaddr;
return 0;
}
static int i2c_arbitrator_probe(struct udevice *dev)
{
struct i2c_arbitrator_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
int node = dev->of_offset;
int ret;
debug("%s: %s\n", __func__, dev->name);
priv->slew_delay_us = fdtdec_get_int(blob, node, "slew-delay-us", 0);
priv->wait_retry_ms = fdtdec_get_int(blob, node, "wait-retry-us", 0) /
1000;
priv->wait_free_ms = fdtdec_get_int(blob, node, "wait-free-us", 0) /
1000;
ret = gpio_request_by_name(dev, "our-claim-gpio", 0, &priv->ap_claim,
GPIOD_IS_OUT);
if (ret)
goto err;
ret = gpio_request_by_name(dev, "their-claim-gpios", 0, &priv->ec_claim,
GPIOD_IS_IN);
if (ret)
goto err_ec_gpio;
return 0;
err_ec_gpio:
dm_gpio_free(dev, &priv->ap_claim);
err:
debug("%s: ret=%d\n", __func__, ret);
return ret;
}
int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob)
{
/* Decode interface-specific FDT params */
dev->max_frequency = fdtdec_get_int(blob, dev->node,
"spi-max-frequency", 500000);
dev->cs = fdtdec_get_int(blob, dev->node, "reg", 0);
return 0;
}
int spi_slave_ofdata_to_platdata(const void *blob, int node,
struct dm_spi_slave_platdata *plat)
{
int mode = 0, mode_rx = 0;
int value;
plat->cs = fdtdec_get_int(blob, node, "reg", -1);
plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 0);
if (fdtdec_get_bool(blob, node, "spi-cpol"))
mode |= SPI_CPOL;
if (fdtdec_get_bool(blob, node, "spi-cpha"))
mode |= SPI_CPHA;
if (fdtdec_get_bool(blob, node, "spi-cs-high"))
mode |= SPI_CS_HIGH;
if (fdtdec_get_bool(blob, node, "spi-3wire"))
mode |= SPI_3WIRE;
if (fdtdec_get_bool(blob, node, "spi-half-duplex"))
mode |= SPI_PREAMBLE;
/* Device DUAL/QUAD mode */
value = fdtdec_get_uint(blob, node, "spi-tx-bus-width", 1);
switch (value) {
case 1:
break;
case 2:
mode |= SPI_TX_DUAL;
break;
case 4:
mode |= SPI_TX_QUAD;
break;
default:
error("spi-tx-bus-width %d not supported\n", value);
break;
}
plat->mode = mode;
value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1);
switch (value) {
case 1:
break;
case 2:
mode_rx |= SPI_RX_DUAL;
break;
case 4:
mode_rx |= SPI_RX_QUAD;
break;
default:
error("spi-rx-bus-width %d not supported\n", value);
break;
}
plat->mode_rx = mode_rx;
return 0;
}
static int altera_nios2_probe(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
gd->cpu_clk = fdtdec_get_int(blob, node,
"clock-frequency", 0);
gd->arch.dcache_line_size = fdtdec_get_int(blob, node,
"dcache-line-size", 0);
gd->arch.icache_line_size = fdtdec_get_int(blob, node,
"icache-line-size", 0);
gd->arch.dcache_size = fdtdec_get_int(blob, node,
"dcache-size", 0);
gd->arch.icache_size = fdtdec_get_int(blob, node,
"icache-size", 0);
gd->arch.reset_addr = fdtdec_get_int(blob, node,
"altr,reset-addr", 0);
gd->arch.exception_addr = fdtdec_get_int(blob, node,
"altr,exception-addr", 0);
gd->arch.has_initda = fdtdec_get_int(blob, node,
"altr,has-initda", 0);
gd->arch.has_mmu = fdtdec_get_int(blob, node,
"altr,has-mmu", 0);
gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x80000000;
gd->arch.mem_region_base = gd->arch.has_mmu ? 0xc0000000 : 0x00000000;
gd->arch.physaddr_mask = gd->arch.has_mmu ? 0x1fffffff : 0x7fffffff;
return 0;
}
int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
{
struct ns16550_platdata *plat = dev->platdata;
fdt_addr_t addr;
/* try Processor Local Bus device first */
addr = dev_get_addr(dev);
#if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI)
if (addr == FDT_ADDR_T_NONE) {
/* then try pci device */
struct fdt_pci_addr pci_addr;
u32 bar;
int ret;
/* we prefer to use a memory-mapped register */
ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
FDT_PCI_SPACE_MEM32, "reg",
&pci_addr);
if (ret) {
/* try if there is any i/o-mapped register */
ret = fdtdec_get_pci_addr(gd->fdt_blob,
dev->of_offset,
FDT_PCI_SPACE_IO,
"reg", &pci_addr);
if (ret)
return ret;
}
ret = fdtdec_get_pci_bar32(dev, &pci_addr, &bar);
if (ret)
return ret;
addr = bar;
}
#endif
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
plat->base = addr;
plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"reg-shift", 0);
plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"clock-frequency",
CONFIG_SYS_NS16550_CLK);
if (!plat->clock) {
debug("ns16550 clock not defined\n");
return -EINVAL;
}
return 0;
}
static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
{
struct reg_data {
u32 addr;
u32 size;
} regs_data[2];
struct fsl_qspi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
int ret, flash_num = 0, subnode;
if (fdtdec_get_bool(blob, node, "big-endian"))
plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
ret = fdtdec_get_int_array(blob, node, "reg", (u32 *)regs_data,
sizeof(regs_data)/sizeof(u32));
if (ret) {
debug("Error: can't get base addresses (ret = %d)!\n", ret);
return -ENOMEM;
}
/* Count flash numbers */
fdt_for_each_subnode(blob, subnode, node)
++flash_num;
if (flash_num == 0) {
debug("Error: Missing flashes!\n");
return -ENODEV;
}
plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
FSL_QSPI_DEFAULT_SCK_FREQ);
plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
FSL_QSPI_MAX_CHIPSELECT_NUM);
plat->reg_base = regs_data[0].addr;
plat->amba_base = regs_data[1].addr;
plat->amba_total_size = regs_data[1].size;
plat->flash_num = flash_num;
debug("%s: regs=<0x%x> <0x%x, 0x%x>, max-frequency=%d, endianess=%s\n",
__func__,
plat->reg_base,
plat->amba_base,
plat->amba_total_size,
plat->speed_hz,
plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
);
return 0;
}
/**
* exynos_pinctrl_set_state: configure a pin state.
* dev: the pinctrl device to be configured.
* config: the state to be configured.
*/
int exynos_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
const void *fdt = gd->fdt_blob;
int node = config->of_offset;
unsigned int count, idx, pin_num;
unsigned int pinfunc, pinpud, pindrv;
unsigned long reg, value;
const char *name;
/*
* refer to the following document for the pinctrl bindings
* linux/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
*/
count = fdt_stringlist_count(fdt, node, "samsung,pins");
if (count <= 0)
return -EINVAL;
pinfunc = fdtdec_get_int(fdt, node, "samsung,pin-function", -1);
pinpud = fdtdec_get_int(fdt, node, "samsung,pin-pud", -1);
pindrv = fdtdec_get_int(fdt, node, "samsung,pin-drv", -1);
for (idx = 0; idx < count; idx++) {
name = fdt_stringlist_get(fdt, node, "samsung,pins", idx, NULL);
if (!name)
continue;
reg = pin_to_bank_base(dev, name, &pin_num);
if (pinfunc != -1) {
value = readl(reg + PIN_CON);
value &= ~(0xf << (pin_num << 2));
value |= (pinfunc << (pin_num << 2));
writel(value, reg + PIN_CON);
}
if (pinpud != -1) {
value = readl(reg + PIN_PUD);
value &= ~(0x3 << (pin_num << 1));
value |= (pinpud << (pin_num << 1));
writel(value, reg + PIN_PUD);
}
if (pindrv != -1) {
value = readl(reg + PIN_DRV);
value &= ~(0x3 << (pin_num << 1));
value |= (pindrv << (pin_num << 1));
writel(value, reg + PIN_DRV);
}
}
return 0;
}
static int board_i2c_arb_init(const void *blob)
{
int node;
local.arbitrate_node = -1;
node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_ARBITRATOR);
if (node < 0) {
debug("Cannot find bus arbitrator node\n");
return 0;
}
if (fdtdec_decode_gpio(blob, node, "google,ap-claim-gpios",
&local.ap_claim) ||
fdtdec_decode_gpio(blob, node, "google,ec-claim-gpios",
&local.ec_claim)) {
debug("Cannot find bus arbitrator GPIOs\n");
return 0;
}
if (fdtdec_setup_gpio(&local.ap_claim) ||
fdtdec_setup_gpio(&local.ec_claim)) {
debug("Cannot claim arbitration GPIOs\n");
return -1;
}
/* We are currently not claiming the bus */
gpio_direction_output(local.ap_claim.gpio, 1);
gpio_direction_input(local.ec_claim.gpio);
gpio_set_pull(local.ec_claim.gpio, EXYNOS_GPIO_PULL_UP);
local.arbitrate_node = fdtdec_lookup_phandle(blob, node,
"google,arbitrate-bus");
if (local.arbitrate_node < 0) {
debug("Cannot find bus to arbitrate\n");
return -1;
}
local.slew_delay_us = fdtdec_get_int(blob, node,
"google,slew-delay-us", 10);
local.wait_retry_ms = fdtdec_get_int(blob, node,
"google,wait-retry-us", 2000);
local.wait_retry_ms = DIV_ROUND_UP(local.wait_retry_ms, 1000);
local.wait_free_ms = fdtdec_get_int(blob, node,
"google,wait-free-us", 50000);
local.wait_free_ms = DIV_ROUND_UP(local.wait_free_ms, 1000);
debug("Bus arbitration ready on fdt node %d\n", local.arbitrate_node);
return 0;
}
int i2c_chip_ofdata_to_platdata(const void *blob, int node,
struct dm_i2c_chip *chip)
{
chip->offset_len = fdtdec_get_int(gd->fdt_blob, node,
"u-boot,i2c-offset-len", 1);
chip->flags = 0;
chip->chip_addr = fdtdec_get_int(gd->fdt_blob, node, "reg", -1);
if (chip->chip_addr == -1) {
debug("%s: I2C Node '%s' has no 'reg' property\n", __func__,
fdt_get_name(blob, node, NULL));
return -EINVAL;
}
return 0;
}
static int spi_post_probe(struct udevice *bus)
{
struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
"spi-max-frequency", 0);
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
struct dm_spi_ops *ops = spi_get_ops(bus);
if (ops->claim_bus)
ops->claim_bus += gd->reloc_off;
if (ops->release_bus)
ops->release_bus += gd->reloc_off;
if (ops->set_wordlen)
ops->set_wordlen += gd->reloc_off;
if (ops->xfer)
ops->xfer += gd->reloc_off;
if (ops->set_speed)
ops->set_speed += gd->reloc_off;
if (ops->set_mode)
ops->set_mode += gd->reloc_off;
if (ops->cs_info)
ops->cs_info += gd->reloc_off;
#endif
return 0;
}
static int sandbox_sdl_bind(struct udevice *dev)
{
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
struct sandbox_sdl_plat *plat = dev_get_platdata(dev);
const void *blob = gd->fdt_blob;
int node = dev->of_offset;
int ret = 0;
plat->xres = fdtdec_get_int(blob, node, "xres", LCD_MAX_WIDTH);
plat->yres = fdtdec_get_int(blob, node, "yres", LCD_MAX_HEIGHT);
plat->bpix = VIDEO_BPP16;
uc_plat->size = plat->xres * plat->yres * (1 << plat->bpix) / 8;
debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
return ret;
}
/**
* cros_ec_read_state() - read the sandbox EC state from the state file
*
* If data is available, then blob and node will provide access to it. If
* not this function sets up an empty EC.
*
* @param blob: Pointer to device tree blob, or NULL if no data to read
* @param node: Node offset to read from
*/
static int cros_ec_read_state(const void *blob, int node)
{
struct ec_state *ec = &s_state;
const char *prop;
int len;
/* Set everything to defaults */
ec->current_image = EC_IMAGE_RO;
if (!blob)
return 0;
/* Read the data if available */
ec->current_image = fdtdec_get_int(blob, node, "current-image",
EC_IMAGE_RO);
prop = fdt_getprop(blob, node, "vbnv-context", &len);
if (prop && len == sizeof(ec->vbnv_context))
memcpy(ec->vbnv_context, prop, len);
prop = fdt_getprop(blob, node, "flash-data", &len);
if (prop) {
ec->flash_data_len = len;
ec->flash_data = os_malloc(len);
if (!ec->flash_data)
return -ENOMEM;
memcpy(ec->flash_data, prop, len);
debug("%s: Loaded EC flash data size %#x\n", __func__, len);
}
return 0;
}
static int ks2_eth_bind_slaves(struct udevice *dev, int gbe, int *gbe_0)
{
const void *fdt = gd->fdt_blob;
struct udevice *sl_dev;
int interfaces;
int sec_slave;
int slave;
int ret;
char *slave_name;
interfaces = fdt_subnode_offset(fdt, gbe, "interfaces");
fdt_for_each_subnode(fdt, slave, interfaces) {
int slave_no;
slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
if (slave_no == -ENOENT)
continue;
if (slave_no == 0) {
/* This is the current eth device */
*gbe_0 = slave;
} else {
/* Slave devices to be registered */
slave_name = malloc(20);
snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
ret = device_bind_driver_to_node(dev, "eth_ks2_sl",
slave_name, slave,
&sl_dev);
if (ret) {
error("ks2_net - not able to bind slave interfaces\n");
return ret;
}
}
}
static int pic32_sdhci_probe(struct udevice *dev)
{
struct sdhci_host *host = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
u32 f_min_max[2];
fdt_addr_t addr;
fdt_size_t size;
int ret;
addr = fdtdec_get_addr_size(fdt, dev->of_offset, "reg", &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
host->ioaddr = ioremap(addr, size);
host->name = dev->name;
host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_NO_CD;
host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"bus-width", 4);
ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
"clock-freq-min-max", f_min_max, 2);
if (ret) {
printf("sdhci: clock-freq-min-max not found\n");
return ret;
}
ret = add_sdhci(host, f_min_max[1], f_min_max[0]);
if (ret)
return ret;
host->mmc->dev = dev;
return 0;
}
static int owl_mac_parse_fdtdec(struct owl_mac_info *info)
{
int node,ret;
//const char *mac_compat = OWL_MAC_COMPAT;
node = fdt_node_offset_by_compatible(gd->fdt_blob,0,OWL_MAC_COMPAT);
if(node <= 0){
debug("Can't get owl-ethernet node\n");
return -1;
}
ret = fdtdec_get_is_enabled(gd->fdt_blob,node);
if(!ret){
debug("Disable by dts\n");
return -1;
}
info->phy_addr = fdtdec_get_int(gd->fdt_blob, node, "phy_addr", -1);
printf("owl_mac_parse_fdtdec,phy_addr %d\n",info->phy_addr);
owl_fdtdec_decode_gpio(gd->fdt_blob, node, "phy-power-gpios",&info->phy_power_gpio);
owl_fdtdec_decode_gpio(gd->fdt_blob, node, "phy-reset-gpios",&info->phy_reset_gpio);
printf("owl_mac_parse_fdtdec,power-gpio %d\n",info->phy_power_gpio.gpio,info->phy_power_gpio.flags);
printf("owl_mac_parse_fdtdec,reset-gpio %d\n",info->phy_reset_gpio.gpio,info->phy_reset_gpio.flags);
return 0;
}
static int pwm_regulator_ofdata_to_platdata(struct udevice *dev)
{
struct pwm_regulator_info *priv = dev_get_priv(dev);
struct fdtdec_phandle_args args;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
int ret;
ret = fdtdec_parse_phandle_with_args(blob, node, "pwms", "#pwm-cells",
0, 0, &args);
if (ret) {
debug("%s: Cannot get PWM phandle: ret=%d\n", __func__, ret);
return ret;
}
priv->period_ns = args.args[1];
priv->polarity = args.args[2];
priv->init_voltage = fdtdec_get_int(blob, node,
"regulator-init-microvolt", -1);
if (priv->init_voltage < 0) {
printf("Cannot find regulator pwm init_voltage\n");
return -EINVAL;
}
ret = uclass_get_device_by_of_offset(UCLASS_PWM, args.node, &priv->pwm);
if (ret) {
debug("%s: Cannot get PWM: ret=%d\n", __func__, ret);
return ret;
}
return 0;
}
static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
int offset = 0;
const char *phy_mode;
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
/* Hardcode for now */
priv->emio = 0;
priv->phyaddr = -1;
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
"phy-handle");
if (offset > 0)
priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
priv->interface = pdata->phy_interface;
priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio");
printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
return 0;
}
static int rk32_lcdc_parse_dt(struct lcdc_device *lcdc_dev,
const void *blob)
{
int order = FB0_WIN0_FB1_WIN1_FB2_WIN2;
if (lcdc_dev->id == 0)
lcdc_dev->node = fdt_path_offset(blob, "lcdc0");
else
lcdc_dev->node = fdt_path_offset(blob, "lcdc1");
if (lcdc_dev->node < 0) {
debug("rk32 lcdc node is not found\n");
return -ENODEV;
}
if (!fdt_device_is_available(blob, lcdc_dev->node)) {
debug("device lcdc is disabled\n");
return -EPERM;
}
lcdc_dev->regs = fdtdec_get_addr(blob, lcdc_dev->node, "reg");
order = fdtdec_get_int(blob, lcdc_dev->node,
"rockchip,fb-win-map", order);
lcdc_dev->dft_win = order % 10;
return 0;
}
static int arasan_sdhci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
struct rockchip_sdhc *prv = dev_get_priv(dev);
struct sdhci_host *host = &prv->host;
int max_frequency, ret;
struct clk clk;
max_frequency = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"max-frequency", 0);
ret = clk_get_by_index(dev, 0, &clk);
if (!ret) {
ret = clk_set_rate(&clk, max_frequency);
if (IS_ERR_VALUE(ret))
printf("%s clk set rate fail!\n", __func__);
} else {
printf("%s fail to get clk\n", __func__);
}
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
host->max_clk = max_frequency;
ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
host->mmc = &plat->mmc;
if (ret)
return ret;
host->mmc->priv = &prv->host;
host->mmc->dev = dev;
upriv->mmc = host->mmc;
return sdhci_probe(dev);
}
static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host)
{
int bus_width, dev_id;
unsigned int base;
/* Get device id */
dev_id = pinmux_decode_periph_id(blob, node);
if (dev_id < PERIPH_ID_SDMMC0 && dev_id > PERIPH_ID_SDMMC3) {
debug("MMC: Can't get device id\n");
return -1;
}
host->index = dev_id - PERIPH_ID_SDMMC0;
/* Get bus width */
bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
if (bus_width <= 0) {
debug("MMC: Can't get bus-width\n");
return -1;
}
host->bus_width = bus_width;
/* Get the base address from the device node */
base = fdtdec_get_addr(blob, node, "reg");
if (!base) {
debug("MMC: Can't get base address\n");
return -1;
}
host->ioaddr = (void *)base;
fdtdec_decode_gpio(blob, node, "pwr-gpios", &host->pwr_gpio);
fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio);
return 0;
}
