//
// Retrieve a data object from the data base (in memory copy)
//
bool
flash_get_config(char *key, void *val, int type)
{
unsigned char *dp;
void *val_ptr;
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG_READONLY_FALLBACK
struct _config *save_config = 0;
bool res;
#endif
if (!config_ok) return false;
if ((dp = flash_lookup_config(key)) != (unsigned char *)NULL) {
if (CONFIG_OBJECT_TYPE(dp) == type) {
val_ptr = (void *)CONFIG_OBJECT_VALUE(dp);
switch (type) {
// Note: the data may be unaligned in the configuration data
case CONFIG_BOOL:
memcpy(val, val_ptr, sizeof(bool));
break;
case CONFIG_INT:
memcpy(val, val_ptr, sizeof(unsigned long));
break;
#ifdef CYGPKG_REDBOOT_NETWORKING
case CONFIG_IP:
memcpy(val, val_ptr, sizeof(in_addr_t));
break;
case CONFIG_ESA:
memcpy(val, val_ptr, sizeof(enet_addr_t));
break;
#endif
#if defined(CYGHWR_NET_DRIVERS) && (CYGHWR_NET_DRIVERS > 1)
case CONFIG_NETPORT:
#endif
case CONFIG_STRING:
case CONFIG_SCRIPT:
// Just return a pointer to the script/line
*(unsigned char **)val = (unsigned char *)val_ptr;
break;
}
} else {
diag_printf("Request for config value '%s' - wrong type\n", key);
}
return true;
}
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG_READONLY_FALLBACK
// Did not find key. Is configuration data valid?
// Check to see if the config data is valid, if not, revert to
// readonly mode, by setting config to readonly_config. We
// will set it back before we leave this function.
if ( (config != readonly_config) && ((flash_crc(config) != config->cksum) ||
(config->key1 != CONFIG_KEY1)|| (config->key2 != CONFIG_KEY2))) {
save_config = config;
config = readonly_config;
if ((flash_crc(config) != config->cksum) ||
(config->key1 != CONFIG_KEY1)|| (config->key2 != CONFIG_KEY2)) {
diag_printf("FLASH configuration checksum error or invalid key\n");
config = save_config;
return false;
}
else{
diag_printf("Getting config information in READONLY mode\n");
res = flash_get_config(key, val, type);
config = save_config;
return res;
}
}
#endif
return false;
}
// Initialize the interface - performed at system startup
// This function must set up the interface, including arranging to
// handle interrupts, etc, so that it may be "started" cheaply later.
static bool
s3esk_eth_init(struct cyg_netdevtab_entry *dtp)
{
struct eth_drv_sc *sc = (struct eth_drv_sc *)dtp->device_instance;
struct s3esk_eth_info *qi = (struct s3esk_eth_info *)sc->driver_private;
//Xuint32 opt;
unsigned char _enaddr[6];
bool esa_ok;
// Try to read the ethernet address of the transciever ...
#if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG)
esa_ok = flash_get_config(qi->esa_key, _enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
qi->esa_key, _enaddr, CONFIG_ESA);
#endif
if (esa_ok) {
memcpy(qi->enaddr, _enaddr, sizeof(qi->enaddr));
} else {
// No 'flash config' data available - use default
diag_printf("s3esk_ETH - Warning! Using default ESA for '%s'\n", dtp->name);
}
// Initialize Xilinx driver
if (XEmacLite_Initialize(&qi->dev, XPAR_ETHERNET_MAC_DEVICE_ID) != XST_SUCCESS) {
diag_printf("s3esk_ETH - can't initialize\n");
return false;
}
//if (XEmac_mIsSgDma(&qi->dev)) {
// diag_printf("s3esk_ETH - DMA support?\n");
// return false;
//}
if (XEmacLite_SelfTest(&qi->dev) != XST_SUCCESS) {
diag_printf("s3esk_ETH - self test failed\n");
return false;
}
//XEmac_ClearStats(&qi->dev);
// Configure device operating mode
//opt = XEM_UNICAST_OPTION |
// XEM_BROADCAST_OPTION |
// XEM_INSERT_PAD_OPTION |
// XEM_INSERT_FCS_OPTION |
// XEM_STRIP_PAD_FCS_OPTION;
//if (XEmac_SetOptions(&qi->dev, opt) != XST_SUCCESS) {
// diag_printf("s3esk_ETH - can't configure mode\n");
// return false;
//}
//if (XEmacLite_SetMacAddress(&qi->dev, qi->enaddr) != XST_SUCCESS) {
// diag_printf("s3esk_ETH - can't set ESA\n");
// return false;
//}
XEmacLite_SetMacAddress(&qi->dev, qi->enaddr);
// Set up FIFO handling routines - these are callbacks from the
// Xilinx driver code which happen at interrupt time
XEmacLite_SetSendHandler(&qi->dev, sc, s3esk_eth_TxEvent);
XEmacLite_SetRecvHandler(&qi->dev, sc, s3esk_eth_RxEvent);
//XEmac_SetErrorHandler(&qi->dev, sc, s3esk_eth_ErrEvent);
#ifdef CYGPKG_NET
// Set up to handle interrupts
cyg_drv_interrupt_create(qi->int_vector,
0, // Highest //CYGARC_SIU_PRIORITY_HIGH,
(cyg_addrword_t)sc, // Data passed to ISR
(cyg_ISR_t *)s3esk_eth_isr,
(cyg_DSR_t *)eth_drv_dsr,
&qi->s3esk_eth_interrupt_handle,
&qi->s3esk_eth_interrupt);
cyg_drv_interrupt_attach(qi->s3esk_eth_interrupt_handle);
cyg_drv_interrupt_acknowledge(qi->int_vector);
cyg_drv_interrupt_unmask(qi->int_vector);
#endif
// Operating mode
_s3esk_dev = &qi->dev;
//if (!_eth_phy_init(qi->phy)) {
// return false;
//}
//#ifdef CYGSEM_DEVS_ETH_POWERPC_s3esk_RESET_PHY
//_eth_phy_reset(qi->phy);
//#endif
// Initialize upper level driver for ecos
(sc->funs->eth_drv->init)(sc, (unsigned char *)&qi->enaddr);
return true;
}
//
// Attempt to get configuration information from the FLASH.
// If available (i.e. good checksum, etc), initialize "known"
// values for later use.
//
static void
load_flash_config(void)
{
bool use_boot_script;
unsigned char *cfg_temp = (unsigned char *)workspace_end;
#ifdef CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA_FLASH
void *err_addr;
#endif
config_ok = false;
script = (unsigned char *)0;
cfg_temp -= sizeof(struct _config); // Space for primary config data
config = (struct _config *)cfg_temp;
cfg_temp -= sizeof(struct _config); // Space for backup config data
backup_config = (struct _config *)cfg_temp;
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG_READONLY_FALLBACK
cfg_temp -= sizeof(struct _config); // Space for readonly copy of config data
readonly_config = (struct _config *)cfg_temp;
#endif
workspace_end = cfg_temp;
#ifdef CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA_FLASH
if (!do_flash_init()) return;
#ifdef CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG
cfg_size = _rup(sizeof(struct _config), sizeof(struct fis_image_desc));
if ((fisdir_size-cfg_size) < (CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT *
CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_SIZE)) {
// Too bad this can't be checked at compile/build time
diag_printf("Sorry, FLASH config exceeds available space in FIS directory\n");
return;
}
cfg_base = (void *)(((CYG_ADDRESS)fis_addr + fisdir_size) - cfg_size);
fisdir_size -= cfg_size;
#else
cfg_size = (flash_block_size > sizeof(struct _config)) ?
sizeof(struct _config) :
_rup(sizeof(struct _config), flash_block_size);
if (CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK < 0) {
cfg_base = (void *)((CYG_ADDRESS)flash_end + 1 -
_rup(_rup((-CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK*flash_block_size), cfg_size), flash_block_size));
} else {
cfg_base = (void *)((CYG_ADDRESS)flash_start +
_rup(_rup((CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK*flash_block_size), cfg_size), flash_block_size));
}
#endif
FLASH_READ(cfg_base, config, sizeof(struct _config), &err_addr);
conf_endian_fixup(config);
#else
read_eeprom(config, sizeof(struct _config)); // into 'config'
#endif
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG_READONLY_FALLBACK
memcpy(readonly_config, config, sizeof(struct _config));
#endif
if ((flash_crc(config) != config->cksum) ||
(config->key1 != CONFIG_KEY1)|| (config->key2 != CONFIG_KEY2)) {
diag_printf("**Warning** FLASH configuration checksum error or invalid key\n");
diag_printf("Use 'fconfig -i' to [re]initialize database\n");
config_init();
return;
}
config_ok = true;
flash_get_config("boot_script", &use_boot_script, CONFIG_BOOL);
if (use_boot_script) {
flash_get_config("boot_script_data", &script, CONFIG_SCRIPT);
flash_get_config("boot_script_timeout", &script_timeout, CONFIG_INT);
}
#ifdef CYGSEM_REDBOOT_VARIABLE_BAUD_RATE
if (flash_get_config("console_baud_rate", &console_baud_rate, CONFIG_INT)) {
extern int set_console_baud_rate(int);
set_console_baud_rate(console_baud_rate);
}
#endif
}
static int
get_config(unsigned char *dp, char *title, int list_opt, char *newvalue )
{
char line[256], hold_line[256], *sp, *lp;
int ret;
bool hold_bool_val, new_bool_val, enable;
unsigned long hold_int_val, new_int_val;
#ifdef CYGPKG_REDBOOT_NETWORKING
in_addr_t hold_ip_val, new_ip_val;
enet_addr_t hold_esa_val;
int esa_ptr;
char *esp;
#endif
void *val_ptr;
int type;
if (CONFIG_OBJECT_ENABLE_KEYLEN(dp)) {
flash_get_config(CONFIG_OBJECT_ENABLE_KEY(dp), &enable, CONFIG_BOOL);
if (((bool)CONFIG_OBJECT_ENABLE_SENSE(dp) && !enable) ||
(!(bool)CONFIG_OBJECT_ENABLE_SENSE(dp) && enable)) {
return CONFIG_OK; // Disabled field
}
}
lp = line; *lp = '\0';
val_ptr = (void *)CONFIG_OBJECT_VALUE(dp);
if (LIST_OPT_NICKNAMES & list_opt)
diag_printf("%s: ", CONFIG_OBJECT_KEY(dp));
if (LIST_OPT_FULLNAMES & list_opt) {
if (title != (char *)NULL) {
diag_printf("%s: ", title);
} else {
diag_printf("%s: ", CONFIG_OBJECT_KEY(dp));
}
}
switch (type = CONFIG_OBJECT_TYPE(dp)) {
case CONFIG_BOOL:
memcpy(&hold_bool_val, val_ptr, sizeof(bool));
lp += diag_sprintf(lp, "%s", hold_bool_val ? "true" : "false");
break;
case CONFIG_INT:
memcpy(&hold_int_val, val_ptr, sizeof(unsigned long));
lp += diag_sprintf(lp, "%ld", hold_int_val);
break;
#ifdef CYGPKG_REDBOOT_NETWORKING
case CONFIG_IP:
lp += diag_sprintf(lp, "%s", inet_ntoa((in_addr_t *)val_ptr));
if (0 == strcmp("0.0.0.0", line) && !(LIST_OPT_LIST_ONLY & list_opt)) {
// then we have a deeply unhelpful starting text - kill it off
// (unless we are just listing all values)
lp = line; *lp = '\0';
}
break;
case CONFIG_ESA:
for (esa_ptr = 0; esa_ptr < sizeof(enet_addr_t); esa_ptr++) {
lp += diag_sprintf(lp, "0x%02X", ((unsigned char *)val_ptr)[esa_ptr]);
if (esa_ptr < (sizeof(enet_addr_t)-1)) lp += diag_sprintf(lp, ":");
}
break;
#if defined(CYGHWR_NET_DRIVERS) && (CYGHWR_NET_DRIVERS > 1)
case CONFIG_NETPORT:
lp += diag_sprintf(lp, "%s", (unsigned char *)val_ptr);
break;
#endif
#endif
case CONFIG_STRING:
lp += diag_sprintf(lp, "%s", (unsigned char *)val_ptr);
break;
case CONFIG_SCRIPT:
diag_printf("\n");
sp = lp = (unsigned char *)val_ptr;
while (*sp) {
while (*lp != '\n') lp++;
*lp = '\0';
diag_printf(".. %s\n", sp);
*lp++ = '\n';
sp = lp;
}
break;
}
if (LIST_OPT_LIST_ONLY & list_opt) {
diag_printf("%s\n", line);
return CONFIG_OK;
}
if (type != CONFIG_SCRIPT) {
if (NULL != newvalue) {
ret = strlen(newvalue);
if (ret > sizeof(line))
return CONFIG_BAD;
strcpy(hold_line, line); // Hold the old value for comparison
strcpy(line, newvalue);
diag_printf("Setting to %s\n", newvalue);
} else {
// read from terminal
strcpy(hold_line, line);
if (LIST_OPT_DUMBTERM & list_opt) {
diag_printf( (CONFIG_STRING == type ?
"%s > " :
"%s ? " ), line);
*line = '\0';
}
ret = _rb_gets_preloaded(line, sizeof(line), 0);
}
if (ret < 0) return CONFIG_ABORT;
// empty input - leave value untouched (else DNS goes away for a
// minute to try to look it up) but we must accept empty value for strings.
if (0 == line[0] && CONFIG_STRING != type) return CONFIG_OK;
if (strcmp(line, hold_line) == 0) return CONFIG_OK; // Just a CR - leave value untouched
lp = &line[strlen(line)-1];
if (*lp == '.') return CONFIG_DONE;
if (*lp == '^') return CONFIG_BACK;
}
switch (type) {
case CONFIG_BOOL:
memcpy(&hold_bool_val, val_ptr, sizeof(bool));
if (!parse_bool(line, &new_bool_val)) {
return CONFIG_BAD;
}
if (hold_bool_val != new_bool_val) {
memcpy(val_ptr, &new_bool_val, sizeof(bool));
return CONFIG_CHANGED;
} else {
return CONFIG_OK;
}
break;
case CONFIG_INT:
memcpy(&hold_int_val, val_ptr, sizeof(unsigned long));
if (!parse_num(line, &new_int_val, 0, 0)) {
return CONFIG_BAD;
}
if (hold_int_val != new_int_val) {
memcpy(val_ptr, &new_int_val, sizeof(unsigned long));
return CONFIG_CHANGED;
} else {
return CONFIG_OK;
}
break;
#ifdef CYGPKG_REDBOOT_NETWORKING
case CONFIG_IP:
memcpy(&hold_ip_val.s_addr, &((in_addr_t *)val_ptr)->s_addr, sizeof(in_addr_t));
if (!_gethostbyname(line, &new_ip_val)) {
return CONFIG_BAD;
}
if (hold_ip_val.s_addr != new_ip_val.s_addr) {
memcpy(val_ptr, &new_ip_val, sizeof(in_addr_t));
return CONFIG_CHANGED;
} else {
return CONFIG_OK;
}
break;
case CONFIG_ESA:
memcpy(&hold_esa_val, val_ptr, sizeof(enet_addr_t));
esp = line;
for (esa_ptr = 0; esa_ptr < sizeof(enet_addr_t); esa_ptr++) {
unsigned long esa_byte;
if (!parse_num(esp, &esa_byte, &esp, ":")) {
memcpy(val_ptr, &hold_esa_val, sizeof(enet_addr_t));
return CONFIG_BAD;
}
((unsigned char *)val_ptr)[esa_ptr] = esa_byte;
}
#ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
if (!cyg_plf_redboot_esa_validate(val_ptr)) {
memcpy(val_ptr, &hold_esa_val, sizeof(enet_addr_t));
return CONFIG_BAD;
}
#endif
return CONFIG_CHANGED;
break;
#if defined(CYGHWR_NET_DRIVERS) && (CYGHWR_NET_DRIVERS > 1)
case CONFIG_NETPORT:
if (strlen(line) >= MAX_STRING_LENGTH || net_devindex(line) < 0) {
int index;
const char *name;
diag_printf("Sorry, Port name must be one of:\n");
for (index = 0; (name = net_devname(index)) != NULL; index++)
diag_printf(" %s\n", name);
return CONFIG_BAD;
}
strcpy((unsigned char *)val_ptr, line);
break;
#endif
#endif
case CONFIG_SCRIPT:
// Assume it always changes
sp = (unsigned char *)val_ptr;
diag_printf("Enter script, terminate with empty line\n");
while (true) {
*sp = '\0';
diag_printf(">> ");
ret = _rb_gets(line, sizeof(line), 0);
if (ret < 0) return CONFIG_ABORT;
if (strlen(line) == 0) break;
lp = line;
while (*lp) {
*sp++ = *lp++;
}
*sp++ = '\n';
}
break;
case CONFIG_STRING:
if (strlen(line) >= MAX_STRING_LENGTH) {
diag_printf("Sorry, value is too long\n");
return CONFIG_BAD;
}
strcpy((unsigned char *)val_ptr, line);
break;
}
return CONFIG_CHANGED;
}
//
// Initialize the interface - performed at system startup
// This function must set up the interface, including arranging to
// handle interrupts, etc, so that it may be "started" cheaply later.
//
static bool
quicc_eth_init(struct cyg_netdevtab_entry *tab)
{
struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
volatile EPPC *eppc = (volatile EPPC *)eppc_base();
struct cp_bufdesc *rxbd, *txbd;
unsigned char *RxBUF, *TxBUF, *ep, *ap;
volatile struct ethernet_pram *enet_pram;
volatile struct scc_regs *scc;
int TxBD, RxBD;
int cache_state;
int i;
bool esa_ok;
// Fetch the board address from the VPD
#define VPD_ETHERNET_ADDRESS 0x08
if (_mbx_fetch_VPD(VPD_ETHERNET_ADDRESS, enaddr, sizeof(enaddr)) == 0) {
#if defined(CYGPKG_REDBOOT) && \
defined(CYGSEM_REDBOOT_FLASH_CONFIG)
esa_ok = flash_get_config("quicc_esa", enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"quicc_esa", enaddr, CONFIG_ESA);
#endif
if (!esa_ok) {
// Can't figure out ESA
diag_printf("QUICC_ETH - Warning! ESA unknown\n");
memcpy(&enaddr, &_default_enaddr, sizeof(enaddr));
}
}
// Ensure consistent state between cache and what the QUICC sees
HAL_DCACHE_IS_ENABLED(cache_state);
HAL_DCACHE_SYNC();
HAL_DCACHE_DISABLE();
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
// Set up to handle interrupts
cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_CPM_SCC1,
CYGARC_SIU_PRIORITY_HIGH,
(cyg_addrword_t)sc, // Data item passed to interrupt handler
(cyg_ISR_t *)quicc_eth_isr,
(cyg_DSR_t *)eth_drv_dsr,
&quicc_eth_interrupt_handle,
&quicc_eth_interrupt);
cyg_drv_interrupt_attach(quicc_eth_interrupt_handle);
cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_CPM_SCC1);
cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_CPM_SCC1);
#endif
qi->pram = enet_pram = &eppc->pram[0].enet_scc;
qi->ctl = scc = &eppc->scc_regs[0]; // Use SCC1
// Shut down ethernet, in case it is already running
scc->scc_gsmr_l &= ~(QUICC_SCC_GSML_ENR | QUICC_SCC_GSML_ENT);
memset((void *)enet_pram, 0, sizeof(*enet_pram));
TxBD = 0x2C00; // FIXME
RxBD = TxBD + CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM * sizeof(struct cp_bufdesc);
txbd = (struct cp_bufdesc *)((char *)eppc + TxBD);
rxbd = (struct cp_bufdesc *)((char *)eppc + RxBD);
qi->tbase = txbd;
qi->txbd = txbd;
qi->tnext = txbd;
qi->rbase = rxbd;
qi->rxbd = rxbd;
qi->rnext = rxbd;
RxBUF = &quicc_eth_rxbufs[0][0];
TxBUF = &quicc_eth_txbufs[0][0];
// setup buffer descriptors
for (i = 0; i < CYGNUM_DEVS_ETH_POWERPC_QUICC_RxNUM; i++) {
rxbd->length = 0;
rxbd->buffer = RxBUF;
rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int;
RxBUF += CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
rxbd++;
}
rxbd--;
rxbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer
for (i = 0; i < CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM; i++) {
txbd->length = 0;
txbd->buffer = TxBUF;
txbd->ctrl = 0;
TxBUF += CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
txbd++;
}
txbd--;
txbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer
// Set up parallel ports for connection to MC68160 ethernet tranceiver
eppc->pio_papar |= (QUICC_MBX_PA_RXD | QUICC_MBX_PA_TXD);
eppc->pio_padir &= ~(QUICC_MBX_PA_RXD | QUICC_MBX_PA_TXD);
eppc->pio_paodr &= ~QUICC_MBX_PA_TXD;
eppc->pio_pcpar &= ~(QUICC_MBX_PC_COLLISION | QUICC_MBX_PC_Rx_ENABLE);
eppc->pio_pcdir &= ~(QUICC_MBX_PC_COLLISION | QUICC_MBX_PC_Rx_ENABLE);
eppc->pio_pcso |= (QUICC_MBX_PC_COLLISION | QUICC_MBX_PC_Rx_ENABLE);
eppc->pio_papar |= (QUICC_MBX_PA_Tx_CLOCK | QUICC_MBX_PA_Rx_CLOCK);
eppc->pio_padir &= ~(QUICC_MBX_PA_Tx_CLOCK | QUICC_MBX_PA_Rx_CLOCK);
// Set up clock routing
eppc->si_sicr &= ~QUICC_MBX_SICR_MASK;
eppc->si_sicr |= QUICC_MBX_SICR_ENET;
eppc->si_sicr &= ~QUICC_MBX_SICR_SCC1_ENABLE;
// Set up DMA mode
eppc->dma_sdcr = 0x0001;
// Initialize shared PRAM
enet_pram->rbase = RxBD;
enet_pram->tbase = TxBD;
// Set Big Endian mode
enet_pram->rfcr = QUICC_SCC_FCR_BE;
enet_pram->tfcr = QUICC_SCC_FCR_BE;
// Size of receive buffers
enet_pram->mrblr = CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
// Initialize CRC calculations
enet_pram->c_pres = 0xFFFFFFFF;
enet_pram->c_mask = 0xDEBB20E3; // Actual CRC formula
enet_pram->crcec = 0;
enet_pram->alec = 0;
enet_pram->disfc = 0;
// Frame padding
enet_pram->pads = 0x8888;
enet_pram->pads = 0x0000;
// Retries
enet_pram->ret_lim = 15;
enet_pram->ret_cnt = 0;
// Frame sizes
enet_pram->mflr = IEEE_8023_MAX_FRAME;
enet_pram->minflr = IEEE_8023_MIN_FRAME;
enet_pram->maxd1 = CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
enet_pram->maxd2 = CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
// Group address hash
enet_pram->gaddr1 = 0;
enet_pram->gaddr2 = 0;
enet_pram->gaddr3 = 0;
enet_pram->gaddr4 = 0;
// Device physical address
ep = &enaddr[sizeof(enaddr)];
ap = (unsigned char *)&enet_pram->paddr_h;
for (i = 0; i < sizeof(enaddr); i++) {
*ap++ = *--ep;
}
// Persistence counter
enet_pram->p_per = 0;
// Individual address filter
enet_pram->iaddr1 = 0;
enet_pram->iaddr2 = 0;
enet_pram->iaddr3 = 0;
enet_pram->iaddr4 = 0;
// Temp address
enet_pram->taddr_h = 0;
enet_pram->taddr_m = 0;
enet_pram->taddr_l = 0;
// Initialize the CPM (set up buffer pointers, etc).
eppc->cp_cr = QUICC_CPM_SCC1 | QUICC_CPM_CR_INIT_TXRX | QUICC_CPM_CR_BUSY;
while (eppc->cp_cr & QUICC_CPM_CR_BUSY) ;
// Clear any pending interrupt/exceptions
scc->scc_scce = 0xFFFF;
// Enable interrupts
scc->scc_sccm = QUICC_SCCE_INTS;
// Set up SCC1 to run in ethernet mode
scc->scc_gsmr_h = 0;
scc->scc_gsmr_l = QUICC_SCC_GSML_TCI | QUICC_SCC_GSML_TPL_48 |
QUICC_SCC_GSML_TPP_01 | QUICC_SCC_GSML_MODE_ENET;
// Sync delimiters
scc->scc_dsr = 0xD555;
// Protocol specifics (as if GSML wasn't enough)
scc->scc_psmr = QUICC_PMSR_ENET_CRC | QUICC_PMSR_SEARCH_AFTER_22 |
QUICC_PMSR_RCV_SHORT_FRAMES;
// Configure board interface
*MBX_CTL1 = MBX_CTL1_ETEN | MBX_CTL1_TPEN; // Enable ethernet, TP mode
// Enable ethernet interface
eppc->pio_pcpar |= QUICC_MBX_PC_Tx_ENABLE;
eppc->pio_pcdir &= ~QUICC_MBX_PC_Tx_ENABLE;
if (cache_state)
HAL_DCACHE_ENABLE();
// Initialize upper level driver
(sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr);
return true;
}
/* Initialise the resolver. Open a socket and bind it to the address
of the server. return -1 if something goes wrong, otherwise 0 */
int
redboot_dns_res_init(void)
{
#ifdef CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN
char *dns_domain = NULL;
#endif
memset((char *)&server, 0, sizeof(server));
server.sin_len = sizeof(server);
server.sin_family = AF_INET;
server.sin_port = htons(DOMAIN_PORT);
cyg_drv_mutex_init(&dns_mutex);
/* Set the default DNS domain first, so that it can be overwritten
latter */
#ifdef CYGPKG_REDBOOT_NETWORKING_DNS_DEFAULT_DOMAIN
setdomainname(__Xstr(CYGPKG_REDBOOT_NETWORKING_DNS_DEFAULT_DOMAIN),
strlen(__Xstr(CYGPKG_REDBOOT_NETWORKING_DNS_DEFAULT_DOMAIN)));
#endif
/* Set the domain name from flash so that DHCP can later
overwrite it. */
#ifdef CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN
flash_get_config("dns_domain", &dns_domain, CONFIG_STRING);
if(dns_domain != NULL && dns_domain[0] != '\0')
setdomainname(dns_domain, strlen(dns_domain));
#endif
/* If we got a DNS server address from the DHCP/BOOTP, then use
that address */
if ( __bootp_dns_set ) {
memcpy(&server.sin_addr, &__bootp_dns_addr,
sizeof(__bootp_dns_addr) );
#ifdef CYGPKG_REDBOOT_NETWORKING_DNS_DHCP_DOMAIN
if(__bootp_dns_domain_set)
setdomainname(__bootp_dns_domain, strlen(__bootp_dns_domain));
#endif
/* server config is valid */
s = 0;
}
else {
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
{
ip_addr_t dns_ip;
flash_get_config("dns_ip", &dns_ip, CONFIG_IP);
if (dns_ip[0] == 0 && dns_ip[1] == 0 &&
dns_ip[2] == 0 && dns_ip[3] == 0)
return -1;
memcpy(&server.sin_addr, &dns_ip, sizeof(dns_ip));
/* server config is valid */
s = 0;
}
#else
// Use static configuration. If CYGPKG_REDBOOT_NETWORKING_DNS_IP
// is valid s will set set as a side effect.
set_dns(__Xstr(CYGPKG_REDBOOT_NETWORKING_DNS_IP));
#endif
}
return 0;
}
void
net_init(void)
{
cyg_netdevtab_entry_t *t;
// Set defaults as appropriate
#ifdef CYGSEM_REDBOOT_DEFAULT_NO_BOOTP
use_bootp = false;
#else
use_bootp = true;
#endif
#ifdef CYGDBG_REDBOOT_NET_DEBUG
net_debug = true;
#else
net_debug = false;
#endif
gdb_port = CYGNUM_REDBOOT_NETWORKING_TCP_PORT;
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
// Fetch values from saved config data, if available
flash_get_config("net_debug", &net_debug, CONFIG_BOOL);
flash_get_config("gdb_port", &gdb_port, CONFIG_INT);
flash_get_config("bootp", &use_bootp, CONFIG_BOOL);
use_bootp = false;
if (!use_bootp)
{
flash_get_IP("bootp_my_ip", &__local_ip_addr);
#ifdef CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY
flash_get_IP("bootp_my_ip_mask", &__local_ip_mask);
flash_get_IP("bootp_my_gateway_ip", &__local_ip_gate);
#endif
flash_get_config("bootp_server_ip", &my_bootp_info.bp_siaddr,
CONFIG_IP);
}
#endif
# ifdef CYGDBG_IO_ETH_DRIVERS_DEBUG
// Don't override if the user has deliberately set something more
// verbose.
if (0 == cyg_io_eth_net_debug)
cyg_io_eth_net_debug = net_debug;
# endif
have_net = false;
// Make sure the recv buffers are set up
eth_drv_buffers_init();
__pktbuf_init();
// Initialize all network devices
for (t = &__NETDEVTAB__[0]; t != &__NETDEVTAB_END__; t++) {
if (t->init(t)) {
t->status = CYG_NETDEVTAB_STATUS_AVAIL;
} else {
// What to do if device init fails?
t->status = 0; // Device not [currently] available
}
}
if (!__local_enet_sc) {
diag_printf("No network interfaces found\n");
return;
}
// Initialize the network [if present]
if (use_bootp) {
if (__bootp_find_local_ip(&my_bootp_info) == 0) {
have_net = true;
} else {
// Is it an unset address, or has it been set to a static addr
if (__local_ip_addr[0] == 0 && __local_ip_addr[1] == 0 &&
__local_ip_addr[2] == 0 && __local_ip_addr[3] == 0) {
diag_printf("Ethernet %s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
__local_enet_sc->dev_name,
__local_enet_addr[0],
__local_enet_addr[1],
__local_enet_addr[2],
__local_enet_addr[3],
__local_enet_addr[4],
__local_enet_addr[5]);
diag_printf("Can't get BOOTP info for device!\n");
} else {
diag_printf("Can't get BOOTP info, using default IP address\n");
have_net = true;
}
}
} else {
have_net = true; // Assume values in FLASH were OK
}
if (have_net) {
diag_printf("Ethernet %s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
__local_enet_sc->dev_name,
__local_enet_addr[0],
__local_enet_addr[1],
__local_enet_addr[2],
__local_enet_addr[3],
__local_enet_addr[4],
__local_enet_addr[5]);
#ifdef CYGPKG_REDBOOT_NETWORKING_DNS
redboot_dns_res_init();
#endif
show_addrs();
net_io_init();
}
}
// Initialize the interface - performed at system startup
// This function must set up the interface, including arranging to
// handle interrupts, etc, so that it may be "started" cheaply later.
static bool
fcc_eth_init(struct cyg_netdevtab_entry *dtp)
{
struct eth_drv_sc *sc = (struct eth_drv_sc *)dtp->device_instance;
struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
volatile t_Fcc_Pram *fcc = (volatile t_Fcc_Pram *)0;
volatile t_EnetFcc_Pram *E_fcc;
int i, fcc_chan;
bool esa_ok;
unsigned char *c_ptr;
unsigned char _enaddr[6];
unsigned long rxbase, txbase;
struct fcc_bd *rxbd, *txbd;
// The FCC seems rather picky about these...
static long rxbd_base = 0x3000;
static long txbd_base = 0xB000;
#ifdef CYGPKG_DEVS_ETH_PHY
unsigned short phy_state = 0;
#endif
// Set up pointers to FCC controller
switch (qi->int_vector) {
case CYGNUM_HAL_INTERRUPT_FCC1:
qi->fcc_reg = &(IMM->fcc_regs[FCC1]);
fcc = (volatile t_Fcc_Pram *)((unsigned long)IMM + FCC1_PRAM_OFFSET);
fcc_chan = FCC1_PAGE_SUBBLOCK;
break;
case CYGNUM_HAL_INTERRUPT_FCC2:
qi->fcc_reg = &(IMM->fcc_regs[FCC2]);
fcc = (volatile t_Fcc_Pram *)((unsigned long)IMM + FCC2_PRAM_OFFSET);
fcc_chan = FCC2_PAGE_SUBBLOCK;
break;
case CYGNUM_HAL_INTERRUPT_FCC3:
qi->fcc_reg = &(IMM->fcc_regs[FCC3]);
fcc = (volatile t_Fcc_Pram *)((unsigned long)IMM + FCC3_PRAM_OFFSET);
fcc_chan = FCC3_PAGE_SUBBLOCK;
break;
default:
os_printf("Can't initialize '%s' - unknown FCC!\n", dtp->name);
return false;
}
// just in case : disable Transmit and Receive
qi->fcc_reg->fcc_gfmr &= ~(FCC_GFMR_EN_Rx | FCC_GFMR_EN_Tx);
// Try to read the ethernet address of the transciever ...
#ifdef CYGPKG_REDBOOT
esa_ok = flash_get_config(qi->esa_key, _enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
qi->esa_key, _enaddr, CONFIG_ESA);
#endif
if (esa_ok) {
memcpy(qi->enaddr, _enaddr, sizeof(qi->enaddr));
} else {
// No 'flash config' data available - use default
os_printf("FCC_ETH - Warning! Using default ESA for '%s'\n", dtp->name);
}
// Initialize Receive Buffer Descriptors
rxbase = rxbd_base;
fcc->riptr = rxbase; // temp work buffer
fcc->mrblr = FCC_PRAM_MRBLR; // Max Rx buffer
fcc->rstate &= FCC_FCR_INIT;
fcc->rstate |= FCC_FCR_MOT_BO;
rxbase += 64;
rxbd_base += sizeof(struct fcc_bd)*qi->rxnum + 64;
rxbd = (struct fcc_bd *)(CYGARC_IMM_BASE + rxbase);
fcc->rbase = (CYG_WORD)rxbd;
c_ptr = qi->rxbuf;
qi->rbase = rxbd;
qi->rxbd = rxbd;
qi->rnext = rxbd;
for (i = 0; i < qi->rxnum; i++, rxbd++) {
rxbd->ctrl = (FCC_BD_Rx_Empty | FCC_BD_Rx_Int);
rxbd->length = 0; // reset
c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
rxbd->buffer = (volatile unsigned char *)c_ptr;
c_ptr += CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE;
}
rxbd--;
rxbd->ctrl |= FCC_BD_Rx_Wrap;
// Initialize Transmit Buffer Descriptors
txbase = txbd_base;
fcc->tiptr = txbase; // in dual port RAM (see 28-11)
fcc->tstate &= FCC_FCR_INIT;
fcc->tstate |= FCC_FCR_MOT_BO;
txbase += 64;
txbd_base += sizeof(struct fcc_bd)*qi->txnum + 64;
txbd = (struct fcc_bd *)(CYGARC_IMM_BASE + txbase);
fcc->tbase = (CYG_WORD)txbd;
c_ptr = qi->txbuf;
qi->tbase = txbd;
qi->txbd = txbd;
qi->tnext = txbd;
for (i = 0; i < qi->txnum; i++, txbd++) {
txbd->ctrl = (FCC_BD_Tx_Pad | FCC_BD_Tx_Int);
txbd->length = 0; // reset : Write before send
c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
txbd->buffer = (volatile unsigned char *)c_ptr;
c_ptr += CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE;
}
txbd--;
txbd->ctrl |= FCC_BD_Tx_Wrap;
// Ethernet Specific FCC Parameter RAM Initialization
E_fcc = &(fcc->SpecificProtocol.e);
E_fcc->c_mask = FCC_PRAM_C_MASK; // (see 30-9)
E_fcc->c_pres = FCC_PRAM_C_PRES;
E_fcc->crcec = 0;
E_fcc->alec = 0;
E_fcc->disfc = 0;
E_fcc->ret_lim = FCC_PRAM_RETLIM;
E_fcc->p_per = FCC_PRAM_PER_LO;
E_fcc->gaddr_h = 0;
E_fcc->gaddr_l = 0;
E_fcc->tfcstat = 0;
E_fcc->mflr = FCC_MAX_FLR;
E_fcc->paddr1_h = ((short)qi->enaddr[5] << 8) | qi->enaddr[4];
E_fcc->paddr1_m = ((short)qi->enaddr[3] << 8) | qi->enaddr[2];
E_fcc->paddr1_l = ((short)qi->enaddr[1] << 8) | qi->enaddr[0];
E_fcc->iaddr_h = 0;
E_fcc->iaddr_l = 0;
E_fcc->minflr = FCC_MIN_FLR;
E_fcc->taddr_h = 0;
E_fcc->taddr_m = 0;
E_fcc->taddr_l = 0;
E_fcc->pad_ptr = fcc->tiptr; // No special padding char ...
E_fcc->cf_type = 0;
E_fcc->maxd1 = FCC_PRAM_MAXD;
E_fcc->maxd2 = FCC_PRAM_MAXD;
// FCC register initialization
qi->fcc_reg->fcc_gfmr = FCC_GFMR_INIT;
qi->fcc_reg->fcc_psmr = FCC_PSMR_INIT;
qi->fcc_reg->fcc_dsr = FCC_DSR_INIT;
#ifdef CYGPKG_NET
// clear the events of FCCX
qi->fcc_reg->fcc_fcce = 0xFFFF;
qi->fcc_reg->fcc_fccm = FCC_EV_TXE | FCC_EV_TXB | FCC_EV_RXF;
// Set up to handle interrupts
cyg_drv_interrupt_create(qi->int_vector,
0, // Highest //CYGARC_SIU_PRIORITY_HIGH,
(cyg_addrword_t)sc, // Data passed to ISR
(cyg_ISR_t *)fcc_eth_isr,
(cyg_DSR_t *)eth_drv_dsr,
&qi->fcc_eth_interrupt_handle,
&qi->fcc_eth_interrupt);
cyg_drv_interrupt_attach(qi->fcc_eth_interrupt_handle);
cyg_drv_interrupt_acknowledge(qi->int_vector);
cyg_drv_interrupt_unmask(qi->int_vector);
#else
// Mask the interrupts
qi->fcc_reg->fcc_fccm = 0;
#endif
// Issue Init RX & TX Parameters Command for FCCx
while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
IMM->cpm_cpcr = CPCR_INIT_TX_RX_PARAMS |
fcc_chan |
CPCR_MCN_FCC |
CPCR_FLG; /* ISSUE COMMAND */
while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
// Operating mode
if (!_eth_phy_init(qi->phy)) {
return false;
}
#ifdef CYGSEM_DEVS_ETH_POWERPC_FCC_RESET_PHY
_eth_phy_reset(qi->phy);
#endif
phy_state = _eth_phy_state(qi->phy);
os_printf("FCC %s: ", sc->dev_name);
if ((phy_state & ETH_PHY_STAT_LINK) != 0) {
if ((phy_state & ETH_PHY_STAT_100MB) != 0) {
// Link can handle 100Mb
os_printf("100Mb");
if ((phy_state & ETH_PHY_STAT_FDX) != 0) {
os_printf("/Full Duplex");
}
} else {
// Assume 10Mb, half duplex
os_printf("10Mb");
}
} else {
os_printf("/***NO LINK***\n");
#ifdef CYGPKG_REDBOOT
return false;
#endif
}
os_printf("\n");
// Initialize upper level driver for ecos
(sc->funs->eth_drv->init)(sc, (unsigned char *)&qi->enaddr);
return true;
}
// Initialize the interface - performed at system startup
// This function must set up the interface, including arranging to
// handle interrupts, etc, so that it may be "started" cheaply later.
static bool
fec_eth_init(struct cyg_netdevtab_entry *tab)
{
struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE;
volatile t_Fcc_Pram *fcc = (volatile t_Fcc_Pram *) (QUICC2_VADS_IMM_BASE + FEC_PRAM_OFFSET);
volatile t_EnetFcc_Pram *E_fcc = &(fcc->SpecificProtocol.e);
#if defined(CYGPKG_HAL_POWERPC_VADS) || defined(CYGPKG_HAL_POWERPC_TS6)
volatile t_BCSR *CSR = (t_BCSR *) 0x04500000;
#endif
int i;
bool esa_ok;
bool fec_100;
unsigned char *c_ptr;
UINT16 link_speed;
// Link the memory to the driver control memory
qi->fcc_reg = & (IMM->fcc_regs[FCC2]);
// just in case : disable Transmit and Receive
qi->fcc_reg->fcc_gfmr &= ~(FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx);
// Via BCSR, (re)start LXT970
#if defined(CYGPKG_HAL_POWERPC_VADS) || defined(CYGPKG_HAL_POWERPC_TS6)
EnableResetPHY(CSR);
#endif
// Try to read the ethernet address of the transciever ...
#ifdef CYGPKG_REDBOOT
esa_ok = flash_get_config("fec_100", &fec_100, CONFIG_BOOL);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"fec_100", &fec_100, CONFIG_BOOL);
#endif
link_speed = NOTLINKED;
if(esa_ok && fec_100){
// Via MII Management pins, tell LXT970 to initialize
os_printf("Attempting to acquire 100 Mbps half_duplex link ...");
InitEthernetPHY((VUINT32 *) &(IMM->io_regs[PORT_C].pdir),
(VUINT32 *) &(IMM->io_regs[PORT_C].pdat),
HUNDRED_HD);
link_speed = LinkTestPHY();
os_printf("\n");
if(link_speed == NOTLINKED){
os_printf("Failed to get 100 Mbps half_duplex link.\n");
}
}
if(link_speed == NOTLINKED){
os_printf("Attempting to acquire 10 Mbps half_duplex link ...");
InitEthernetPHY((VUINT32 *) &(IMM->io_regs[PORT_C].pdir),
(VUINT32 *) &(IMM->io_regs[PORT_C].pdat),
TEN_HD);
link_speed = LinkTestPHY();
os_printf("\n");
if(link_speed == NOTLINKED){
link_speed = LinkTestPHY();
os_printf("Failed to get 10 Mbps half_duplex link.\n");
}
}
switch ( link_speed ) {
case HUNDRED_FD:
os_printf("100 MB full-duplex ethernet link \n");
break;
case HUNDRED_HD:
os_printf("100 MB half-duplex ethernet link \n");
break;
case TEN_FD:
os_printf("10 MB full-duplex ethernet link \n");
break;
case TEN_HD:
os_printf("10 MB half-duplex ethernet link \n");
break;
default:
os_printf("NO ethernet link \n");
}
// Connect PORTC pins: (C19) to clk13, (C18) to clk 14
IMM->io_regs[PORT_C].ppar |= 0x00003000;
IMM->io_regs[PORT_C].podr &= ~(0x00003000);
IMM->io_regs[PORT_C].psor &= ~(0x00003000);
IMM->io_regs[PORT_C].pdir &= ~(0x00003000);
// Connect clk13 to RxClk and clk14 to TxClk on FCC2
IMM->cpm_mux_cmxfcr &= 0x7f007f00; // clear fcc2 clocks
IMM->cpm_mux_cmxfcr |= 0x00250000; // set fcc2 clocks (see 15-14)
IMM->cpm_mux_cmxuar = 0x0000; // Utopia address reg, just clear
// Initialize parallel port registers to connect FCC2 to MII
IMM->io_regs[PORT_B].podr &= 0xffffc000; // clear bits 18-31
IMM->io_regs[PORT_B].psor &= 0xffffc000;
IMM->io_regs[PORT_B].pdir &= 0xffffc000;
IMM->io_regs[PORT_B].psor |= 0x00000004;
IMM->io_regs[PORT_B].pdir |= 0x000003c5;
IMM->io_regs[PORT_B].ppar |= 0x00003fff;
// Initialize Receive Buffer Descriptors
qi->rbase = fec_eth_rxring;
qi->rxbd = fec_eth_rxring;
qi->rnext = fec_eth_rxring;
c_ptr = fec_eth_rxbufs;
for(i=0; i<CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM; i++) {
fec_eth_rxring[i].ctrl = (FEC_BD_Rx_Empty | FEC_BD_Rx_Int);
fec_eth_rxring[i].length = 0; // reset
c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
fec_eth_rxring[i].buffer = (volatile unsigned char *)c_ptr;
c_ptr += CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE;
}
fec_eth_rxring[CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM-1].ctrl |= FEC_BD_Rx_Wrap;
// Initialize Transmit Buffer Descriptors
qi->tbase = fec_eth_txring;
qi->txbd = fec_eth_txring;
qi->tnext = fec_eth_txring;
c_ptr = fec_eth_txbufs;
for(i=0; i<CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM; i++) {
fec_eth_txring[i].ctrl = (FEC_BD_Tx_Pad | FEC_BD_Tx_Int);
fec_eth_txring[i].length = 0; // reset : Write before send
c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
fec_eth_txring[i].buffer = (volatile unsigned char *)c_ptr;
c_ptr += CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE;
}
fec_eth_txring[CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM-1].ctrl |= FEC_BD_Tx_Wrap;
// Common FCC Parameter RAM initialization
fcc->riptr = FEC_PRAM_RIPTR; // in dual port RAM (see 28-11)
fcc->tiptr = FEC_PRAM_TIPTR; // in dual port RAM (see 28-11)
fcc->mrblr = FEC_PRAM_MRBLR; // ?? FROM 8101 code ...
fcc->rstate &= FEC_FCR_INIT;
fcc->rstate |= FEC_FCR_MOT_BO;
fcc->rbase = (long) fec_eth_rxring;
fcc->tstate &= FEC_FCR_INIT;
fcc->tstate |= FEC_FCR_MOT_BO;
fcc->tbase = (long) fec_eth_txring;
// Ethernet Specific FCC Parameter RAM Initialization
E_fcc->c_mask = FEC_PRAM_C_MASK; // (see 30-9)
E_fcc->c_pres = FEC_PRAM_C_PRES;
E_fcc->crcec = 0;
E_fcc->alec = 0;
E_fcc->disfc = 0;
E_fcc->ret_lim = FEC_PRAM_RETLIM;
E_fcc->p_per = FEC_PRAM_PER_LO;
E_fcc->gaddr_h = 0;
E_fcc->gaddr_l = 0;
E_fcc->tfcstat = 0;
E_fcc->mflr = FEC_MAX_FLR;
// Try to read the ethernet address of the transciever ...
#ifdef CYGPKG_REDBOOT
esa_ok = flash_get_config("fec_esa", enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"fec_esa", enaddr, CONFIG_ESA);
#endif
if (!esa_ok) {
// If can't use the default ...
os_printf("FEC_ETH - Warning! ESA unknown\n");
memcpy(enaddr, _default_enaddr, sizeof(enaddr));
}
E_fcc->paddr1_h = ((short)enaddr[5] << 8) | enaddr[4]; // enaddr[2];
E_fcc->paddr1_m = ((short)enaddr[3] << 8) | enaddr[2]; // enaddr[1];
E_fcc->paddr1_l = ((short)enaddr[1] << 8) | enaddr[0]; // enaddr[0];
E_fcc->iaddr_h = 0;
E_fcc->iaddr_l = 0;
E_fcc->minflr = FEC_MIN_FLR;
E_fcc->taddr_h = 0;
E_fcc->taddr_m = 0;
E_fcc->taddr_l = 0;
E_fcc->pad_ptr = FEC_PRAM_TIPTR; // No special padding char ...
E_fcc->cf_type = 0;
E_fcc->maxd1 = FEC_PRAM_MAXD;
E_fcc->maxd2 = FEC_PRAM_MAXD;
// FCC register initialization
IMM->fcc_regs[FCC2].fcc_gfmr = FEC_GFMR_INIT;
IMM->fcc_regs[FCC2].fcc_psmr = FEC_PSMR_INIT;
IMM->fcc_regs[FCC2].fcc_dsr = FEC_DSR_INIT;
#ifdef CYGPKG_NET
// clear the events of FCC2
IMM->fcc_regs[FCC2].fcc_fcce = 0xFFFF0000;
IMM->fcc_regs[FCC2].fcc_fccm = FEC_EV_TXE | FEC_EV_TXB | FEC_EV_RXF;
// Set up to handle interrupts
cyg_drv_interrupt_create(FEC_ETH_INT,
0, // Highest //CYGARC_SIU_PRIORITY_HIGH,
(cyg_addrword_t)sc, // Data passed to ISR
(cyg_ISR_t *)fec_eth_isr,
(cyg_DSR_t *)eth_drv_dsr,
&fec_eth_interrupt_handle,
&fec_eth_interrupt);
cyg_drv_interrupt_attach(fec_eth_interrupt_handle);
cyg_drv_interrupt_acknowledge(FEC_ETH_INT);
cyg_drv_interrupt_unmask(FEC_ETH_INT);
#else
// Mask the interrupts
IMM->fcc_regs[FCC2].fcc_fccm = 0;
#endif
// Issue Init RX & TX Parameters Command for FCC2
while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
IMM->cpm_cpcr = CPCR_INIT_TX_RX_PARAMS |
CPCR_FCC2_CH |
CPCR_MCN_FEC |
CPCR_FLG; /* ISSUE COMMAND */
while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
// Initialize upper level driver for ecos
(sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr);
return true;
}
void
net_init(void)
{
cyg_netdevtab_entry_t *t;
unsigned index;
struct eth_drv_sc *primary_net = (struct eth_drv_sc *)0;
#if defined(CYGHWR_NET_DRIVERS) && (CYGHWR_NET_DRIVERS > 1)
char *default_devname;
int default_index;
#endif
#ifdef CYGDAT_REDBOOT_DEFAULT_BOOTP_SERVER_IP_ADDR
char ip_addr[16];
#endif
// Set defaults as appropriate
#ifdef CYGSEM_REDBOOT_DEFAULT_NO_BOOTP
use_bootp = false;
#else
use_bootp = true;
#endif
#ifdef CYGDBG_REDBOOT_NET_DEBUG
net_debug = true;
#else
net_debug = false;
#endif
gdb_port = CYGNUM_REDBOOT_NETWORKING_TCP_PORT;
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
// Fetch values from saved config data, if available
#if defined(CYGHWR_NET_DRIVERS) && (CYGHWR_NET_DRIVERS > 1)
flash_get_config("net_device", &default_devname, CONFIG_NETPORT);
#endif
flash_get_config("net_debug", &net_debug, CONFIG_BOOL);
flash_get_config("gdb_port", &gdb_port, CONFIG_INT);
flash_get_config("bootp", &use_bootp, CONFIG_BOOL);
if (!use_bootp) {
flash_get_IP("bootp_my_ip", &__local_ip_addr);
#ifdef CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY
flash_get_IP("bootp_my_ip_mask", &__local_ip_mask);
flash_get_IP("bootp_my_gateway_ip", &__local_ip_gate);
#endif
}
#endif
# ifdef CYGDBG_IO_ETH_DRIVERS_DEBUG
// Don't override if the user has deliberately set something more
// verbose.
if (0 == cyg_io_eth_net_debug)
cyg_io_eth_net_debug = net_debug;
# endif
have_net = false;
// Make sure the recv buffers are set up
eth_drv_buffers_init();
__pktbuf_init();
// Initialize network device(s).
#if defined(CYGHWR_NET_DRIVERS) && (CYGHWR_NET_DRIVERS > 1)
default_index = net_devindex(default_devname);
if (default_index < 0)
default_index = 0;
#ifdef CYGSEM_REDBOOT_NETWORK_INIT_ONE_DEVICE
if ((t = net_devtab_entry(default_index)) != NULL && t->init(t)) {
t->status = CYG_NETDEVTAB_STATUS_AVAIL;
primary_net = __local_enet_sc;
} else
#endif
#endif
for (index = 0; (t = net_devtab_entry(index)) != NULL; index++) {
#if defined(CYGSEM_REDBOOT_NETWORK_INIT_ONE_DEVICE)
if (index == default_index)
continue;
#endif
if (t->init(t)) {
t->status = CYG_NETDEVTAB_STATUS_AVAIL;
if (primary_net == (struct eth_drv_sc *)0) {
primary_net = __local_enet_sc;
}
#if defined(CYGHWR_NET_DRIVERS) && (CYGHWR_NET_DRIVERS > 1)
#if !defined(CYGSEM_REDBOOT_NETWORK_INIT_ONE_DEVICE)
if (index == default_index) {
primary_net = __local_enet_sc;
}
#else
break;
#endif
#endif
}
}
__local_enet_sc = primary_net;
if (!__local_enet_sc) {
diag_printf("No network interfaces found\n");
return;
}
// Initialize the network [if present]
if (use_bootp) {
if (__bootp_find_local_ip(&my_bootp_info) == 0) {
have_net = true;
} else {
// Is it an unset address, or has it been set to a static addr
if (__local_ip_addr[0] == 0 && __local_ip_addr[1] == 0 &&
__local_ip_addr[2] == 0 && __local_ip_addr[3] == 0) {
show_eth_info();
diag_printf("Can't get BOOTP info for device!\n");
} else {
diag_printf("Can't get BOOTP info, using default IP address\n");
have_net = true;
}
}
} else {
enet_addr_t enet_addr;
have_net = true; // Assume values in FLASH were OK
// Tell the world that we are using this fixed IP address
if (__arp_request((ip_addr_t *)__local_ip_addr, &enet_addr, 1) >= 0) {
diag_printf("Warning: IP address %s in use\n", inet_ntoa((in_addr_t *)&__local_ip_addr));
}
}
if (have_net) {
show_eth_info();
#ifdef CYGDAT_REDBOOT_DEFAULT_BOOTP_SERVER_IP_ADDR
diag_sprintf(ip_addr, "%d.%d.%d.%d",
CYGDAT_REDBOOT_DEFAULT_BOOTP_SERVER_IP_ADDR);
inet_aton(ip_addr, &my_bootp_info.bp_siaddr);
#endif
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
flash_get_IP("bootp_server_ip", (ip_addr_t *)&my_bootp_info.bp_siaddr);
#endif
#ifdef CYGPKG_REDBOOT_NETWORKING_DNS
redboot_dns_res_init();
#endif
show_addrs();
net_io_init();
}
}
//
// Initialize the interface - performed at system startup
// This function must set up the interface, including arranging to
// handle interrupts, etc, so that it may be "started" cheaply later.
//
static bool
fec_eth_init(struct cyg_netdevtab_entry *tab)
{
struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
volatile EPPC *eppc = (volatile EPPC *)eppc_base();
volatile struct fec *fec = (volatile struct fec *)((unsigned char *)eppc + FEC_OFFSET);
unsigned short phy_state = 0;
int cache_state;
int i;
unsigned long proc_rev;
bool esa_ok, phy_ok;
int phy_timeout = 5*1000; // Wait 5 seconds max for link to clear
// Ensure consistent state between cache and what the FEC sees
HAL_DCACHE_IS_ENABLED(cache_state);
HAL_DCACHE_SYNC();
HAL_DCACHE_DISABLE();
qi->fec = fec;
fec_eth_stop(sc); // Make sure it's not running yet
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
#ifdef _FEC_USE_INTS
// Set up to handle interrupts
cyg_drv_interrupt_create(FEC_ETH_INT,
CYGARC_SIU_PRIORITY_HIGH,
(cyg_addrword_t)sc, // Data item passed to interrupt handler
(cyg_ISR_t *)fec_eth_isr,
(cyg_DSR_t *)eth_drv_dsr,
&fec_eth_interrupt_handle,
&fec_eth_interrupt);
cyg_drv_interrupt_attach(fec_eth_interrupt_handle);
cyg_drv_interrupt_acknowledge(FEC_ETH_INT);
cyg_drv_interrupt_unmask(FEC_ETH_INT);
#else // _FEC_USE_INTS
// Hack - use a thread to simulate interrupts
cyg_thread_create(1, // Priority
fec_fake_int, // entry
(cyg_addrword_t)sc, // entry parameter
"CS8900 int", // Name
&fec_fake_int_stack[0], // Stack
STACK_SIZE, // Size
&fec_fake_int_thread_handle, // Handle
&fec_fake_int_thread_data // Thread data structure
);
cyg_thread_resume(fec_fake_int_thread_handle); // Start it
#endif
#endif
// Set up parallel port for connection to ethernet tranceiver
eppc->pio_pdpar = 0x1FFF;
CYGARC_MFSPR( CYGARC_REG_PVR, proc_rev );
#define PROC_REVB 0x0020
if ((proc_rev & 0x0000FFFF) == PROC_REVB) {
eppc->pio_pddir = 0x1C58;
} else {
eppc->pio_pddir = 0x1FFF;
}
// Get physical device address
#ifdef CYGPKG_REDBOOT
esa_ok = flash_get_config("fec_esa", enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"fec_esa", enaddr, CONFIG_ESA);
#endif
if (!esa_ok) {
// Can't figure out ESA
os_printf("FEC_ETH - Warning! ESA unknown\n");
memcpy(&enaddr, &_default_enaddr, sizeof(enaddr));
}
// Configure the device
if (!fec_eth_reset(sc, enaddr, 0)) {
return false;
}
// Reset PHY (transceiver)
eppc->pip_pbdat &= ~0x00004000; // Reset PHY chip
CYGACC_CALL_IF_DELAY_US(10000); // 10ms
eppc->pip_pbdat |= 0x00004000; // Enable PHY chip
// Enable transceiver (PHY)
phy_ok = 0;
phy_write(PHY_BMCR, 0, PHY_BMCR_RESET);
for (i = 0; i < 10; i++) {
phy_ok = phy_read(PHY_BMCR, 0, &phy_state);
if (!phy_ok) break;
if (!(phy_state & PHY_BMCR_RESET)) break;
}
if (!phy_ok || (phy_state & PHY_BMCR_RESET)) {
os_printf("FEC: Can't get PHY unit to reset: %x\n", phy_state);
return false;
}
fec->iEvent = 0xFFFFFFFF; // Clear all interrupts
phy_write(PHY_BMCR, 0, PHY_BMCR_AUTO_NEG|PHY_BMCR_RESTART);
while (phy_timeout-- >= 0) {
int ev = fec->iEvent;
unsigned short state;
fec->iEvent = ev;
if (ev & iEvent_MII) {
phy_ok = phy_read(PHY_BMSR, 0, &state);
if (phy_ok && (state & PHY_BMSR_AUTO_NEG)) {
// os_printf("State: %x\n", state);
break;
} else {
CYGACC_CALL_IF_DELAY_US(1000); // 1ms
}
}
}
if (phy_timeout <= 0) {
os_printf("** FEC Warning: PHY auto-negotiation failed\n");
}
// Initialize upper level driver
(sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr);
return true;
}