static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency) { return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency); }
static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency) { return muldiv64(timer_ticks, frequency, get_ticks_per_sec()); }
/* PowerPC Mac99 hardware initialisation */ static void ppc_core99_init(QEMUMachineInitArgs *args) { ram_addr_t ram_size = args->ram_size; const char *cpu_model = args->cpu_model; const char *kernel_filename = args->kernel_filename; const char *kernel_cmdline = args->kernel_cmdline; const char *initrd_filename = args->initrd_filename; const char *boot_device = args->boot_device; PowerPCCPU *cpu = NULL; CPUPPCState *env = NULL; char *filename; qemu_irq *pic, **openpic_irqs; MemoryRegion *unin_memory = g_new(MemoryRegion, 1); int linux_boot, i; MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); hwaddr kernel_base, initrd_base, cmdline_base = 0; long kernel_size, initrd_size; PCIBus *pci_bus; MacIONVRAMState *nvr; int bios_size; MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem, *escc_mem; MemoryRegion *escc_bar = g_new(MemoryRegion, 1); MemoryRegion *ide_mem[3]; int ppc_boot_device; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; void *fw_cfg; void *dbdma; int machine_arch; linux_boot = (kernel_filename != NULL); /* init CPUs */ if (cpu_model == NULL) #ifdef TARGET_PPC64 cpu_model = "970fx"; #else cpu_model = "G4"; #endif for (i = 0; i < smp_cpus; i++) { cpu = cpu_ppc_init(cpu_model); if (cpu == NULL) { fprintf(stderr, "Unable to find PowerPC CPU definition\n"); exit(1); } env = &cpu->env; /* Set time-base frequency to 100 Mhz */ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); qemu_register_reset(ppc_core99_reset, cpu); } /* allocate RAM */ memory_region_init_ram(ram, "ppc_core99.ram", ram_size); vmstate_register_ram_global(ram); memory_region_add_subregion(get_system_memory(), 0, ram); /* allocate and load BIOS */ memory_region_init_ram(bios, "ppc_core99.bios", BIOS_SIZE); vmstate_register_ram_global(bios); if (bios_name == NULL) bios_name = PROM_FILENAME; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); memory_region_set_readonly(bios, true); memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios); /* Load OpenBIOS (ELF) */ if (filename) { bios_size = load_elf(filename, NULL, NULL, NULL, NULL, NULL, 1, ELF_MACHINE, 0); g_free(filename); } else { bios_size = -1; } if (bios_size < 0 || bios_size > BIOS_SIZE) { hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name); exit(1); } if (linux_boot) { uint64_t lowaddr = 0; int bswap_needed; #ifdef BSWAP_NEEDED bswap_needed = 1; #else bswap_needed = 0; #endif kernel_base = KERNEL_LOAD_ADDR; kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); if (kernel_size < 0) kernel_size = load_aout(kernel_filename, kernel_base, ram_size - kernel_base, bswap_needed, TARGET_PAGE_SIZE); if (kernel_size < 0) kernel_size = load_image_targphys(kernel_filename, kernel_base, ram_size - kernel_base); if (kernel_size < 0) { hw_error("qemu: could not load kernel '%s'\n", kernel_filename); exit(1); } /* load initrd */ if (initrd_filename) { initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); initrd_size = load_image_targphys(initrd_filename, initrd_base, ram_size - initrd_base); if (initrd_size < 0) { hw_error("qemu: could not load initial ram disk '%s'\n", initrd_filename); exit(1); } cmdline_base = round_page(initrd_base + initrd_size); } else { initrd_base = 0; initrd_size = 0; cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); } ppc_boot_device = 'm'; } else { kernel_base = 0; kernel_size = 0; initrd_base = 0; initrd_size = 0; ppc_boot_device = '\0'; /* We consider that NewWorld PowerMac never have any floppy drive * For now, OHW cannot boot from the network. */ for (i = 0; boot_device[i] != '\0'; i++) { if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { ppc_boot_device = boot_device[i]; break; } } if (ppc_boot_device == '\0') { fprintf(stderr, "No valid boot device for Mac99 machine\n"); exit(1); } } /* Register 8 MB of ISA IO space */ isa_mmio_init(0xf2000000, 0x00800000); /* UniN init */ memory_region_init_io(unin_memory, &unin_ops, NULL, "unin", 0x1000); memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory); openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); openpic_irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); for (i = 0; i < smp_cpus; i++) { /* Mac99 IRQ connection between OpenPIC outputs pins * and PowerPC input pins */ switch (PPC_INPUT(env)) { case PPC_FLAGS_INPUT_6xx: openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); openpic_irqs[i][OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_MCK] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; /* Not connected ? */ openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; /* Check this */ openpic_irqs[i][OPENPIC_OUTPUT_RESET] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; break; #if defined(TARGET_PPC64) case PPC_FLAGS_INPUT_970: openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); openpic_irqs[i][OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; openpic_irqs[i][OPENPIC_OUTPUT_MCK] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; /* Not connected ? */ openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; /* Check this */ openpic_irqs[i][OPENPIC_OUTPUT_RESET] = ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; break; #endif /* defined(TARGET_PPC64) */ default: hw_error("Bus model not supported on mac99 machine\n"); exit(1); } } pic = openpic_init(&pic_mem, smp_cpus, openpic_irqs, NULL); if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { /* 970 gets a U3 bus */ pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io()); machine_arch = ARCH_MAC99_U3; } else { pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io()); machine_arch = ARCH_MAC99; } /* init basic PC hardware */ pci_vga_init(pci_bus); escc_mem = escc_init(0, pic[0x25], pic[0x24], serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); memory_region_init_alias(escc_bar, "escc-bar", escc_mem, 0, memory_region_size(escc_mem)); for(i = 0; i < nb_nics; i++) pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); ide_drive_get(hd, MAX_IDE_BUS); dbdma = DBDMA_init(&dbdma_mem); /* We only emulate 2 out of 3 IDE controllers for now */ ide_mem[0] = NULL; ide_mem[1] = pmac_ide_init(hd, pic[0x0d], dbdma, 0x16, pic[0x02]); ide_mem[2] = pmac_ide_init(&hd[MAX_IDE_DEVS], pic[0x0e], dbdma, 0x1a, pic[0x02]); /* cuda also initialize ADB */ if (machine_arch == ARCH_MAC99_U3) { usb_enabled = 1; } cuda_init(&cuda_mem, pic[0x19]); adb_kbd_init(&adb_bus); adb_mouse_init(&adb_bus); macio_init(pci_bus, PCI_DEVICE_ID_APPLE_UNI_N_KEYL, 0, pic_mem, dbdma_mem, cuda_mem, NULL, 3, ide_mem, escc_bar); if (usb_enabled) { pci_create_simple(pci_bus, -1, "pci-ohci"); } /* U3 needs to use USB for input because Linux doesn't support via-cuda on PPC64 */ if (machine_arch == ARCH_MAC99_U3) { usbdevice_create("keyboard"); usbdevice_create("mouse"); } if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) graphic_depth = 15; /* The NewWorld NVRAM is not located in the MacIO device */ nvr = macio_nvram_init(0x2000, 1); pmac_format_nvram_partition(nvr, 0x2000); macio_nvram_setup_bar(nvr, get_system_memory(), 0xFFF04000); /* No PCI init: the BIOS will do it */ fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); if (kernel_cmdline) { fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); } else { fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); } fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); if (kvm_enabled()) { #ifdef CONFIG_KVM uint8_t *hypercall; fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); hypercall = g_malloc(16); kvmppc_get_hypercall(env, hypercall, 16); fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); #endif } else { fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec()); } qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); }
static void icount_adjust_vm(void *opaque) { qemu_mod_timer(icount_vm_timer, qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 10); icount_adjust(); }
static uint32_t pl031_get_count(pl031_state *s) { int64_t now = qemu_get_clock_ns(rtc_clock); return s->tick_offset + now / get_ticks_per_sec(); }
static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset) { arm_sysctl_state *s = (arm_sysctl_state *)opaque; switch (offset) { case 0x00: /* ID */ return s->sys_id; case 0x04: /* SW */ /* General purpose hardware switches. We don't have a useful way of exposing these to the user. */ return 0; case 0x08: /* LED */ return s->leds; case 0x20: /* LOCK */ return s->lockval; case 0x0c: /* OSC0 */ case 0x10: /* OSC1 */ case 0x14: /* OSC2 */ case 0x18: /* OSC3 */ case 0x1c: /* OSC4 */ case 0x24: /* 100HZ */ /* ??? Implement these. */ return 0; case 0x28: /* CFGDATA1 */ return s->cfgdata1; case 0x2c: /* CFGDATA2 */ return s->cfgdata2; case 0x30: /* FLAGS */ return s->flags; case 0x38: /* NVFLAGS */ return s->nvflags; case 0x40: /* RESETCTL */ if (board_id(s) == BOARD_ID_VEXPRESS) { /* reserved: RAZ/WI */ return 0; } return s->resetlevel; case 0x44: /* PCICTL */ return 1; case 0x48: /* MCI */ return s->sys_mci; case 0x4c: /* FLASH */ return 0; case 0x50: /* CLCD */ return 0x1000; case 0x54: /* CLCDSER */ return 0; case 0x58: /* BOOTCS */ return 0; case 0x5c: /* 24MHz */ return muldiv64(qemu_get_clock_ns(vm_clock), 24000000, get_ticks_per_sec()); case 0x60: /* MISC */ return 0; case 0x84: /* PROCID0 */ return s->proc_id; case 0x88: /* PROCID1 */ return 0xff000000; case 0x64: /* DMAPSR0 */ case 0x68: /* DMAPSR1 */ case 0x6c: /* DMAPSR2 */ case 0x70: /* IOSEL */ case 0x74: /* PLDCTL */ case 0x80: /* BUSID */ case 0x8c: /* OSCRESET0 */ case 0x90: /* OSCRESET1 */ case 0x94: /* OSCRESET2 */ case 0x98: /* OSCRESET3 */ case 0x9c: /* OSCRESET4 */ case 0xc0: /* SYS_TEST_OSC0 */ case 0xc4: /* SYS_TEST_OSC1 */ case 0xc8: /* SYS_TEST_OSC2 */ case 0xcc: /* SYS_TEST_OSC3 */ case 0xd0: /* SYS_TEST_OSC4 */ return 0; case 0xa0: /* SYS_CFGDATA */ if (board_id(s) != BOARD_ID_VEXPRESS) { goto bad_reg; } return s->sys_cfgdata; case 0xa4: /* SYS_CFGCTRL */ if (board_id(s) != BOARD_ID_VEXPRESS) { goto bad_reg; } return s->sys_cfgctrl; case 0xa8: /* SYS_CFGSTAT */ if (board_id(s) != BOARD_ID_VEXPRESS) { goto bad_reg; } return s->sys_cfgstat; default: bad_reg: printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset); return 0; } }
static int64_t get_clock(void) { LARGE_INTEGER ti; QueryPerformanceCounter(&ti); return muldiv64(ti.QuadPart, get_ticks_per_sec(), clock_freq); }
/* Try to interpret a whole incoming packet */ static int baum_eat_packet(BaumDriverState *baum, const uint8_t *buf, int len) { const uint8_t *cur = buf; uint8_t req = 0; if (!len--) return 0; if (*cur++ != ESC) { while (*cur != ESC) { if (!len--) return 0; cur++; } DPRINTF("Dropped %td bytes!\n", cur - buf); } #define EAT(c) do {\ if (!len--) \ return 0; \ if ((c = *cur++) == ESC) { \ if (!len--) \ return 0; \ if (*cur++ != ESC) { \ DPRINTF("Broken packet %#2x, tossing\n", req); \ if (timer_pending(baum->cellCount_timer)) { \ timer_del(baum->cellCount_timer); \ baum_cellCount_timer_cb(baum); \ } \ return (cur - 2 - buf); \ } \ } \ } while (0) EAT(req); switch (req) { case BAUM_REQ_DisplayData: { uint8_t cells[baum->x * baum->y], c; uint8_t text[baum->x * baum->y]; uint8_t zero[baum->x * baum->y]; int cursor = BRLAPI_CURSOR_OFF; int i; /* Allow 100ms to complete the DisplayData packet */ timer_mod(baum->cellCount_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + get_ticks_per_sec() / 10); for (i = 0; i < baum->x * baum->y ; i++) { EAT(c); cells[i] = c; if ((c & (BRLAPI_DOT7|BRLAPI_DOT8)) == (BRLAPI_DOT7|BRLAPI_DOT8)) { cursor = i + 1; c &= ~(BRLAPI_DOT7|BRLAPI_DOT8); } if (!(c = nabcc_translation[c])) c = '?'; text[i] = c; } timer_del(baum->cellCount_timer); memset(zero, 0, sizeof(zero)); brlapi_writeArguments_t wa = { .displayNumber = BRLAPI_DISPLAY_DEFAULT, .regionBegin = 1, .regionSize = baum->x * baum->y, .text = (char *)text, .textSize = baum->x * baum->y, .andMask = zero, .orMask = cells, .cursor = cursor, .charset = (char *)"ISO-8859-1", }; if (brlapi__write(baum->brlapi, &wa) == -1) brlapi_perror("baum brlapi_write"); break; } case BAUM_REQ_SetMode: { uint8_t mode, setting; DPRINTF("SetMode\n"); EAT(mode); EAT(setting); /* ignore */ break; } case BAUM_REQ_SetProtocol: { uint8_t protocol; DPRINTF("SetProtocol\n"); EAT(protocol); /* ignore */ break; } case BAUM_REQ_GetDeviceIdentity: { uint8_t identity[17] = { BAUM_RSP_DeviceIdentity, 'B','a','u','m',' ','V','a','r','i','o' }; DPRINTF("GetDeviceIdentity\n"); identity[11] = '0' + baum->x / 10; identity[12] = '0' + baum->x % 10; baum_write_packet(baum, identity, sizeof(identity)); break; } case BAUM_REQ_GetVersionNumber: { uint8_t version[] = { BAUM_RSP_VersionNumber, 1 }; /* ? */ DPRINTF("GetVersionNumber\n"); baum_write_packet(baum, version, sizeof(version)); break; } case BAUM_REQ_GetSerialNumber: { uint8_t serial[] = { BAUM_RSP_SerialNumber, '0','0','0','0','0','0','0','0' }; DPRINTF("GetSerialNumber\n"); baum_write_packet(baum, serial, sizeof(serial)); break; } case BAUM_REQ_GetKeys: { DPRINTF("Get%0#2x\n", req); /* ignore */ break; } default: DPRINTF("unrecognized request %0#2x\n", req); do if (!len--) return 0; while (*cur++ != ESC); cur--; break; } return cur - buf; } /* The other end is writing some data. Store it and try to interpret */ static int baum_write(CharDriverState *chr, const uint8_t *buf, int len) { BaumDriverState *baum = chr->opaque; int tocopy, cur, eaten, orig_len = len; if (!len) return 0; if (!baum->brlapi) return len; while (len) { /* Complete our buffer as much as possible */ tocopy = len; if (tocopy > BUF_SIZE - baum->in_buf_used) tocopy = BUF_SIZE - baum->in_buf_used; memcpy(baum->in_buf + baum->in_buf_used, buf, tocopy); baum->in_buf_used += tocopy; buf += tocopy; len -= tocopy; /* Interpret it as much as possible */ cur = 0; while (cur < baum->in_buf_used && (eaten = baum_eat_packet(baum, baum->in_buf + cur, baum->in_buf_used - cur))) cur += eaten; /* Shift the remainder */ if (cur) { memmove(baum->in_buf, baum->in_buf + cur, baum->in_buf_used - cur); baum->in_buf_used -= cur; } /* And continue if any data left */ } return orig_len; }
static void tusb_async_writew(void *opaque, hwaddr addr, uint32_t value) { TUSBState *s = (TUSBState *) opaque; int offset = addr & 0xfff; int epnum; switch (offset) { case TUSB_VLYNQ_CTRL: break; case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): musb_write[2](s->musb, offset & 0x1ff, value); break; case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): musb_write[2](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); break; case TUSB_DEV_CONF: s->dev_config = value; s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE); if (value & TUSB_DEV_CONF_PROD_TEST_MODE) hw_error("%s: Product Test mode not allowed\n", __FUNCTION__); break; case TUSB_PHY_OTG_CTRL_ENABLE: case TUSB_PHY_OTG_CTRL: return; /* TODO */ case TUSB_DEV_OTG_TIMER: s->otg_timer_val = value; if (value & TUSB_DEV_OTG_TIMER_ENABLE) timer_mod(s->otg_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + muldiv64(TUSB_DEV_OTG_TIMER_VAL(value), get_ticks_per_sec(), TUSB_DEVCLOCK)); else timer_del(s->otg_timer); break; case TUSB_PRCM_CONF: s->prcm_config = value; break; case TUSB_PRCM_MNGMT: s->prcm_mngmt = value; break; case TUSB_PRCM_WAKEUP_CLEAR: break; case TUSB_PRCM_WAKEUP_MASK: s->wkup_mask = value; break; case TUSB_PULLUP_1_CTRL: s->pullup[0] = value; break; case TUSB_PULLUP_2_CTRL: s->pullup[1] = value; break; case TUSB_INT_CTRL_CONF: s->control_config = value; tusb_intr_update(s); break; case TUSB_USBIP_INT_SET: s->usbip_intr |= value; tusb_usbip_intr_update(s); break; case TUSB_USBIP_INT_CLEAR: s->usbip_intr &= ~value; tusb_usbip_intr_update(s); musb_core_intr_clear(s->musb, ~value); break; case TUSB_USBIP_INT_MASK: s->usbip_mask = value; tusb_usbip_intr_update(s); break; case TUSB_DMA_INT_SET: s->dma_intr |= value; tusb_dma_intr_update(s); break; case TUSB_DMA_INT_CLEAR: s->dma_intr &= ~value; tusb_dma_intr_update(s); break; case TUSB_DMA_INT_MASK: s->dma_mask = value; tusb_dma_intr_update(s); break; case TUSB_GPIO_INT_SET: s->gpio_intr |= value; tusb_gpio_intr_update(s); break; case TUSB_GPIO_INT_CLEAR: s->gpio_intr &= ~value; tusb_gpio_intr_update(s); break; case TUSB_GPIO_INT_MASK: s->gpio_mask = value; tusb_gpio_intr_update(s); break; case TUSB_INT_SRC_SET: s->intr |= value; tusb_intr_update(s); break; case TUSB_INT_SRC_CLEAR: s->intr &= ~value; tusb_intr_update(s); break; case TUSB_INT_MASK: s->mask = value; tusb_intr_update(s); break; case TUSB_GPIO_CONF: s->gpio_config = value; break; case TUSB_DMA_REQ_CONF: s->dma_config = value; break; case TUSB_EP0_CONF: s->ep0_config = value & 0x1ff; musb_set_size(s->musb, 0, TUSB_EP0_CONFIG_XFR_SIZE(value), value & TUSB_EP0_CONFIG_DIR_TX); break; case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b): epnum = (offset - TUSB_EP_IN_SIZE) >> 2; s->tx_config[epnum] = value; musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 1); break; case TUSB_DMA_EP_MAP: s->dma_map = value; break; case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b): epnum = (offset - TUSB_EP_OUT_SIZE) >> 2; s->rx_config[epnum] = value; musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 0); break; case TUSB_EP_MAX_PACKET_SIZE_OFFSET ... (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b): return; /* TODO */ case TUSB_WAIT_COUNT: return; /* TODO */ case TUSB_SCRATCH_PAD: s->scratch = value; break; case TUSB_PROD_TEST_RESET: s->test_reset = value; break; default: printf("%s: unknown register at %03x\n", __FUNCTION__, offset); return; } }
static uint64_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset, unsigned size) { PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; int tm = 0; switch (offset) { case OSMR3: tm ++; case OSMR2: tm ++; case OSMR1: tm ++; case OSMR0: return s->timer[tm].value; case OSMR11: tm ++; case OSMR10: tm ++; case OSMR9: tm ++; case OSMR8: tm ++; case OSMR7: tm ++; case OSMR6: tm ++; case OSMR5: tm ++; case OSMR4: if (!pxa2xx_timer_has_tm4(s)) goto badreg; return s->tm4[tm].tm.value; case OSCR: return s->clock + muldiv64(qemu_get_clock_ns(vm_clock) - s->lastload, s->freq, get_ticks_per_sec()); case OSCR11: tm ++; case OSCR10: tm ++; case OSCR9: tm ++; case OSCR8: tm ++; case OSCR7: tm ++; case OSCR6: tm ++; case OSCR5: tm ++; case OSCR4: if (!pxa2xx_timer_has_tm4(s)) goto badreg; if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) { if (s->tm4[tm - 1].freq) s->snapshot = s->tm4[tm - 1].clock + muldiv64( qemu_get_clock_ns(vm_clock) - s->tm4[tm - 1].lastload, s->tm4[tm - 1].freq, get_ticks_per_sec()); else s->snapshot = s->tm4[tm - 1].clock; } if (!s->tm4[tm].freq) return s->tm4[tm].clock; return s->tm4[tm].clock + muldiv64(qemu_get_clock_ns(vm_clock) - s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec()); case OIER: return s->irq_enabled; case OSSR: /* Status register */ return s->events; case OWER: return s->reset3; case OMCR11: tm ++; case OMCR10: tm ++; case OMCR9: tm ++; case OMCR8: tm ++; case OMCR7: tm ++; case OMCR6: tm ++; case OMCR5: tm ++; case OMCR4: if (!pxa2xx_timer_has_tm4(s)) goto badreg; return s->tm4[tm].control; case OSNR: return s->snapshot; default: badreg: hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset); } return 0; }
static uint32_t get_pmtmr(PIIX4PMState *s) { uint32_t d; d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec()); return d & 0xffffff; }
static void ppc_heathrow_init (ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { CPUState *env = NULL; char *filename; qemu_irq *pic, **heathrow_irqs; int linux_boot, i; ram_addr_t ram_offset, bios_offset; uint32_t kernel_base, initrd_base, cmdline_base = 0; int32_t kernel_size, initrd_size; PCIBus *pci_bus; MacIONVRAMState *nvr; int bios_size; int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index; int escc_mem_index, ide_mem_index[2]; uint16_t ppc_boot_device; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; void *fw_cfg; void *dbdma; linux_boot = (kernel_filename != NULL); /* init CPUs */ if (cpu_model == NULL) cpu_model = "G3"; for (i = 0; i < smp_cpus; i++) { env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find PowerPC CPU definition\n"); exit(1); } /* Set time-base frequency to 16.6 Mhz */ cpu_ppc_tb_init(env, 16600000UL); qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); } /* allocate RAM */ if (ram_size > (2047 << 20)) { fprintf(stderr, "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n", ((unsigned int)ram_size / (1 << 20))); exit(1); } ram_offset = qemu_ram_alloc(NULL, "ppc_heathrow.ram", ram_size); cpu_register_physical_memory(0, ram_size, ram_offset); /* allocate and load BIOS */ bios_offset = qemu_ram_alloc(NULL, "ppc_heathrow.bios", BIOS_SIZE); if (bios_name == NULL) bios_name = PROM_FILENAME; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM); /* Load OpenBIOS (ELF) */ if (filename) { bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL, 1, ELF_MACHINE, 0); qemu_free(filename); } else { bios_size = -1; } if (bios_size < 0 || bios_size > BIOS_SIZE) { hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name); exit(1); } if (linux_boot) { uint64_t lowaddr = 0; int bswap_needed; #ifdef BSWAP_NEEDED bswap_needed = 1; #else bswap_needed = 0; #endif kernel_base = KERNEL_LOAD_ADDR; kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); if (kernel_size < 0) kernel_size = load_aout(kernel_filename, kernel_base, ram_size - kernel_base, bswap_needed, TARGET_PAGE_SIZE); if (kernel_size < 0) kernel_size = load_image_targphys(kernel_filename, kernel_base, ram_size - kernel_base); if (kernel_size < 0) { hw_error("qemu: could not load kernel '%s'\n", kernel_filename); exit(1); } /* load initrd */ if (initrd_filename) { initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); initrd_size = load_image_targphys(initrd_filename, initrd_base, ram_size - initrd_base); if (initrd_size < 0) { hw_error("qemu: could not load initial ram disk '%s'\n", initrd_filename); exit(1); } cmdline_base = round_page(initrd_base + initrd_size); } else { initrd_base = 0; initrd_size = 0; cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); } ppc_boot_device = 'm'; } else { kernel_base = 0; kernel_size = 0; initrd_base = 0; initrd_size = 0; ppc_boot_device = '\0'; for (i = 0; boot_device[i] != '\0'; i++) { /* TOFIX: for now, the second IDE channel is not properly * used by OHW. The Mac floppy disk are not emulated. * For now, OHW cannot boot from the network. */ #if 0 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { ppc_boot_device = boot_device[i]; break; } #else if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { ppc_boot_device = boot_device[i]; break; } #endif } if (ppc_boot_device == '\0') { fprintf(stderr, "No valid boot device for G3 Beige machine\n"); exit(1); } } isa_mem_base = 0x80000000; /* Register 2 MB of ISA IO space */ isa_mmio_init(0xfe000000, 0x00200000); /* XXX: we register only 1 output pin for heathrow PIC */ heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *)); heathrow_irqs[0] = qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1); /* Connect the heathrow PIC outputs to the 6xx bus */ for (i = 0; i < smp_cpus; i++) { switch (PPC_INPUT(env)) { case PPC_FLAGS_INPUT_6xx: heathrow_irqs[i] = heathrow_irqs[0] + (i * 1); heathrow_irqs[i][0] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; break; default: hw_error("Bus model not supported on OldWorld Mac machine\n"); } } /* init basic PC hardware */ if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { hw_error("Only 6xx bus is supported on heathrow machine\n"); } pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs); pci_bus = pci_grackle_init(0xfec00000, pic); pci_vga_init(pci_bus); escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); for(i = 0; i < nb_nics; i++) pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); ide_drive_get(hd, MAX_IDE_BUS); /* First IDE channel is a MAC IDE on the MacIO bus */ dbdma = DBDMA_init(&dbdma_mem_index); ide_mem_index[0] = -1; ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]); /* Second IDE channel is a CMD646 on the PCI bus */ hd[0] = hd[MAX_IDE_DEVS]; hd[1] = hd[MAX_IDE_DEVS + 1]; hd[3] = hd[2] = NULL; pci_cmd646_ide_init(pci_bus, hd, 0); /* cuda also initialize ADB */ cuda_init(&cuda_mem_index, pic[0x12]); adb_kbd_init(&adb_bus); adb_mouse_init(&adb_bus); nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 4); pmac_format_nvram_partition(nvr, 0x2000); macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem_index, dbdma_mem_index, cuda_mem_index, nvr, 2, ide_mem_index, escc_mem_index); if (usb_enabled) { usb_ohci_init_pci(pci_bus, -1); } if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) graphic_depth = 15; /* No PCI init: the BIOS will do it */ fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); if (kernel_cmdline) { fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); } else { fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); } fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); if (kvm_enabled()) { #ifdef CONFIG_KVM uint8_t *hypercall; fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); hypercall = qemu_malloc(16); kvmppc_get_hypercall(env, hypercall, 16); fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); #endif } else { fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec()); } qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); }
static uint32_t pl031_get_count(pl031_state *s) { /* This assumes qemu_get_clock returns the time since the machine was created. */ return s->tick_offset + qemu_get_clock(vm_clock) / get_ticks_per_sec(); }