void
discoverypic_setup(bus_space_tag_t memt, bus_space_handle_t memh)
{
struct discoverypic_ops *dsc;
uint32_t val;
dsc = malloc(sizeof(*dsc), M_DEVBUF, M_NOWAIT|M_ZERO);
if (!dsc)
panic("dsc_pic_setup: malloc(%zu) failed", sizeof(*dsc));
dsc->dsc_memt = memt;
dsc->dsc_memh = memh;
dsc->dsc_pic.pic_get_irq = dsc_get_irq;
dsc->dsc_pic.pic_enable_irq = dsc_enable_irq;
dsc->dsc_pic.pic_reenable_irq = dsc_enable_irq;
dsc->dsc_pic.pic_disable_irq = dsc_disable_irq;
dsc->dsc_pic.pic_ack_irq = dsc_ack_irq;
dsc->dsc_pic.pic_establish_irq = dsc_establish_irq;
dsc->dsc_pic.pic_source_name = dsc_source_name;
pic_add(&dsc->dsc_pic);
KASSERT(dsc->dsc_pic.pic_intrbase == 0);
pic = dscpic_setup(memt, memh);
intr_establish(dsc->dsc_pic.pic_intrbase + IRQ_GPP7_0,
IST_LEVEL, IPL_NONE, pic_handle_intr, pic);
intr_establish(dsc->dsc_pic.pic_intrbase + IRQ_GPP15_8,
IST_LEVEL, IPL_NONE, pic_handle_intr, pic);
intr_establish(dsc->dsc_pic.pic_intrbase + IRQ_GPP23_16,
IST_LEVEL, IPL_NONE, pic_handle_intr, pic);
intr_establish(dsc->dsc_pic.pic_intrbase + IRQ_GPP31_24,
IST_LEVEL, IPL_NONE, pic_handle_intr, pic);
}
void *
vbus_intr_establish(bus_space_tag_t t, bus_space_tag_t t0, int ihandle,
int level, int flags, int (*handler)(void *), void *arg, const char *what)
{
uint64_t sysino = INTVEC(ihandle);
struct intrhand *ih;
int err;
ih = bus_intr_allocate(t0, handler, arg, ihandle, level,
NULL, NULL, what);
if (ih == NULL)
return (NULL);
if (flags & BUS_INTR_ESTABLISH_MPSAFE)
ih->ih_mpsafe = 1;
intr_establish(ih->ih_pil, ih);
ih->ih_ack = vbus_intr_ack;
err = hv_intr_settarget(sysino, ih->ih_cpu->ci_upaid);
if (err != H_EOK)
return (NULL);
/* Clear pending interrupts. */
err = hv_intr_setstate(sysino, INTR_IDLE);
if (err != H_EOK)
return (NULL);
err = hv_intr_setenabled(sysino, INTR_ENABLED);
if (err != H_EOK)
return (NULL);
return (ih);
}
static void
amlogic_com_attach(device_t parent, device_t self, void *aux)
{
struct amlogic_com_softc * const asc = device_private(self);
struct com_softc * const sc = &asc->asc_sc;
struct amlogicio_attach_args * const aio = aux;
const struct amlogic_locators * const loc = &aio->aio_loc;
bus_space_tag_t iot = aio->aio_core_a4x_bst;
const bus_addr_t iobase = AMLOGIC_CORE_BASE + loc->loc_offset;
bus_space_handle_t ioh;
amlogic_com_ports |= __BIT(loc->loc_port);
sc->sc_dev = self;
sc->sc_frequency = AMLOGIC_UART_FREQ;
sc->sc_type = COM_TYPE_NORMAL;
if (com_is_console(iot, iobase, &ioh) == 0
&& bus_space_subregion(iot, aio->aio_bsh,
loc->loc_offset / 4, loc->loc_size, &ioh)) {
panic(": can't map registers");
}
COM_INIT_REGS(sc->sc_regs, iot, ioh, iobase);
com_attach_subr(sc);
aprint_naive("\n");
KASSERT(loc->loc_intr != AMLOGICIO_INTR_DEFAULT);
asc->asc_ih = intr_establish(loc->loc_intr, IPL_SERIAL,
IST_EDGE | IST_MPSAFE, comintr, sc);
if (asc->asc_ih == NULL)
panic("%s: failed to establish interrupt %d",
device_xname(self), loc->loc_intr);
}
static void
obiouart_attach(device_t parent, device_t self, void *aux)
{
struct com_obio_softc *osc = device_private(self);
struct com_softc *sc = &osc->sc_sc;
struct obio_attach_args *obio = aux;
bus_space_tag_t bst;
bus_space_handle_t bsh = 0;
bus_addr_t iobase;
sc->sc_dev = self;
bst = obio->obio_bst;
iobase = obio->obio_base + obio->obio_offset;
sc->sc_frequency = ROCKCHIP_UART_FREQ;
sc->sc_type = COM_TYPE_NORMAL;
if (com_is_console(bst, iobase, &bsh) == 0 &&
bus_space_subregion(bst, obio->obio_bsh, obio->obio_size, 0, &bsh)) {
panic(": can't map registers\n");
return;
}
COM_INIT_REGS(sc->sc_regs, bst, bsh, iobase);
com_attach_subr(sc);
aprint_naive("\n");
KASSERT(obio->obio_intr != OBIOCF_INTR_DEFAULT);
osc->sc_ih = intr_establish(obio->obio_intr, IPL_SERIAL, IST_LEVEL,
comintr, sc);
if (osc->sc_ih == NULL)
panic("%s: failed to establish interrup %d",
device_xname(self), obio->obio_intr);
}
void
com_eumb_attach(device_t parent, device_t self, void *aux)
{
struct com_softc *sc = device_private(self);
struct eumb_attach_args *eaa = aux;
int comaddr, epicirq;
bus_space_handle_t ioh;
extern u_long ticks_per_sec;
sc->sc_dev = self;
found = 1;
comaddr = (eaa->eumb_unit == 1) ? 0x4600 : 0x4500;
if (comaddr == cnregs.cr_iobase)
sc->sc_regs = cnregs;
else {
ioh = comaddr;
bus_space_map(eaa->eumb_bt, comaddr, COM_NPORTS, 0, &ioh);
COM_INIT_REGS(sc->sc_regs, eaa->eumb_bt, ioh, comaddr);
}
sc->sc_frequency = 4 * ticks_per_sec;
epicirq = (eaa->eumb_unit == 1) ? 25 : 24;
com_attach_subr(sc);
intr_establish(epicirq + 16, IST_LEVEL, IPL_SERIAL, comintr, sc);
}
static void
awin_tve_attach(device_t parent, device_t self, void *aux)
{
struct awin_tve_softc *sc = device_private(self);
struct awinio_attach_args * const aio = aux;
const struct awin_locators * const loc = &aio->aio_loc;
prop_dictionary_t cfg = device_properties(self);
int8_t tcon_unit = -1;
sc->sc_dev = self;
sc->sc_bst = aio->aio_core_bst;
bus_space_subregion(sc->sc_bst, aio->aio_core_bsh,
loc->loc_offset, loc->loc_size, &sc->sc_bsh);
if (prop_dictionary_get_int8(cfg, "tcon_unit", &tcon_unit)) {
sc->sc_tcon_unit = tcon_unit;
} else {
sc->sc_tcon_unit = 0; /* default value */
}
sc->sc_tcon_pll = awin_tcon_get_clk_pll(sc->sc_tcon_unit);
switch (sc->sc_tcon_pll) {
case 3:
awin_pll3_enable();
break;
case 7:
awin_pll7_enable();
break;
default:
panic("awin_tve pll");
}
/* for now assume we're always at 0 */
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_AHB_GATING1_REG, AWIN_AHB_GATING1_TVE0, 0);
aprint_naive("\n");
aprint_normal(": TV Encoder / VGA output\n");
if (tcon_unit >= 0) {
aprint_verbose_dev(self, ": using TCON%d, pll%d\n",
sc->sc_tcon_unit, sc->sc_tcon_pll);
}
sc->sc_i2c_blklen = 16;
#if 0
sc->sc_ih = intr_establish(loc->loc_intr, IPL_SCHED, IST_LEVEL,
awin_tve_intr, sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(self, "couldn't establish interrupt %d\n",
loc->loc_intr);
return;
}
aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
#endif
awin_tve_i2c_init(sc);
awin_tve_enable(sc);
awin_tve_read_edid(sc);
}
static void
gemini_com_attach(device_t parent, device_t self, void *aux)
{
struct com_softc *sc = device_private(self);
struct obio_attach_args *obio = aux;
bus_space_tag_t iot;
bus_space_handle_t ioh;
bus_addr_t iobase;
sc->sc_dev = self;
iot = obio->obio_iot;
iobase = obio->obio_addr;
sc->sc_frequency = GEMINI_COM_FREQ;
sc->sc_type = COM_TYPE_16550_NOERS;
if (com_is_console(iot, iobase, &ioh) == 0 &&
bus_space_map(iot, iobase, obio->obio_size, 0, &ioh)) {
panic(": can't map registers\n");
return;
}
COM_INIT_REGS(sc->sc_regs, iot, ioh, iobase);
com_attach_subr(sc);
aprint_naive("\n");
intr_establish(obio->obio_intr, IPL_SERIAL, IST_LEVEL_HIGH,
comintr, sc);
}
void
le_sbdio_attach(device_t parent, device_t self, void *aux)
{
struct le_sbdio_softc *lesc = device_private(self);
struct sbdio_attach_args *sa = aux;
struct lance_softc *sc = &lesc->sc_am7990.lsc;
bus_dma_segment_t seg;
int rseg;
sc->sc_dev = self;
lesc->sc_dmat = sa->sa_dmat;
lesc->sc_bst = sa->sa_bust;
if (bus_space_map(lesc->sc_bst, sa->sa_addr1, 8 /* XXX */,
BUS_SPACE_MAP_LINEAR, &lesc->sc_bsh) != 0) {
aprint_error(": cannot map registers\n");
return;
}
/* Allocate DMA memory for the chip. */
if (bus_dmamem_alloc(lesc->sc_dmat, LE_MEMSIZE, 0, 0, &seg, 1, &rseg,
BUS_DMA_NOWAIT) != 0) {
aprint_error(": can't allocate DMA memory\n");
return;
}
if (bus_dmamem_map(lesc->sc_dmat, &seg, rseg, LE_MEMSIZE,
(void **)&sc->sc_mem, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) != 0) {
aprint_error(": can't map DMA memory\n");
return;
}
if (bus_dmamap_create(lesc->sc_dmat, LE_MEMSIZE, 1, LE_MEMSIZE,
0, BUS_DMA_NOWAIT, &lesc->sc_dmamap) != 0) {
aprint_error(": can't create DMA map\n");
return;
}
if (bus_dmamap_load(lesc->sc_dmat, lesc->sc_dmamap, sc->sc_mem,
LE_MEMSIZE, NULL, BUS_DMA_NOWAIT) != 0) {
aprint_error(": can't load DMA map\n");
return;
}
sc->sc_memsize = LE_MEMSIZE;
sc->sc_addr = lesc->sc_dmamap->dm_segs[0].ds_addr;
sc->sc_conf3 = LE_C3_BSWP | LE_C3_BCON;
(*platform.ether_addr)(sc->sc_enaddr);
sc->sc_copytodesc = lance_copytobuf_contig;
sc->sc_copyfromdesc = lance_copyfrombuf_contig;
sc->sc_copytobuf = lance_copytobuf_contig;
sc->sc_copyfrombuf = lance_copyfrombuf_contig;
sc->sc_zerobuf = lance_zerobuf_contig;
#ifdef LEDEBUG
sc->sc_debug = 0xff;
#endif
sc->sc_rdcsr = le_sbdio_rdcsr;
sc->sc_wrcsr = le_sbdio_wrcsr;
am7990_config(&lesc->sc_am7990);
intr_establish(sa->sa_irq, am7990_intr, sc);
}
void *
pci_intr_establish(void *v, pci_intr_handle_t ih, int level,
int (*func)(void *), void *arg)
{
int type;
if (brdtype == BRD_STORCENTER && ih == 1) {
/*
* XXX This is a workaround for the VT6410 IDE controller!
* Apparently its interrupt cannot be disabled and remains
* asserted during the whole device probing procedure,
* causing an interrupt storm.
* Using an edge-trigger fixes that and triggers the
* interrupt only once during probing.
*/
type = IST_EDGE;
} else
type = IST_LEVEL;
/*
* ih is the value assigned in pci_intr_map(), above.
* It's the EPIC IRQ #.
*/
return intr_establish(ih + I8259_ICU, type, level, func, arg);
}
void
hil_intio_attach(struct device *parent, struct device *self, void *aux)
{
struct hil_softc *sc = (void *)self;
struct intio_attach_args *ia = aux;
extern struct consdev wsdisplay_cons;
sc->sc_bst = ia->ia_tag;
if (bus_space_map(sc->sc_bst, HILADDR,
HILMAPSIZE, 0, &sc->sc_bsh) != 0) {
printf(": couldn't map hil controller\n");
return;
}
/*
* Check that the configured console device is a wsdisplay.
*/
if (cn_tab != &wsdisplay_cons)
hil_is_console = 0;
hil_isr.isr_func = hil_intr;
hil_isr.isr_arg = sc;
hil_isr.isr_ipl = 1;
hil_isr.isr_priority = IPL_TTY;
printf(" ipl %d", hil_isr.isr_ipl);
hil_attach(sc, &hil_is_console);
intr_establish(&hil_isr, self->dv_xname);
startuphook_establish(hil_attach_deferred, sc);
}
void
com_cpc_attach(struct device *parent, struct device *self, void *aux)
{
struct cpcbus_attach_args *caa = aux;
struct com_cpc_softc *sc = (struct com_cpc_softc *)self;
int iobase = caa->cpca_addr;
int irq = caa->cpca_irq;
sc->sc_com.sc_iot = caa->cpca_tag;
sc->sc_com.sc_iobase = iobase;
if (!com_is_console(sc->sc_com.sc_iot, iobase, &sc->sc_com.sc_ioh) &&
bus_space_map(sc->sc_com.sc_iot, iobase, COM_NPORTS, 0,
&sc->sc_com.sc_ioh)) {
printf("%s: can't map i/o space\n", self->dv_xname);
return;
}
sc->sc_com.sc_frequency = CPC_COM_SPEED(caa->cpca_freq);
com_attach_subr(&sc->sc_com);
sc->sc_ih = intr_establish(irq, IST_LEVEL, IPL_SERIAL, comintr,
&sc->sc_com);
}
void *
pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
int (*func)(void *), void *arg, char *what)
{
int pin, irq;
struct pic *pic;
pic = &i8259_pic;
pin = irq = ih;
#if NIOAPIC > 0
if (ih & APIC_INT_VIA_APIC) {
pic = (struct pic *)ioapic_find(APIC_IRQ_APIC(ih));
if (pic == NULL) {
printf("pci_intr_establish: bad ioapic %d\n",
APIC_IRQ_APIC(ih));
return NULL;
}
pin = APIC_IRQ_PIN(ih);
irq = APIC_IRQ_LEGACY_IRQ(ih);
if (irq < 0 || irq >= NUM_LEGACY_IRQS)
irq = -1;
}
#endif
return intr_establish(irq, pic, pin, IST_LEVEL, level, func, arg, what);
}
static void
awin_otg_attach(device_t parent, device_t self, void *aux)
{
struct awin_otg_softc *sc = device_private(self);
struct awinio_attach_args * const aio = aux;
const struct awin_locators * const loc = &aio->aio_loc;
aprint_naive("\n");
aprint_normal(": OTG\n");
if (awin_chip_id() == AWIN_CHIP_ID_A31) {
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_USB_CLK_REG,
AWIN_A31_USB_CLK_USBPHY0_ENABLE |
AWIN_A31_USB_CLK_PHY0_ENABLE, 0);
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_AHB_GATING0_REG, AWIN_A31_AHB_GATING0_USB0, 0);
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_A31_AHB_RESET0_REG, AWIN_A31_AHB_RESET0_USBOTG_RST, 0);
} else {
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_AHB_GATING0_REG, AWIN_AHB_GATING0_USB0, 0);
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_USB_CLK_REG,
AWIN_USB_CLK_USBPHY_ENABLE|AWIN_USB_CLK_PHY0_ENABLE, 0);
awin_reg_set_clear(aio->aio_core_bst, aio->aio_core_bsh,
AWIN_SRAM_OFFSET + AWIN_SRAM_CTL1_REG,
__SHIFTIN(AWIN_SRAM_CTL1_SRAMD_MAP_USB0,
AWIN_SRAM_CTL1_SRAMD_MAP),
0);
}
sc->sc_motg.sc_dev = self;
sc->sc_motg.sc_bus.dmatag = aio->aio_dmat;
sc->sc_motg.sc_iot = aio->aio_core_bst;
bus_space_subregion(sc->sc_motg.sc_iot, aio->aio_core_bsh,
loc->loc_offset, loc->loc_size, &sc->sc_motg.sc_ioh);
sc->sc_motg.sc_size = loc->loc_size;
sc->sc_motg.sc_intr_poll = awin_otg_poll;
sc->sc_motg.sc_intr_poll_arg = sc;
sc->sc_motg.sc_mode = MOTG_MODE_HOST;
sc->sc_motg.sc_ep_max = 5;
sc->sc_motg.sc_ep_fifosize = 512;
sc->sc_ih = intr_establish(loc->loc_intr, IPL_USB, IST_LEVEL,
awin_otg_intr, sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(self, "couldn't establish interrupt %d\n",
loc->loc_intr);
return;
}
device_printf(self, "interrupting at irq %d\n", loc->loc_intr);
awin_otg_init(sc);
motg_init(&sc->sc_motg);
}
static void
ehci_awinusb_attach(device_t parent, device_t self, void *aux)
{
struct awinusb_softc * const usbsc = device_private(parent);
struct ehci_softc * const sc = device_private(self);
struct awinusb_attach_args * const usbaa = aux;
int irq;
sc->sc_dev = self;
sc->iot = usbaa->usbaa_bst;
sc->ioh = usbaa->usbaa_bsh;
sc->sc_size = usbaa->usbaa_size;
sc->sc_bus.dmatag = usbaa->usbaa_dmat;
sc->sc_bus.hci_private = sc;
sc->sc_bus.usbrev = USBREV_2_0;
sc->sc_ncomp = 0;
if (usbsc->usbsc_ohci_dev != NULL) {
sc->sc_comps[sc->sc_ncomp++] = usbsc->usbsc_ohci_dev;
}
//sc->sc_id_vendor = PCI_VENDOR_ALLWINNER;
strlcpy(sc->sc_vendor, "Allwinner", sizeof(sc->sc_vendor));
aprint_naive(": EHCI USB controller\n");
aprint_normal(": EHCI USB controller\n");
int error = ehci_init(sc);
if (error != USBD_NORMAL_COMPLETION) {
aprint_error_dev(self, "init failed, error=%d\n", error);
return;
}
/* Attach usb device. */
sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint);
switch (awin_chip_id()) {
case AWIN_CHIP_ID_A80:
irq = awinusb_ehci_irqs_a80[usbaa->usbaa_port];
break;
case AWIN_CHIP_ID_A31:
irq = awinusb_ehci_irqs_a31[usbaa->usbaa_port];
break;
default:
irq = awinusb_ehci_irqs[usbaa->usbaa_port];
break;
}
usbsc->usbsc_ehci_ih = intr_establish(irq, IPL_VM,
IST_LEVEL, ehci_intr, sc);
if (usbsc->usbsc_ehci_ih == NULL) {
aprint_error_dev(self, "failed to establish interrupt %d\n",
irq);
return;
}
aprint_normal_dev(self, "interrupting on irq %d\n", irq);
}
void *
pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
int (*func)(void *), void *arg)
{
if (ih == 0 || ih >= ICU_LEN)
panic("pci_intr_establish: bogus handle 0x%x\n", ih);
return intr_establish(ih, IST_LEVEL, level, func, arg);
}
void
ti_sbus_attach(struct device *parent, struct device *self, void *aux)
{
struct confargs *ca = aux;
struct ti_sbus_softc *tsc = (void *)self;
struct ti_softc *sc = &tsc->tsc_sc;
bus_space_handle_t ioh;
/* Pass on the bus tags */
tsc->tsc_rr = ca->ca_ra.ra_reg[1];
sc->ti_btag = &tsc->tsc_rr;
sc->sc_dmatag = iommu_dmatag;
if (ca->ca_ra.ra_nintr < 1) {
printf(": no interrupt\n");
return;
}
if (ca->ca_ra.ra_nreg < 2) {
printf(": only %d register sets\n", ca->ca_ra.ra_nreg);
return;
}
if (bus_space_map(&ca->ca_ra.ra_reg[1], 0,
ca->ca_ra.ra_reg[1].rr_len, 0, &sc->ti_bhandle)) {
printf(": can't map registers\n");
return;
}
if (bus_space_map(&ca->ca_ra.ra_reg[0], 0,
ca->ca_ra.ra_reg[0].rr_len, 0, &ioh)) {
printf(": can't map registers\n");
goto fail;
}
tsc->tsc_ih.ih_fun = ti_intr;
tsc->tsc_ih.ih_arg = sc;
intr_establish(ca->ca_ra.ra_intr[0].int_pri, &tsc->tsc_ih,
IPL_NET, self->dv_xname);
bus_space_write_4(sc->ti_btag, ioh, TI_PCI_CMDSTAT, 0x02000006);
bus_space_write_4(sc->ti_btag, ioh, TI_PCI_BIST, 0xffffffff);
bus_space_write_4(sc->ti_btag, ioh, TI_PCI_LOMEM, 0x00000400);
bus_space_unmap(&ca->ca_ra.ra_reg[0], ioh, ca->ca_ra.ra_reg[0].rr_len);
sc->ti_sbus = 1;
if (ti_attach(sc) == 0)
return;
fail:
bus_space_unmap(&ca->ca_ra.ra_reg[1], sc->ti_bhandle,
ca->ca_ra.ra_reg[1].rr_len);
}
static void
exynos_usb_attach(device_t parent, device_t self, void *aux)
{
struct exynos_usb_softc * const sc = &exynos_usb_sc;
struct fdt_attach_args *const faa = aux;
bus_addr_t addr;
bus_size_t size;
int error;
if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
aprint_error(": couldn't get registers\n");
return;
}
sc->sc_self = self;
// sc->sc_irq = loc->loc_intr;
/* get our bushandles */
sc->sc_bst = faa->faa_bst;
// sc->sc_dmat = exyoaa->exyo_dmat;
// sc->sc_dmat = exyoaa->exyo_coherent_dmat;
error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
if (error) {
aprint_error(": couldn't map %#llx: %d",
(uint64_t)addr, error);
return;
}
aprint_normal(" @ 0x%08x: USB - NOT IMPLEMENTED", (uint)addr);
aprint_naive("\n");
aprint_normal("\n");
/* power up USB subsystem */
// exynos_usb_soc_powerup();
/* init USB phys */
// exynos_usb_phy_init(sc->sc_usb2phy_bsh);
#if 0
/* claim shared interrupt for OHCI/EHCI */
sc->sc_intrh = intr_establish(sc->sc_irq,
IPL_USB, IST_LEVEL, exynos_usb_intr, sc);
if (!sc->sc_intrh) {
aprint_error(": unable to establish interrupt at irq %d\n",
sc->sc_irq);
/* disable? TBD */
return;
}
#endif
aprint_normal_dev(sc->sc_self, "USB host NOT IMPLEMENTED\n");
}
void *
pci_msi_establish(struct pci_attach_args *pa, int level,
int (*func)(void *), void *arg)
{
int co;
struct intrhand *ih;
struct msi_hdl *msih;
struct cpu_info *ci;
struct intrsource *is;
pcireg_t reg;
if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, &co, 0))
return NULL;
ih = intr_establish(-1, &msi_pic, -1, IST_EDGE, level, func, arg, 0);
if (ih == NULL)
return NULL;
msih = malloc(sizeof(*msih), M_DEVBUF, M_WAITOK);
msih->ih = ih;
msih->pc = pa->pa_pc;
msih->tag = pa->pa_tag;
msih->co = co;
ci = ih->ih_cpu;
is = ci->ci_isources[ih->ih_slot];
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, co + PCI_MSI_CTL);
pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MADDR64_LO,
LAPIC_MSIADDR_BASE |
__SHIFTIN(ci->ci_cpuid, LAPIC_MSIADDR_DSTID_MASK));
if (reg & PCI_MSI_CTL_64BIT_ADDR) {
pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MADDR64_HI,
0);
/* XXX according to the manual, ASSERT is unnecessary if
* EDGE
*/
pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MDATA64,
__SHIFTIN(is->is_idtvec, LAPIC_MSIDATA_VECTOR_MASK) |
LAPIC_MSIDATA_TRGMODE_EDGE | LAPIC_MSIDATA_LEVEL_ASSERT |
LAPIC_MSIDATA_DM_FIXED);
} else {
/* XXX according to the manual, ASSERT is unnecessary if
* EDGE
*/
pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MDATA,
__SHIFTIN(is->is_idtvec, LAPIC_MSIDATA_VECTOR_MASK) |
LAPIC_MSIDATA_TRGMODE_EDGE | LAPIC_MSIDATA_LEVEL_ASSERT |
LAPIC_MSIDATA_DM_FIXED);
}
pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_CTL,
PCI_MSI_CTL_MSI_ENABLE);
return msih;
}
static void
n900audjck_attach(device_t parent, device_t self, void *aux)
{
struct n900audjck_softc *sc = device_private(self);
struct gpio_attach_args *ga = aux;
int caps;
sc->sc_dev = self;
sc->sc_gpio = ga->ga_gpio;
/* map pins */
sc->sc_map.pm_map = sc->sc_map_pins;
if (gpio_pin_map(sc->sc_gpio, ga->ga_offset, ga->ga_mask,
&sc->sc_map)) {
aprint_error(": couldn't map the pins\n");
return;
}
/* configure the input pin */
caps = gpio_pin_caps(sc->sc_gpio, &sc->sc_map, N900AUDJCK_PIN_INPUT);
if (!(caps & GPIO_PIN_INPUT)) {
aprint_error(": pin is unable to read input\n");
gpio_pin_unmap(sc->sc_gpio, &sc->sc_map);
return;
}
gpio_pin_ctl(sc->sc_gpio, &sc->sc_map, N900AUDJCK_PIN_INPUT,
GPIO_PIN_INPUT);
sc->sc_intr = intr_establish(N900AUDJCK_GPIO_BASE + ga->ga_offset,
IPL_VM, IST_EDGE_BOTH, n900audjck_intr, sc);
if (sc->sc_intr == NULL) {
aprint_error(": couldn't establish interrupt\n");
gpio_pin_unmap(sc->sc_gpio, &sc->sc_map);
return;
}
aprint_normal(": N900 audio jack\n");
aprint_naive(": N900 audio jack\n");
if (!pmf_device_register(sc->sc_dev, NULL, NULL)) {
aprint_error_dev(sc->sc_dev,
"couldn't establish power handler\n");
}
sysmon_task_queue_init();
sc->sc_smpsw.smpsw_name = device_xname(self);
sc->sc_smpsw.smpsw_type = PSWITCH_TYPE_HOTKEY;
sc->sc_state = PSWITCH_EVENT_RELEASED;
sysmon_pswitch_register(&sc->sc_smpsw);
/* report an event immediately if an audio jack is inserted */
n900audjck_refresh(sc);
}
void
gpio_gpio_attach(struct device *parent, struct device *self, void *aux)
{
struct gpio_softc *sc = device_private(self);
struct confargs *ca = aux;
sc->sc_port = device_private(parent)->sc_port;
intr_establish(ca->ca_intr[0], IST_LEVEL, IPL_HIGH, gpio_intr, sc);
printf(" irq %d\n", ca->ca_intr[0]);
}
void *
pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
int (*func)(void *), void *arg, const char *what)
{
int pin, irq;
int bus, dev;
pcitag_t tag = ih.tag;
struct pic *pic;
if (ih.line & APIC_INT_VIA_MSG) {
return intr_establish(-1, &msi_pic, tag, IST_PULSE, level,
func, arg, what);
}
pci_decompose_tag(pc, ih.tag, &bus, &dev, NULL);
#if NACPIPRT > 0
acpiprt_route_interrupt(bus, dev, ih.pin);
#endif
pic = &i8259_pic;
pin = irq = ih.line;
#if NIOAPIC > 0
if (ih.line & APIC_INT_VIA_APIC) {
pic = (struct pic *)ioapic_find(APIC_IRQ_APIC(ih.line));
if (pic == NULL) {
printf("pci_intr_establish: bad ioapic %d\n",
APIC_IRQ_APIC(ih.line));
return NULL;
}
pin = APIC_IRQ_PIN(ih.line);
irq = APIC_IRQ_LEGACY_IRQ(ih.line);
if (irq < 0 || irq >= NUM_LEGACY_IRQS)
irq = -1;
}
#endif
return intr_establish(irq, pic, pin, IST_LEVEL, level, func, arg, what);
}
static void
openpic_establish_ipi(int type, int level, void *ih_args)
{
/*
* XXX
* for now we catch IPIs early in pic_handle_intr() so no need to do anything
* here
*/
#if 0
intr_establish(ipiops.ppc_ipi_vector, type, level, ppcipi_intr,
ih_args);
#endif
}
static void
ehci_obio_attach(device_t parent, device_t self, void *aux)
{
struct ehci_softc * const sc = device_private(self);
struct obio_attach_args * const obio = aux;
const char * const devname = device_xname(self);
usbd_status r;
sc->sc_dev = self;
sc->sc_bus.hci_private = sc;
sc->iot = obio->obio_iot;
aprint_naive(": EHCI USB controller\n");
aprint_normal(": EHCI USB controller\n");
/* Map I/O registers */
if (bus_space_map(sc->iot, obio->obio_addr, obio->obio_size, 0,
&sc->ioh)) {
aprint_error("%s: can't map memory space\n", devname);
return;
}
sc->sc_bus.dmatag = obio->obio_dmat;
/* Disable interrupts, so we don't get any spurious ones. */
sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
DPRINTF(("%s: offs=%d\n", devname, sc->sc_offs));
EOWRITE2(sc, EHCI_USBINTR, 0);
bus_space_write_4(sc->iot, sc->ioh, EHCI_HCOTGDEV_INTR_MASK,
OTG_INT|DEV_INT);
if (obio->obio_intr != OBIOCF_INTR_DEFAULT) {
intr_establish(obio->obio_intr, IPL_USB, IST_LEVEL,
ehci_obio_intr, sc);
}
sc->sc_bus.usbrev = USBREV_2_0;
/* Figure out vendor for root hub descriptor. */
sc->sc_id_vendor = PCI_VENDOR_FARADAY;
strlcpy(sc->sc_vendor, "SL351x", sizeof(sc->sc_vendor));
r = ehci_init(sc);
if (r != USBD_NORMAL_COMPLETION) {
aprint_error("%s: init failed, error=%d\n", devname, r);
return;
}
/* Attach usb device. */
sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint);
}
/*
* gt_comm_intr_init - enable GT-64260 Comm Unit interrupts
*/
static void
gt_comm_intr_enb(struct gt_softc *gt)
{
u_int32_t cause;
cause = gt_read(gt, GT_CommUnitIntr_Cause);
if (cause)
gt_write(gt, GT_CommUnitIntr_Cause, ~cause);
gt_write(gt, GT_CommUnitIntr_Mask, GT_CommUnitIntr_DFLT);
(void)gt_read(gt, GT_CommUnitIntr_ErrAddr);
intr_establish(IRQ_COMM, IST_LEVEL, IPL_GTERR, gt_comm_intr, gt);
printf("%s: Comm Unit irpt at %d\n", gt->gt_dev.dv_xname, IRQ_COMM);
}
void
ehci_obio_attach(struct device *parent, struct device *self, void *aux)
{
struct ehci_softc *sc = (void *)self;
struct obio_attach_args *oa = aux;
usbd_status r;
int s;
sc->iot = oa->oa_iot;
sc->sc_size = 1028;
if (bus_space_map(sc->iot, oa->oa_offset + USB_EHCI_OFFSET,
sc->sc_size, 0, &sc->ioh)) {
printf(": can't map registers\n");
return;
}
sc->sc_id_vendor = PCI_VENDOR_FREESCALE;
strlcpy(sc->sc_vendor, "Freescale", sizeof sc->sc_vendor);
sc->sc_bus.dmatag = &ehci_bus_dma_tag;
bus_space_write_4(sc->iot, sc->ioh, USB_CONTROL, USB_CONTROL_USB_EN);
bus_space_write_4(sc->iot, sc->ioh, USB_SNOOP1, USB_SNOOP_2GB);
s = splhardusb();
sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
EOWRITE2(sc, EHCI_USBINTR, 0);
intr_establish(oa->oa_ivec, IST_LEVEL, IPL_USB, ehci_intr, sc,
sc->sc_bus.bdev.dv_xname);
r = ehci_init(sc);
if (r != USBD_NORMAL_COMPLETION) {
printf(": init failed, error=%d\n", r);
goto unmap_ret;
}
splx(s);
printf("\n");
/* Attach usb device. */
sc->sc_child = config_found((void *)sc, &sc->sc_bus, usbctlprint);
return;
unmap_ret:
bus_space_unmap(sc->iot, sc->ioh, sc->sc_size);
splx(s);
}
void *
vbus_intr_establish(bus_space_tag_t t, int ihandle, int level,
int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */)
{
uint64_t sysino = INTVEC(ihandle);
struct intrhand *ih;
int ino;
int err;
DPRINTF(VBUS_INTR, ("vbus_intr_establish()\n"));
ino = INTINO(ihandle);
ih = intrhand_alloc();
ih->ih_ivec = ihandle;
ih->ih_fun = handler;
ih->ih_arg = arg;
ih->ih_pil = level;
ih->ih_number = ino;
ih->ih_pending = 0;
intr_establish(ih->ih_pil, level != IPL_VM, ih);
ih->ih_ack = vbus_intr_ack;
err = hv_intr_settarget(sysino, cpus->ci_cpuid);
if (err != H_EOK) {
printf("hv_intr_settarget(%lu, %u) failed - err = %d\n",
(long unsigned int)sysino, cpus->ci_cpuid, err);
return (NULL);
}
/* Clear pending interrupts. */
err = hv_intr_setstate(sysino, INTR_IDLE);
if (err != H_EOK) {
printf("hv_intr_setstate(%lu, INTR_IDLE) failed - err = %d\n",
(long unsigned int)sysino, err);
return (NULL);
}
err = hv_intr_setenabled(sysino, INTR_ENABLED);
if (err != H_EOK) {
printf("hv_intr_setenabled(%lu) failed - err = %d\n",
(long unsigned int)sysino, err);
return (NULL);
}
return (ih);
}
static void
pckbc_elb_intr_establish(struct pckbc_softc *sc, pckbc_slot_t slot)
{
struct pckbc_elb_softc *msc = (void *)sc;
int irq = msc->sc_irq;
/*
* We ignore slot since all slots use the same interrupt.
*/
if (irq >= 0)
intr_establish(irq, IST_LEVEL, IPL_SERIAL, pckbcintr, sc);
irq = -1;
}
static void
tegra_ahcisata_attach(device_t parent, device_t self, void *aux)
{
struct tegra_ahcisata_softc * const sc = device_private(self);
struct tegraio_attach_args * const tio = aux;
const struct tegra_locators * const loc = &tio->tio_loc;
prop_dictionary_t prop = device_properties(self);
const char *pin;
sc->sc_bst = tio->tio_bst;
bus_space_subregion(tio->tio_bst, tio->tio_bsh,
loc->loc_offset, loc->loc_size, &sc->sc_bsh);
sc->sc.sc_atac.atac_dev = self;
sc->sc.sc_dmat = tio->tio_dmat;
sc->sc.sc_ahcit = tio->tio_bst;
sc->sc.sc_ahcis = loc->loc_size - TEGRA_AHCISATA_OFFSET;
bus_space_subregion(tio->tio_bst, tio->tio_bsh,
loc->loc_offset + TEGRA_AHCISATA_OFFSET,
loc->loc_size - TEGRA_AHCISATA_OFFSET, &sc->sc.sc_ahcih);
sc->sc.sc_ahci_quirks = AHCI_QUIRK_SKIP_RESET;
aprint_naive("\n");
aprint_normal(": SATA\n");
if (prop_dictionary_get_cstring_nocopy(prop, "power-gpio", &pin)) {
sc->sc_pin_power = tegra_gpio_acquire(pin, GPIO_PIN_OUTPUT);
if (sc->sc_pin_power)
tegra_gpio_write(sc->sc_pin_power, 1);
}
tegra_car_periph_sata_enable();
tegra_xusbpad_sata_enable();
tegra_ahcisata_init(sc);
sc->sc_ih = intr_establish(loc->loc_intr, IPL_BIO, IST_LEVEL,
ahci_intr, &sc->sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(self, "couldn't establish interrupt %d\n",
loc->loc_intr);
return;
}
aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
ahci_attach(&sc->sc);
}
static void
awin_com_attach(device_t parent, device_t self, void *aux)
{
cfdata_t cf = device_cfdata(self);
struct awin_com_softc * const asc = device_private(self);
struct com_softc * const sc = &asc->asc_sc;
struct awinio_attach_args * const aio = aux;
const struct awin_locators * const loc = &aio->aio_loc;
bus_space_tag_t iot = aio->aio_core_a4x_bst;
const bus_addr_t iobase = AWIN_CORE_PBASE + loc->loc_offset;
const struct awin_gpio_pinset *pinset;
bus_space_handle_t ioh;
if (awin_chip_id() == AWIN_CHIP_ID_A31) {
pinset = awin_com_pinsets_a31;
} else if (awin_chip_id() == AWIN_CHIP_ID_A80) {
pinset = awin_com_pinsets_a80;
} else {
pinset = loc->loc_port + ((cf->cf_flags & 1) ?
awin_com_alt_pinsets : awin_com_pinsets);
}
awin_com_ports |= __BIT(loc->loc_port);
awin_gpio_pinset_acquire(pinset);
sc->sc_dev = self;
sc->sc_frequency = AWIN_UART_FREQ;
sc->sc_type = COM_TYPE_NORMAL;
if (com_is_console(iot, iobase, &ioh) == 0
&& bus_space_subregion(iot, aio->aio_core_bsh,
loc->loc_offset / 4, loc->loc_size, &ioh)) {
panic(": can't map registers");
}
COM_INIT_REGS(sc->sc_regs, iot, ioh, iobase);
com_attach_subr(sc);
aprint_naive("\n");
KASSERT(loc->loc_intr != AWINIO_INTR_DEFAULT);
asc->asc_ih = intr_establish(loc->loc_intr, IPL_SERIAL,
IST_EDGE | IST_MPSAFE, comintr, sc);
if (asc->asc_ih == NULL)
panic("%s: failed to establish interrupt %d",
device_xname(self), loc->loc_intr);
}
static void
awin_p2wi_attach(device_t parent, device_t self, void *aux)
{
struct awin_p2wi_softc *sc = device_private(self);
struct awinio_attach_args * const aio = aux;
const struct awin_locators * const loc = &aio->aio_loc;
struct i2cbus_attach_args iba;
sc->sc_dev = self;
sc->sc_bst = aio->aio_core_bst;
sc->sc_rsb_p = awin_chip_id() == AWIN_CHIP_ID_A80;
mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SCHED);
cv_init(&sc->sc_cv, "awinp2wi");
bus_space_subregion(sc->sc_bst,
sc->sc_rsb_p ? aio->aio_a80_rcpus_bsh : aio->aio_core_bsh,
loc->loc_offset, loc->loc_size, &sc->sc_bsh);
aprint_naive("\n");
aprint_normal(": %s\n", sc->sc_rsb_p ? "RSB" : "P2WI");
sc->sc_ih = intr_establish(loc->loc_intr, IPL_SCHED, IST_LEVEL,
awin_p2wi_intr, sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(self, "couldn't establish interrupt %d\n",
loc->loc_intr);
return;
}
aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
/* Enable interrupts */
P2WI_WRITE(sc, AWIN_A31_P2WI_INTE_REG,
AWIN_A31_P2WI_INTE_LOAD_BSY_ENB |
AWIN_A31_P2WI_INTE_TRANS_ERR_ENB |
AWIN_A31_P2WI_INTE_TRANS_OVER_ENB);
P2WI_WRITE(sc, AWIN_A31_P2WI_CTRL_REG,
AWIN_A31_P2WI_CTRL_GLOBAL_INT_ENB);
sc->sc_ic.ic_cookie = sc;
sc->sc_ic.ic_acquire_bus = awin_p2wi_acquire_bus;
sc->sc_ic.ic_release_bus = awin_p2wi_release_bus;
sc->sc_ic.ic_exec = awin_p2wi_exec;
memset(&iba, 0, sizeof(iba));
iba.iba_tag = &sc->sc_ic;
sc->sc_i2cdev = config_found_ia(self, "i2cbus", &iba, iicbus_print);
}
