void kmain() { irq_disable(); /* * A primeira coisa a se fazer é iniciar todo o gerenciador * de memória. */ mm_init(); arch_early_init(); ioremap_init(); irq_init(); sched_init(); timer_init(); /* * Neste momento temos o gerenciador de memória e escalonador prontos, * já podemos habilitar as interrupções, que podem ser utilizadas * pelos drivers. */ irq_enable(); /* Inicia os drivers da plataforma */ arch_setup(); /* Requisita um modo se existir um framebuffer*/ fb_set_mode(); /* Inicia o console sobre o framebuffer */ fb_console_init(); kernel_info(); #if 1 irq_disable(); semaphore_init(&sem, 1); create_task("a", 4); create_task("b", 5); create_task("c", 6); create_task("d", 7); create_task("b", 8); create_task("b", 9); irq_enable(); /* Fica de boas esperando as trocas de contexto */ #endif /* Como queremos imprimir para depuração do driver, inicializamos ele agora */ //bcm2835_emmc_init(); for (;;) { led_blink(); //printk("-"); } }
void process_exit_test() { process_table_init(); process_create(1, (int) serial_test_write_exit_1); process_create(1, (int) serial_test_write_exit_2); process_create(1, (int) toggle_led1); devices_init(); irq_init(); timer_init(); irq_register_context_switch(); irq_enable(); kernel_to_user_mode(); }
void serial_test_calc() { process_table_init(); process_create(1, (int) toggle_led1); process_create(1, (int) serial_test_calculator); devices_init(); irq_init(); timer_init(); irq_register_context_switch(); irq_enable(); kernel_to_user_mode(); }
int board_init(void) { init_sc520(); bus_init(); irq_init(); /* max drive current on SDRAM */ sc520_mmcr->dsctl = 0x0100; /* enter debug mode after next reset (only if jumper is also set) */ sc520_mmcr->rescfg = 0x08; /* configure the software timer to 33.333MHz */ sc520_mmcr->swtmrcfg = 0; gd->bus_clk = 33333000; return 0; }
void init_all(void) { // initialize Stick BaseStickConfig(); // Heitmann SCS |= 1; //Umschalten von Port0 und Port1 auf Fast GPIO FIO0DIR = (1 << 16); //Setzen der Richtungsbits FIO1DIR = (1 << 16) | 0xFF; // Unteren 8 bit=> out (also wir duerfen dort schreiben) // initialize Buffer init_BUF(); // initialize rest timer_init(); irq_init(); pwm_init(); }
void init_system() { uint8_t cpuid = smp_processor_id(); setup_vector(); setup_httbr((uint32_t) &__HYP_PGTABLE); setup_mem_attr(); if (cpuid == 0) { // TODO(wonseok) console init will be moved dev_init(). console_init(); libc_init(); } irq_init(); //enable_traps(); if (cpuid == 0) { paging_create((addr_t) &__HYP_PGTABLE); platform_init(); dev_init(); /* we don't have */ vdev_init(); /* Already we have */ timer_hw_init(NS_PL2_PTIMER_IRQ); setup_vm_mmap(); #ifdef CONFIG_SMP printf("wake up...other CPUs\n"); secondary_smp_pen = 1; #endif } printf("%s[%d]: CPU[%d]\n", __func__, __LINE__, cpuid); enable_mmu(); start_hypervisor(); }
int main() { copy_vec(); irq_init(); button_init(); uart0_init(); timer_init(); // timer4_init(); lcd_init(); lcd_clean(0xffff); adc_ts_init(); ts_init(); // tslib_calibrate(); // lcd_clean(0xffff); nand_init(); #if 1 nand_read_id(); while(1); #endif printf("\r\n\n"); printf("===============================================\r\n"); printf(" NAND FLASH PROGRAMMING \r\n"); unsigned int size = 512 * 1024; // 512KB nand_read_id(); printf("erase entire flash, waiting ... \r\n"); int i; for(i = 0; i < 2048; i++) nand_erase_block(i); printf("start program ... \r\n"); nand_write_bytes(0x0, (unsigned char *)0x31000000, size); printf("program end ... \r\n"); printf("===============================================\r\n"); while(1); return 0; }
int main() { // Init interrupts and VBlank irq. irq_init(NULL); irq_add(II_VBLANK, mmVBlank); mmInitDefault( (mm_addr)soundbank_bin, 8 ); CreditDevkitArmandtonc(); MainMenu(); while(1) { VBlankIntrWait(); } return 0; }
/*---------------------------------------------------------------------------*/ PROCESS_THREAD(sensors_process, ev, data) { static int i; static int events; PROCESS_BEGIN(); for(i = 0; sensors[i] != NULL; ++i) { sensors_flags[i] = 0; sensors[i]->init(); } num_sensors = i; sensors_event = process_alloc_event(); irq_init(); while(1) { PROCESS_WAIT_EVENT(); do { events = 0; for(i = 0; i < num_sensors; ++i) { if(sensors_flags[i] & FLAG_CHANGED) { /* if(sensors_selecting_proc[i] == SELCOLL || sensors_selecting_proc[i] == NULL) process_post(PROCESS_BROADCAST, sensors_event, sensors[i]); else process_post(sensors_selecting_proc[i], sensors_event, sensors[i]);*/ if(process_post(PROCESS_BROADCAST, sensors_event, sensors[i]) == PROCESS_ERR_OK) { PROCESS_WAIT_EVENT_UNTIL(ev == sensors_event); } sensors_flags[i] &= ~FLAG_CHANGED; events++; } } } while(events); } PROCESS_END(); }
void console_test() { process_table_init(); //process_create(1, (int) toggle_led1); //process_create(1, (int) toggle_led2); //process_create(1, (int) dummy_process); // process_create(1, (int) console_start); devices_init(); irq_init(); timer_init(); irq_register_context_switch(); irq_enable(); kernel_to_user_mode(); }
int main() { //Start video driver (must always be before loading message) mm_init(); pg_init(); real_init(); video_init(); video_setdriver(video_vgatext_getdriver(),0); //Put loading message cli_puts("ArcaneOS Loading...\n"); //Setup kernel gdt_init(); idt_init(); isr_init(); irq_init(); timer_init(); kb_init(); ui_init(); cpuid_init(); cmos_init(); rtc_init(); acpi_init(); power_init(); mt_init(); syscall_init(); floppy_init(); __asm__ __volatile__ ("sti"); //Enable ACPI acpi_enable(); //Create thread for ui mt_create_thread(mt_kernel_process,test,2); //Endless loop to prevent bugs when all threads are sleeping for(;;) __asm__ __volatile__ ("hlt"); }
void timer_test() { process_table_init(); process_create(1, (int)toggle_led1); process_create(1, (int)toggle_led2); devices_init(); irq_init(); timer_init(); //timer_add_handler(toggle_led_1, 5000); //timer_add_handler(toggle_led_2, 10000); irq_register_context_switch(); irq_enable(); kernel_to_user_mode(); }
/******************************************************************************* Routine Name: _initPeri Form: static void _initPeri( void ) Parameters: void Return value: void Description: initialize peripheral. *******************************************************************************/ static void _initPeri( void ) { /*--- BLKCON ---*/ BLKCON2 = 0xC9; // UART0 BLKCON4 = 0x01; BLKCON6 = 0xC0; // BLKCON7 = 0x00; // PWMC/D/E/F /*--- Interrupt ---*/ irq_di(); irq_init(); (void)irq_setHdr( (unsigned char)IRQ_NO_PA0INT, _intPA0 ); (void)irq_setHdr( (unsigned char)IRQ_NO_TMBINT, _intTMB ); QPA0 = 0; QTMB = 0; EPA0 = 1; ETMB = 1; irq_ei(); /*---- WDT ---*/ WDTMOD = WDT_23MS; // main_clrWDT(); /*--- Clock ---*/ clk_setSysclk(); /*--- TBC ---*/ (void)tb_setHtbdiv( (unsigned char)TB_HTD_1_1 ); /*--- Timer ---*/ tm_init( TM_CH_NO_AB ); /* Timer channel */ tm_setABSource(TM_CS_LSCLK); /* Operation clock */ tm_setABData( (unsigned short)(MAIN_TIMER_CNT) ); /* Timer count value */ tm_startAB(); _swInit(); /*--- LED ---*/ led_Init(); }
// Starts system void init_system(multiboot_info_t* bi) { // Start display vga_init(); printk(" KiteOS V1.0 --- Initializing \n"); // PIT-less wait to show user boot for(int i=0;i<64821125;i++); vga_color(0x3, 0x0); printk("-- STARTING LOWLEVEL KERNEL --\n"); vga_color(0x5, 0x0); printk("!* Initiating GDT\n"); gdt_init(); printk("!* Initiating IDT\n"); idt_init(); printk("!* Installing Exceptions\n"); isr_init(); vga_color(0x4, 0x0); printk("*** ENTERTED PROTECTED MODE ***\n"); vga_color(0x5, 0x0); printk("!* Initiating IRQ\n"); irq_init(); printk("!* Starting PIT\n"); pit_init(); printk("!* Starting RTC\n"); rtc_init(); printk("!* Restoring Interrupts\n"); __asm__ __volatile__ ("sti"); vga_color(0x3, 0x0); printk("-- STARTING LOWLEVEL DRIVERS --\n"); vga_color(0x5, 0x0); printk("!* Starting physical memory manager\n"); kalloc_init((void*)bi->mmap_addr, (unsigned long)bi->mmap_length); printk("!* Starting keyboard driver\n"); kb_init(); printk("!* Starting IDE driver\n"); ide_init(0x1F0, 0x3F6, 0x170, 0x366); vga_color(0x4, 0x0); printk("*** Initialized system successfully ***\n"); }
extern void swap_init_nios2(void); int alt_main(void) { const char *message = "(THU.CST) os is loading ..."; kprintf("%s\n\n", message); mp_init(); pmm_init(); // init physical memory management pmm_init_ap(); vmm_init(); // init virtual memory management
void kmain(mboot_info_t *mboot_info,uint32_t mboot_magic,uint32_t stack_ptr){ /* vga konsol */ init_vga_console(); time_init(); debug_print(KERN_INFO,"Stack pointer : \033[1;7m%P",stack_ptr); if(mboot_magic != MULTIBOOT_LOADER_MAGIC) debug_print(KERN_WARNING,"Invalid the magic number. The magic number is \033[1;31m%P",mboot_magic); else debug_print(KERN_INFO,"Valid the magic number.The magic number is \033[1;37m%P",mboot_magic); /* * gdt,idt,isr ve irq */ gdt_init(); /* global tanimlayici tablosu */ idt_init(); /* kesme tanimlayici tablosu */ isr_init(); /* kesme servis istekleri */ irq_init(); /* donanim kesme istekleri */ #if 0 __int_test(); #endif timer_init(); /* * memory */ paging_init(mboot_info->mem_lower + mboot_info->mem_upper); paging_final(); #if 0 __page_fault_test(); #endif heap_init(); multitasking_init(); }
void serial_test() { process_table_init(); // process_create(1, (int)serial_test_test_yield); // process_create(1, (int)toggle_led1_yield); // process_create(1, (int)toggle_led2_yield); //process_create(1, (int) led1_on); //process_create(1, (int) led1_off); process_create(1, (int) toggle_led1); process_create(1, (int) toggle_led2); //process_create(1, (int) serial_test_write_1); //process_create(1, (int) serial_test_write_2); //process_create(1, (int) serial_test_write_3); //process_create(1, (int) serial_test_write_4); //process_create(1, (int) serial_test_write_5); process_create(1, (int) serial_test_calculator); devices_init(); serial_test_create(); irq_init(); timer_init(); irq_register_context_switch(); irq_enable(); kernel_to_user_mode(); // sys_yield(); // serial_test_test(); }
//******************************************************************************** // local functions //******************************************************************************** void init(void) { /* --- MIE Disable --- */ __DI(); /* Set oscillation mode */ clk_setLsclk( CLK_XTM_CRYSTAL ); /* crystal/ceramic oscillation */ /* Wait stables crystal oscillation */ while( (clk_getClkStatus() & FSTAT_LOSCS) != 0 ) {} clk_disHsclk(); // stop HSCLK oscillation clk_setHsclk( (unsigned char)(CLK_SYSC_OSCLK | CLK_OSCM_RC | CLK_OUTC_OSCLK | CLK_LOSCON_DIS), CLK_LOSCON_DIS ); /* set HSCLK */ // BUG620Q504 clk_enaHsclk(); // start HSCLK oscillation clk_setSysclk( CLK_SYSCLK_HSCLK ); // Choose HSCLK clk_block_ctrl_init(); /* Block Control */ // irq handler initialization irq_init(); /* Interrupt */ // Watch dog timer irq_sethandler(IRQ_NO_WDTINT,watch_dog_isr); wdt_init( WDTMOD_WDT1 | WDTMOD_WDT0); wdt_disHaltCount(); // Initializing GPIO lazurite_gpio_init(); // Initializing timer init_timer(); /* MIE Enable */ rst_interrupts(); __EI(); return; }
int board_init(void) { #ifndef CONFIG_USE_IRQ irq_init(); #endif /* arch number of the board */ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; /* address of boot parameters */ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; /* setup the SUSPSRC for ARM to control emulation suspend */ writel(readl(&davinci_syscfg_regs->suspsrc) & ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | DAVINCI_SYSCFG_SUSPSRC_UART0), &davinci_syscfg_regs->suspsrc); /* configure pinmux settings */ if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) return 1; #ifdef CONFIG_DRIVER_TI_EMAC davinci_emac_mii_mode_sel(HAS_RMII); #endif /* CONFIG_DRIVER_TI_EMAC */ /* enable the console UART */ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | DAVINCI_UART_PWREMU_MGMT_UTRST), #if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) &davinci_uart0_ctrl_regs->pwremu_mgmt); #else &davinci_uart2_ctrl_regs->pwremu_mgmt); #endif return 0; }
int board_init(void) { int i, ret; #ifndef CONFIG_USE_IRQ irq_init(); #endif /* address of boot parameters, not used as booting with DTT */ gd->bd->bi_boot_params = 0; for (i = 0; i < ARRAY_SIZE(enbw_gpio_config); i++) { int gpio = enbw_gpio_config[i].bank * 16 + enbw_gpio_config[i].gpio; ret = gpio_request(gpio, enbw_gpio_config[i].name); if (ret) { printf("%s: Could not get %s gpio\n", __func__, enbw_gpio_config[i].name); return -1; } if (enbw_gpio_config[i].out) gpio_direction_output(gpio, enbw_gpio_config[i].value); else gpio_direction_input(gpio); } /* setup the SUSPSRC for ARM to control emulation suspend */ clrbits_le32(&davinci_syscfg_regs->suspsrc, (DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | DAVINCI_SYSCFG_SUSPSRC_UART2)); return 0; }
void idt_init(void) { idt_ptr.limit = sizeof(idt_entry_t) * 256 -1; idt_ptr.base = (u32int)&idt_entries; // Remap the irq table. outb(0x20, 0x11); outb(0xA0, 0x11); outb(0x21, 0x20); outb(0xA1, 0x28); outb(0x21, 0x04); outb(0xA1, 0x02); outb(0x21, 0x01); outb(0xA1, 0x01); outb(0x21, 0x0); outb(0xA1, 0x0); memset((u8int*)&idt_entries, 0, sizeof(idt_entry_t)*256); isr_init(); // Interruptions - entries 0-31 irq_init(); // IRQs - entries 32-47 idt_flush((u32int)&idt_ptr); }
int main(void) { #if WITH_SD int r; #endif /* WITH_SD */ msp430_cpu_init(); watchdog_stop(); /* Platform-specific initialization. */ msb_ports_init(); adc_init(); clock_init(); rtimer_init(); sht11_init(); leds_init(); leds_on(LEDS_ALL); irq_init(); process_init(); /* serial interface */ rs232_set_input(serial_line_input_byte); rs232_init(); serial_line_init(); uart_lock(UART_MODE_RS232); uart_unlock(UART_MODE_RS232); #if WITH_UIP slip_arch_init(BAUD2UBR(115200)); #endif #if WITH_SD r = sd_initialize(); if(r < 0) { printf("Failed to initialize the SD driver: %s\n", sd_error_string(r)); } else { sd_offset_t capacity; printf("The SD driver was successfully initialized\n"); capacity = sd_get_capacity(); if(capacity < 0) { printf("Failed to get the SD card capacity: %s\n", sd_error_string(r)); } else { printf("SD card capacity: %u MB\n", (unsigned)(capacity / (1024UL * 1024))); } } #endif /* System services */ process_start(&etimer_process, NULL); ctimer_init(); node_id_restore(); init_net(); energest_init(); #if PROFILE_CONF_ON profile_init(); #endif /* PROFILE_CONF_ON */ leds_off(LEDS_ALL); printf(CONTIKI_VERSION_STRING " started. Node id %u, using %s.\n", node_id, rime_mac->name); autostart_start(autostart_processes); /* * This is the scheduler loop. */ ENERGEST_ON(ENERGEST_TYPE_CPU); while (1) { int r; #if PROFILE_CONF_ON profile_episode_start(); #endif /* PROFILE_CONF_ON */ do { /* Reset watchdog. */ watchdog_periodic(); r = process_run(); } while(r > 0); #if PROFILE_CONF_ON profile_episode_end(); #endif /* PROFILE_CONF_ON */ /* * Idle processing. */ int s = splhigh(); /* Disable interrupts. */ if (process_nevents() != 0) { splx(s); /* Re-enable interrupts. */ } else { static unsigned long irq_energest = 0; /* Re-enable interrupts and go to sleep atomically. */ ENERGEST_OFF(ENERGEST_TYPE_CPU); ENERGEST_ON(ENERGEST_TYPE_LPM); /* * We only want to measure the processing done in IRQs when we * are asleep, so we discard the processing time done when we * were awake. */ energest_type_set(ENERGEST_TYPE_IRQ, irq_energest); if (uart_edge) { _BIC_SR(LPM1_bits + GIE); } else { _BIS_SR(LPM1_bits + GIE); } /* * We get the current processing time for interrupts that was * done during the LPM and store it for next time around. */ dint(); irq_energest = energest_type_time(ENERGEST_TYPE_IRQ); eint(); ENERGEST_OFF(ENERGEST_TYPE_LPM); ENERGEST_ON(ENERGEST_TYPE_CPU); #if PROFILE_CONF_ON profile_clear_timestamps(); #endif /* PROFILE_CONF_ON */ } } return 0; }
int board_early_init_f(void) { /* PinMux for GPIO */ if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) return 1; /* Set DISP_ON high to enable LCD output*/ gpio_direction_output(97, 1); /* Set the RESETOUTn low */ gpio_direction_output(111, 0); /* Set U0_SW0 low for UART0 as console*/ gpio_direction_output(106, 0); /* Set U0_SW1 low for UART0 as console*/ gpio_direction_output(108, 0); /* Set LCD_B_PWR low to power down LCD Backlight*/ gpio_direction_output(102, 0); #ifndef CONFIG_USE_IRQ irq_init(); #endif /* * NAND CS setup - cycle counts based on da850evm NAND timings in the * Linux kernel @ 25MHz EMIFA */ #ifdef CONFIG_NAND_DAVINCI writel((DAVINCI_ABCR_WSETUP(0) | DAVINCI_ABCR_WSTROBE(1) | DAVINCI_ABCR_WHOLD(0) | DAVINCI_ABCR_RSETUP(0) | DAVINCI_ABCR_RSTROBE(1) | DAVINCI_ABCR_RHOLD(0) | DAVINCI_ABCR_TA(0) | DAVINCI_ABCR_ASIZE_8BIT), &davinci_emif_regs->ab1cr); /* CS2 */ #endif /* * Power on required peripherals * ARM does not have access by default to PSC0 and PSC1 * assuming here that the DSP bootloader has set the IOPU * such that PSC access is available to ARM */ if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) return 1; /* setup the SUSPSRC for ARM to control emulation suspend */ writel(readl(&davinci_syscfg_regs->suspsrc) & ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | DAVINCI_SYSCFG_SUSPSRC_UART0), &davinci_syscfg_regs->suspsrc); /* configure pinmux settings */ if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) return 1; #ifdef CONFIG_DRIVER_TI_EMAC if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) return 1; davinci_emac_mii_mode_sel(HAS_RMII); #endif /* CONFIG_DRIVER_TI_EMAC */ /* enable the console UART */ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | DAVINCI_UART_PWREMU_MGMT_UTRST), &davinci_uart0_ctrl_regs->pwremu_mgmt); /* * Reconfigure the LCDC priority to the highest to ensure that * the throughput/latency requirements for the LCDC are met. */ writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff, &davinci_syscfg_regs->mstpri[2]); return 0; }
int main() { irq_init(); // This will eventually be used to identify whether save data has been // created. As of right now, there is no need for save data, but that // will change in the future. It is likely that 64 kiB of save data // will be more than enough. memcpy8( game_manager::sram_init_str, game_manager::sram_const_init_str, game_manager::sram_init_str_size ); //asm_comment("Before first show_debug_s32_group() call"); //show_debug_s32_group // ( fixedu12p4_packed::get_underlying_type_is_signed(), // fixeds12p4_packed::get_underlying_type_is_signed(), // fixeds8p8_packed::get_underlying_type_is_signed(), // sizeof(fixedu12p4_packed), // sizeof(fixeds12p4_packed), // sizeof(fixeds8p8_packed) ); // //asm_comment("Before second show_debug_s32_group() call"); //show_debug_s32_group( make_f24p8( -3, 5 ).data, // make_f8p8( -3, 5 ).data, // make_fu12p4_packed( 10, 12 ).data, // make_fs12p4_packed( -3, 5 ).data, // make_fs8p8_packed( 124, 200 ).data ); //arr_memfill8( (u8*)ewram_test_arr, '#', ewram_test_arr_size ); //memset( ewram_test_arr, '#', ewram_test_arr_size ); //memset( ewram_test_arr, '#', 4 ); //ewram_test_arr[0] = '9'; //memset( &ewram_test_arr[1], '3', 9 ); //memcpy( &ewram_test_arr[1], test_str, 5 ); //slower_memcpy( &ewram_test_arr[1], test_str, 5 ); //memcpy( &ewram_test_arr[1] //halt(); game_manager::title_screen_func(); // This function is called by game_manager::title_screen_func(). //game_manager::reinit_the_game(); for (;;) { gfx_manager::back_up_bgofs_mirror(); sprite& the_player = *sprite_manager::the_player; debug_arr_group::clear_debug_vars(); clear_oam_mirror(); // Key polling is done in game_manager::vblank_func() //key_poll(); if ( soft_reset_keys_down() ) { // Reset the game if A, B, Start, and Select are pressed //bios_do_hard_reset(); ////bios_do_soft_reset(); game_manager::reinit_the_game(); } sprite_manager::find_all_active_sprites(); // Despawn sprites that are too far offscreen. sprite_manager::despawn_sprites_if_needed (gfx_manager::bgofs_mirror[0].curr); sprite_manager::find_all_active_sprites(); sprite_manager::update_all_sprites ( active_level::get_curr_sublevel_ptr().get_size_2d(), gfx_manager::bgofs_mirror[0] ); // This is temporary if ( key_hit_or_held(key_l) ) { sprite_manager::spawn_a_sprite_basic( st_waffle, the_player.in_level_pos.curr, gfx_manager::bgofs_mirror[0], (bool)the_player.the_oam_entry.get_hflip_status() ); } //if ( key_hit(key_select) ) //{ // game_manager::fade_out_to_black(1); // // game_manager::wait_for_x_frames(60); // // game_manager::fade_in(1); //} sprite_manager::spawn_sprites_if_needed (gfx_manager::bgofs_mirror[0]); //if ( key_hit(key_l) ) //{ // --player_sprite_stuff::remaining_hp; //} //if ( key_hit(key_r) ) //{ // ++player_sprite_stuff::remaining_hp; //} // //active_level_manager::update_sublevel_in_screenblock_mirror_2d // ( active_level::bg0_screenblock_mirror_2d, // test_level.get_size_2d() ); active_level_manager::update_sublevel_in_screenblock_mirror_2d(); bios_wait_for_vblank(); //game_manager::vblank_func(); } return 0; }
int board_init(void) { #ifdef CONFIG_USE_NOR u32 val; #endif #ifndef CONFIG_USE_IRQ irq_init(); #endif #ifdef CONFIG_NAND_DAVINCI /* * NAND CS setup - cycle counts based on da850evm NAND timings in the * Linux kernel @ 25MHz EMIFA */ writel((DAVINCI_ABCR_WSETUP(0) | DAVINCI_ABCR_WSTROBE(1) | DAVINCI_ABCR_WHOLD(0) | DAVINCI_ABCR_RSETUP(0) | DAVINCI_ABCR_RSTROBE(1) | DAVINCI_ABCR_RHOLD(0) | DAVINCI_ABCR_TA(1) | DAVINCI_ABCR_ASIZE_8BIT), &davinci_emif_regs->ab2cr); /* CS3 */ #endif /* arch number of the board */ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; /* address of boot parameters */ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; /* * Power on required peripherals * ARM does not have access by default to PSC0 and PSC1 * assuming here that the DSP bootloader has set the IOPU * such that PSC access is available to ARM */ if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) return 1; /* setup the SUSPSRC for ARM to control emulation suspend */ writel(readl(&davinci_syscfg_regs->suspsrc) & ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | DAVINCI_SYSCFG_SUSPSRC_UART2), &davinci_syscfg_regs->suspsrc); /* configure pinmux settings */ if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) return 1; #ifdef CONFIG_USE_NOR /* Set the GPIO direction as output */ clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); /* Set the output as low */ val = readl(GPIO_BANK0_REG_SET_ADDR); val |= (0x01 << 11); writel(val, GPIO_BANK0_REG_CLR_ADDR); #endif #ifdef CONFIG_DRIVER_TI_EMAC if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) return 1; davinci_emac_mii_mode_sel(HAS_RMII); #endif /* CONFIG_DRIVER_TI_EMAC */ /* enable the console UART */ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | DAVINCI_UART_PWREMU_MGMT_UTRST), &davinci_uart2_ctrl_regs->pwremu_mgmt); return 0; }
void game_manager::title_screen_func() { curr_game_mode = gm_title_screen; irq_init(); //irqEnable(irq_vblank); bios_wait_for_vblank(); // Use video Mode 0, use 1D object mapping, enable forced blank, // and display BG 0. reg_dispcnt = dcnt_mode0 | dcnt_obj_1d | dcnt_blank_on | dcnt_bg0_on; //// Use video Mode 0, use 1D object mapping, enable forced blank, //// and display BG 0, BG 1, BG 2, and BG 3 //reg_dispcnt = dcnt_mode0 | dcnt_obj_1d | dcnt_blank_on | dcnt_bg0_on // | dcnt_bg1_on | dcnt_bg2_on | dcnt_bg3_on | dcnt_obj_on; // Use screen base block 28 for BG0's Map reg_bg0cnt = bgcnt_sbb(bg0_sbb); reg_bg1cnt = bgcnt_sbb(bg1_sbb); reg_bg2cnt = bgcnt_sbb(bg2_sbb); reg_bg3cnt = bgcnt_sbb(bg3_sbb); // Clear bgofs_mirror for ( u32 i=0; i<3; ++i ) { gfx_manager::bgofs_mirror[i].curr.x = gfx_manager::bgofs_mirror[i].prev.x = {0}; gfx_manager::bgofs_mirror[i].curr.y = gfx_manager::bgofs_mirror[i].prev.y = {0}; } gfx_manager::copy_bgofs_mirror_to_registers(); // Copy the title screen's tiles and tilemap to VRAM bios_do_lz77_uncomp_vram( title_screenTiles, bg_tile_vram ); gfx_manager::upload_bg_palettes_to_target(bg_pal_ram); // This is sort of a hack. bios_do_lz77_uncomp_wram( title_screenMap, active_level::bg0_screenblock_mirror ); active_level_manager::copy_sublevel_from_array_2d_helper_to_vram(); // Disable forced blank clear_bits( reg_dispcnt, dcnt_blank_mask ); //memcpy8( test_sram_arr, (void *)debug_arr_u32, test_sram_arr_size ); for (;;) { bios_wait_for_vblank(); key_poll(); // Start the game if the Start button is hit if ( key_hit(key_start) ) { irqSet( irq_vblank, (u32)mmVBlank ); irqEnable(irq_vblank); // Don't call mmInitDefault more than once. It uses malloc(), // and it apparently MaxMOD doesn't ever call free(). mmInitDefault( (mm_addr)practice_17_bin, 8 ); mmSetVBlankHandler(reinterpret_cast<void*>(vblank_func)); reinit_the_game(); break; } } }
void board_init(int with_irq) { /* Disable watchdog (compal loader leaves it enabled) */ wdog_enable(0); /* Configure memory interface */ calypso_mem_cfg(CALYPSO_nCS0, 3, CALYPSO_MEM_16bit, 1); calypso_mem_cfg(CALYPSO_nCS1, 3, CALYPSO_MEM_16bit, 1); calypso_mem_cfg(CALYPSO_nCS2, 5, CALYPSO_MEM_16bit, 1); calypso_mem_cfg(CALYPSO_nCS3, 5, CALYPSO_MEM_16bit, 1); calypso_mem_cfg(CALYPSO_CS4, 0, CALYPSO_MEM_8bit, 1); calypso_mem_cfg(CALYPSO_nCS6, 0, CALYPSO_MEM_32bit, 1); calypso_mem_cfg(CALYPSO_nCS7, 0, CALYPSO_MEM_32bit, 0); /* Set VTCXO_DIV2 = 1, configure PLL for 104 MHz and give ARM half of that */ calypso_clock_set(2, CALYPSO_PLL13_104_MHZ, ARM_MCLK_DIV_2); /* Configure the RHEA bridge with some sane default values */ calypso_rhea_cfg(0, 0, 0xff, 0, 1, 0, 0); /* Initialize board-specific GPIO */ board_io_init(); /* Enable bootrom mapping to route exception vectors to RAM */ calypso_bootrom(with_irq); calypso_exceptions_install(); /* Initialize interrupt controller */ if (with_irq) irq_init(); sercomm_bind_uart(UART_MODEM); cons_bind_uart(UART_IRDA); /* initialize MODEM UART to be used for sercomm */ uart_init(UART_MODEM, with_irq); uart_baudrate(UART_MODEM, UART_115200); /* initialize IRDA UART to be used for old-school console code. * note: IRDA uart only accessible on C115 and C117 PCB */ uart_init(UART_IRDA, with_irq); uart_baudrate(UART_IRDA, UART_115200); /* Initialize hardware timers */ hwtimer_init(); /* Initialize DMA controller */ dma_init(); /* Initialize real time clock */ rtc_init(); /* Initialize system timers (uses hwtimer 2) */ timer_init(); /* Initialize LCD driver (uses UWire) */ fb_init(); bl_mode_pwl(1); bl_level(0); /* Initialize keypad driver */ keypad_init(keymap, with_irq); /* Initialize ABB driver (uses SPI) */ twl3025_init(); /* enable LEDB driver of Iota for keypad backlight */ twl3025_reg_write(AUXLED, 0x02); }
int board_init(void) { irq_init(); #ifdef CONFIG_NAND_DAVINCI /* * NAND CS setup - cycle counts based on da850evm NAND timings in the * Linux kernel @ 25MHz EMIFA */ writel((DAVINCI_ABCR_WSETUP(2) | DAVINCI_ABCR_WSTROBE(2) | DAVINCI_ABCR_WHOLD(1) | DAVINCI_ABCR_RSETUP(1) | DAVINCI_ABCR_RSTROBE(4) | DAVINCI_ABCR_RHOLD(0) | DAVINCI_ABCR_TA(1) | DAVINCI_ABCR_ASIZE_8BIT), &davinci_emif_regs->ab2cr); /* CS3 */ #endif /* arch number of the board */ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; /* address of boot parameters */ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; /* setup the SUSPSRC for ARM to control emulation suspend */ writel(readl(&davinci_syscfg_regs->suspsrc) & ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | DAVINCI_SYSCFG_SUSPSRC_UART2), &davinci_syscfg_regs->suspsrc); /* configure pinmux settings */ if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) return 1; #ifdef CONFIG_USE_NOR /* Set the GPIO direction as output */ clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); /* Set the output as low */ writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR); #endif #ifdef CONFIG_MMC_DAVINCI /* Set the GPIO direction as output */ clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); /* Set the output as high */ writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR); #endif #ifdef CONFIG_DRIVER_TI_EMAC davinci_emac_mii_mode_sel(HAS_RMII); #endif /* CONFIG_DRIVER_TI_EMAC */ /* enable the console UART */ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | DAVINCI_UART_PWREMU_MGMT_UTRST), &davinci_uart2_ctrl_regs->pwremu_mgmt); return 0; }
/** * This is the architecture-independent kernel entry point. Before it is * called, architecture-specific code has done the bare minimum initialization * necessary. This function initializes the kernel and its various subsystems. * It calls back to architecture-specific code at several well defined points, * which all architectures must implement (e.g., setup_arch()). * * \callgraph */ void start_kernel() { unsigned int cpu; unsigned int timeout; int status; /* * Parse the kernel boot command line. * This is where boot-time configurable variables get set, * e.g., the ones with param() and DRIVER_PARAM() specifiers. */ parse_params(lwk_command_line); /* * Initialize the console subsystem. * printk()'s will be visible after this. */ console_init(); /* * Hello, Dave. */ printk("%s", lwk_banner); printk(KERN_DEBUG "%s\n", lwk_command_line); sort_exception_table(); /* * Do architecture specific initialization. * This detects memory, CPUs, architecture dependent irqs, etc. */ setup_arch(); /* * Setup the architecture independent interrupt handling. */ irq_init(); /* * Initialize the kernel memory subsystem. Up until now, the simple * boot-time memory allocator (bootmem) has been used for all dynamic * memory allocation. Here, the bootmem allocator is destroyed and all * of the free pages it was managing are added to the kernel memory * pool (kmem) or the user memory pool (umem). * * After this point, any use of the bootmem allocator will cause a * kernel panic. The normal kernel memory subsystem API should be used * instead (e.g., kmem_alloc() and kmem_free()). */ mem_subsys_init(); /* * Initialize the address space management subsystem. */ aspace_subsys_init(); sched_init_runqueue(0); /* This CPUs scheduler state + idle task */ sched_add_task(current); /* now safe to call schedule() */ /* * Initialize the task scheduling subsystem. */ core_timer_init(0); /* Start the kernel filesystems */ kfs_init(); /* * Initialize the random number generator. */ rand_init(); workq_init(); /* * Boot all of the other CPUs in the system, one at a time. */ printk(KERN_INFO "Number of CPUs detected: %d\n", num_cpus()); for_each_cpu_mask(cpu, cpu_present_map) { /* The bootstrap CPU (that's us) is already booted. */ if (cpu == 0) { cpu_set(cpu, cpu_online_map); continue; } printk(KERN_DEBUG "Booting CPU %u.\n", cpu); arch_boot_cpu(cpu); /* Wait for ACK that CPU has booted (5 seconds max). */ for (timeout = 0; timeout < 50000; timeout++) { if (cpu_isset(cpu, cpu_online_map)) break; udelay(100); } if (!cpu_isset(cpu, cpu_online_map)) panic("Failed to boot CPU %d.\n", cpu); } /* * Initialize the PCI subsystem. */ init_pci(); /* * Enable external interrupts. */ local_irq_enable(); #ifdef CONFIG_NETWORK /* * Bring up any network devices. */ netdev_init(); #endif #ifdef CONFIG_CRAY_GEMINI driver_init_list("net", "gemini"); #endif #ifdef CONFIG_BLOCK_DEVICE /** * Initialize the block devices */ blkdev_init(); #endif mcheck_init_late(); /* * And any modules that need to be started. */ driver_init_by_name( "module", "*" ); #ifdef CONFIG_KGDB /* * Stop eary (before "late" devices) in KGDB if requested */ kgdb_initial_breakpoint(); #endif /* * Bring up any late init devices. */ driver_init_by_name( "late", "*" ); /* * Bring up the Linux compatibility layer, if enabled. */ linux_init(); #ifdef CONFIG_DEBUG_HW_NOISE /* Measure noise/interference in the underlying hardware/VMM */ extern void measure_noise(int, uint64_t); measure_noise(0, 0); #endif /* * Start up user-space... */ printk(KERN_INFO "Loading initial user-level task (init_task)...\n"); if ((status = create_init_task()) != 0) panic("Failed to create init_task (status=%d).", status); current->state = TASK_EXITED; schedule(); /* This should not return */ BUG(); }
//=========================================================================== // Initialize Micro to Desired State... //=========================================================================== static void Initialization(void){ //Initialize Peripherals //BLKCON2 Control Bits...Manually Set 4/12/2013 DSIO0 = 1; // 0=> Enables Synchronous Serial Port 0 (initial value). DUA0 = 0; // 0=> Enables the operation of UART0 (initial value). DUA1 = 1; // 0=> Enables Uart1 (initial value). DI2C1 = 1; // 0=> Enables I2C bus Interface (Slave) (initial value). DI2C0 = 1; // 0=> Enables I2C bus Interface (Master) (initial value). BLKCON4 = 0x00; // 0=> Enables SA-ADC BLKCON6 = 0x00; // (1=disables; 0=enables) the operation of Timers 8, 9, A, E, F. BLKCON7 = 0x00; // (1=disables; 0=enables) the operation of PWW (PWMC, PWMD, PWME, PWMF // Port Initialize PortA_Low(); //Initialize all 3 Ports of Port A to GPIO-Low PortB_Low(); //Initialize all 8 Ports of Port B to GPIO-Low PortC_Low(); //Initialize all 8 Ports of Port C to GPIO-Low PortD_Low(); //Initialize all 6 Ports of Port D to GPIO-Low //Setup PIR Sensor Input on C.0 //Step 1: Set Pin Direction... //PC0DIR = 1; // PortC Bit0 set Direction to INPUT... //Step 2: Set Pin I/O Type... //PC0C1 = 0; // PortC Bit0 set Type to HIGH-IMPEDANCE INPUT... //PC0C0 = 0; //Step 3: Set Pin Purpose... //PC0MD1 = 0; // PortC Bit0 set Purpose to GENERAL PURPOSE Input/Output... //PC0MD0 = 0; // PWM... //PinB0_PWM(); // Set up PWM Pin on B.0... // Comparator... //analog_comparator(); // Set Oscillator Rate...Must Have. SetOSC(); // TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT // TIMER SETUP... Setup_Timer_8: // Reset TIMER DATA REGISTER... TM8D = 0; //Timer 8 DATA Register // Reset TIMER CLOCK REGISTER... TM8C = 0; //Timer 8 CLOCK Register // TIMER-8 Control... // CONTROL-0 Register: // Operation Clock for Timer... T8C1 = 0; // 01 = HTBCLK T8C0 = 1; // Count Mode... T89M16 = 0; // 0=8-Bit Mode; 1=16bit Mode... //One-Shot or Normal Mode... T8OST = 0; // 0=Normal; 1=One-Shot... // CONTROL-1 Register: // RUN Mode... T8RUN = 0; //0=STOP; 1=START... // TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT // IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII // INTERRUPT SETUP... irq_di(); // Disable Interrupts irq_init(); // Initialize Interrupts (All Off and NO Requests) // INTERRUPT ENABLE REGISTERS... // IE0 = VOLTAGE LEVEL SUPERVISOR Int. // IE1 = EXTERNAL Ints on B1, B0, A2, A1, & A0 // IE2 = SUCCESSIVE APPROXIMATION Int. // IE3 = TIMERS 8 & 9 Ints. // IE4 = UART & COMPARATOR Ints. // IE5 = TIMERS A, B, E & F Ints. // IE6 = PWMC & 128Hz & 32Hz TBC Ints. // IE7 = 16Hz & 2Hz TBC Ints. IE0 = IE1 = IE2 = IE3 = IE4 = IE5 = IE6 = IE7 = 0; // INTERRUPT REQUEST REGISTERS... // IRQ0 = WDT & VLS Int Requests // IRQ1 = EXTERNAL Int Requests // IRQ2 = SUCCESSIVE APPROXIMATION Int Requests // IRQ3 = TIMERS 8 & 9 Int Requests // IRQ4 = UART & COMPARATOR Int Requests // IRQ5 = TIMERS A, B, E & F Int Requests // IRQ6 = PWMC & 128Hz & 32Hz TBC Int Requests // IRQ7 = 16Hz & 2Hz TBC Int Requests IRQ0 = IRQ1 = IRQ2 = IRQ3 = IRQ4 = IRQ5 = IRQ6 = IRQ7 = 0; E2H = 0; // E2H is the Enable flag for 2Hz TBC Interrupt (1=ENABLED) //(void)irq_setHdr( (unsigned char)IRQ_NO_I2C0INT, _intI2c ); //(void)irq_setHdr( (unsigned char)IRQ_NO_UA1INT, _intUart ); (void)irq_setHdr( (unsigned char)IRQ_NO_UA0INT, _intUart ); EUA0 = 1; // EUA0 is the enable flag for the UART0 interrupt (1=ENABLED) irq_ei(); // Enable Interrupts // IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII // WDT... WDTMOD = 0x03; // 0x03=overflow 8sec... main_clrWDT(); // Clear WDT //Add EOL characters to strings HelloWorld[12] = 0x0D; HelloWorld[13] = 0x0A; InputStatus[21] = 0x0D; InputStatus[22] = 0x0A; InputRec[12] = 0x0D; InputRec[13] = 0x0A; OutputRec[21] = 0x0D; OutputRec[22] = 0x0A; AckMCUConn[20] = 0x0D; AckMCUConn[21] = 0x0A; //UART Initialization... (void)uart_init( (unsigned char)UART_CS_HSCLK, /* Generator */ (unsigned short)HSCLK_KHZ, /* HSCLK frequency */ &_uartSetParam ); /* Param... */ uart_PortSet(); _flgUartFin = 0; uart_stop(); uart_startSend(HelloWorld, 14, _funcUartFin); // Send, "Hello World!" while(_flgUartFin != 1){ NOP1000(); main_clrWDT(); } }