static void vt8237_usb_i_read_resources(struct device *dev)
{
#if CONFIG_EPIA_VT8237R_INIT
struct resource *res;
u8 function = (u8) dev->path.pci.devfn & 0x7;
printk(BIOS_SPEW, "VT8237R Fixing USB 1.1 fn %d I/O resource = 0x%04X\n", function, usb_io_addr[function]);
/* Fix the I/O Resources of the USB1.1 Interfaces */
/* Auto PCI probe seems to size the resources */
/* Incorrectly */
res = new_resource(dev, PCI_BASE_ADDRESS_4);
res->base = usb_io_addr[function];
res->size = 256;
res->limit = 0xffffUL;
res->align = 10;
res->gran = 8;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED |
IORESOURCE_ASSIGNED;
#else
pci_dev_read_resources(dev);
#endif
return;
}
static void cpu_pci_domain_read_resources(struct device *dev)
{
u16 nbid = pci_read_config16(dev_find_slot(0, 0), PCI_DEVICE_ID);
int i440fx = (nbid == 0x1237);
int q35 = (nbid == 0x29c0);
struct resource *res;
unsigned long tomk = 0, high;
int idx = 10;
int size;
pci_domain_read_resources(dev);
size = fw_cfg_check_file("etc/e820");
if (size > 0) {
/* supported by qemu 1.7+ */
FwCfgE820Entry *list = malloc(size);
int i;
fw_cfg_load_file("etc/e820", list);
for (i = 0; i < size/sizeof(*list); i++) {
switch (list[i].type) {
case 1: /* ram */
printk(BIOS_DEBUG, "QEMU: e820/ram: 0x%08llx +0x%08llx\n",
list[i].address, list[i].length);
if (list[i].address == 0) {
tomk = list[i].length / 1024;
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tomk - 768);
} else {
ram_resource(dev, idx++,
list[i].address / 1024,
list[i].length / 1024);
}
break;
case 2: /* reserved */
printk(BIOS_DEBUG, "QEMU: e820/res: 0x%08llx +0x%08llx\n",
list[i].address, list[i].length);
res = new_resource(dev, idx++);
res->base = list[i].address;
res->size = list[i].length;
res->limit = 0xffffffff;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
break;
default:
/* skip unknown */
break;
}
}
free(list);
}
if (!tomk) {
/* qemu older than 1.7, or reading etc/e820 failed. Fallback to cmos. */
tomk = qemu_get_memory_size();
high = qemu_get_high_memory_size();
printk(BIOS_DEBUG, "QEMU: cmos: %lu MiB RAM below 4G.\n", tomk / 1024);
printk(BIOS_DEBUG, "QEMU: cmos: %lu MiB RAM above 4G.\n", high / 1024);
/* Report the memory regions. */
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tomk - 768);
if (high)
ram_resource(dev, idx++, 4 * 1024 * 1024, high);
}
/* Reserve I/O ports used by QEMU */
qemu_reserve_ports(dev, idx++, 0x0510, 0x02, "firmware-config");
qemu_reserve_ports(dev, idx++, 0x5658, 0x01, "vmware-port");
if (i440fx) {
qemu_reserve_ports(dev, idx++, 0xae00, 0x10, "pci-hotplug");
qemu_reserve_ports(dev, idx++, 0xaf00, 0x20, "cpu-hotplug");
qemu_reserve_ports(dev, idx++, 0xafe0, 0x04, "piix4-gpe0");
}
if (inb(CONFIG_CONSOLE_QEMU_DEBUGCON_PORT) == 0xe9) {
qemu_reserve_ports(dev, idx++, CONFIG_CONSOLE_QEMU_DEBUGCON_PORT, 1,
"debugcon");
}
if (q35 && ((tomk * 1024) < 0xb0000000)) {
/*
* Reserve the region between top-of-ram and the
* mmconf xbar (ar 0xb0000000), so coreboot doesn't
* place pci bars there. The region isn't declared as
* pci io window in the acpi tables (\_SB.PCI0._CRS).
*/
res = new_resource(dev, idx++);
res->base = tomk * 1024;
res->size = 0xb0000000 - tomk * 1024;
res->limit = 0xffffffff;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
if (i440fx) {
/* Reserve space for the IOAPIC. This should be in
* the southbridge, but I couldn't tell which device
* to put it in. */
res = new_resource(dev, 2);
res->base = IO_APIC_ADDR;
res->size = 0x100000UL;
res->limit = 0xffffffffUL;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
/* Reserve space for the LAPIC. There's one in every processor, but
* the space only needs to be reserved once, so we do it here. */
res = new_resource(dev, 3);
res->base = LOCAL_APIC_ADDR;
res->size = 0x10000UL;
res->limit = 0xffffffffUL;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
IORESOURCE_ASSIGNED;
}
