static void __init of_gpio_clk_setup(struct device_node *node,
const char *gpio_name,
struct clk *(*clk_register_get)(const char *name,
const char * const *parent_names,
u8 num_parents,
unsigned gpio, bool active_low))
{
struct clk_gpio_delayed_register_data *data;
const char **parent_names;
int i, num_parents;
data = kzalloc(sizeof(*data), GFP_KERNEL);
if (!data)
return;
num_parents = of_clk_get_parent_count(node);
parent_names = kcalloc(num_parents, sizeof(char *), GFP_KERNEL);
if (!parent_names && num_parents > 0)
return;
for (i = 0; i < num_parents; i++)
parent_names[i] = of_clk_get_parent_name(node, i);
data->num_parents = max(num_parents, 0);
data->parent_names = parent_names;
data->node = node;
data->gpio_name = gpio_name;
data->clk_register_get = clk_register_get;
mutex_init(&data->lock);
of_clk_add_provider(node, of_clk_gpio_delayed_register_get, data);
}
static int __must_check of_clk_bulk_get_all(struct device_node *np,
struct clk_bulk_data **clks)
{
struct clk_bulk_data *clk_bulk;
int num_clks;
int ret;
num_clks = of_clk_get_parent_count(np);
if (!num_clks)
return 0;
clk_bulk = kmalloc_array(num_clks, sizeof(*clk_bulk), GFP_KERNEL);
if (!clk_bulk)
return -ENOMEM;
ret = of_clk_bulk_get(np, num_clks, clk_bulk);
if (ret) {
kfree(clk_bulk);
return ret;
}
*clks = clk_bulk;
return num_clks;
}
static void __init h8s2678_pll_clk_setup(struct device_node *node)
{
unsigned int num_parents;
struct clk *clk;
const char *clk_name = node->name;
const char *parent_name;
struct pll_clock *pll_clock;
struct clk_init_data init;
num_parents = of_clk_get_parent_count(node);
if (num_parents < 1) {
pr_err("%s: no parent found", clk_name);
return;
}
pll_clock = kzalloc(sizeof(struct pll_clock), GFP_KERNEL);
if (!pll_clock) {
pr_err("%s: failed to alloc memory", clk_name);
return;
}
pll_clock->sckcr = of_iomap(node, 0);
if (pll_clock->sckcr == NULL) {
pr_err("%s: failed to map divide register", clk_name);
goto free_clock;
}
pll_clock->pllcr = of_iomap(node, 1);
if (pll_clock->pllcr == NULL) {
pr_err("%s: failed to map multiply register", clk_name);
goto unmap_sckcr;
}
parent_name = of_clk_get_parent_name(node, 0);
init.name = clk_name;
init.ops = &pll_ops;
init.flags = CLK_IS_BASIC;
init.parent_names = &parent_name;
init.num_parents = 1;
pll_clock->hw.init = &init;
clk = clk_register(NULL, &pll_clock->hw);
if (IS_ERR(clk)) {
pr_err("%s: failed to register %s div clock (%ld)\n",
__func__, clk_name, PTR_ERR(clk));
goto unmap_pllcr;
}
of_clk_add_provider(node, of_clk_src_simple_get, clk);
return;
unmap_pllcr:
iounmap(pll_clock->pllcr);
unmap_sckcr:
iounmap(pll_clock->sckcr);
free_clock:
kfree(pll_clock);
}
static void __init of_dra7_apll_setup(struct device_node *node)
{
struct dpll_data *ad = NULL;
struct clk_hw_omap *clk_hw = NULL;
struct clk_init_data *init = NULL;
const char **parent_names = NULL;
int i;
ad = kzalloc(sizeof(*ad), GFP_KERNEL);
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
init = kzalloc(sizeof(*init), GFP_KERNEL);
if (!ad || !clk_hw || !init)
goto cleanup;
clk_hw->dpll_data = ad;
clk_hw->hw.init = init;
clk_hw->flags = MEMMAP_ADDRESSING;
init->name = node->name;
init->ops = &apll_ck_ops;
init->num_parents = of_clk_get_parent_count(node);
if (init->num_parents < 1) {
pr_err("dra7 apll %s must have parent(s)\n", node->name);
goto cleanup;
}
parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL);
if (!parent_names)
goto cleanup;
for (i = 0; i < init->num_parents; i++)
parent_names[i] = of_clk_get_parent_name(node, i);
init->parent_names = parent_names;
ad->control_reg = ti_clk_get_reg_addr(node, 0);
ad->idlest_reg = ti_clk_get_reg_addr(node, 1);
if (!ad->control_reg || !ad->idlest_reg)
goto cleanup;
ad->idlest_mask = 0x1;
ad->enable_mask = 0x3;
omap_clk_register_apll(&clk_hw->hw, node);
return;
cleanup:
kfree(parent_names);
kfree(ad);
kfree(clk_hw);
kfree(init);
}
static void __init of_dra7_atl_clock_setup(struct device_node *node)
{
struct dra7_atl_desc *clk_hw = NULL;
struct clk_init_data init = { NULL };
const char **parent_names = NULL;
struct clk *clk;
int ret;
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
if (!clk_hw) {
pr_err("%s: could not allocate dra7_atl_desc\n", __func__);
return;
}
clk_hw->hw.init = &init;
clk_hw->divider = 1;
init.name = node->name;
init.ops = &atl_clk_ops;
init.flags = CLK_IGNORE_UNUSED;
init.num_parents = of_clk_get_parent_count(node);
if (init.num_parents != 1) {
pr_err("%s: atl clock %s must have 1 parent\n", __func__,
node->name);
goto cleanup;
}
parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
if (!parent_names)
goto cleanup;
parent_names[0] = of_clk_get_parent_name(node, 0);
init.parent_names = parent_names;
clk = ti_clk_register(NULL, &clk_hw->hw, node->name);
if (!IS_ERR(clk)) {
ret = ti_clk_add_alias(NULL, clk, node->name);
if (ret) {
clk_unregister(clk);
goto cleanup;
}
of_clk_add_provider(node, of_clk_src_simple_get, clk);
kfree(parent_names);
return;
}
cleanup:
kfree(parent_names);
kfree(clk_hw);
}
void __init of_sama5d2_clk_generated_setup(struct device_node *np)
{
int num;
u32 id;
const char *name;
struct clk *clk;
unsigned int num_parents;
const char *parent_names[GENERATED_SOURCE_MAX];
struct device_node *gcknp;
struct clk_range range = CLK_RANGE(0, 0);
struct regmap *regmap;
num_parents = of_clk_get_parent_count(np);
if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
return;
of_clk_parent_fill(np, parent_names, num_parents);
num = of_get_child_count(np);
if (!num || num > PERIPHERAL_MAX)
return;
regmap = syscon_node_to_regmap(of_get_parent(np));
if (IS_ERR(regmap))
return;
for_each_child_of_node(np, gcknp) {
if (of_property_read_u32(gcknp, "reg", &id))
continue;
if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX)
continue;
if (of_property_read_string(np, "clock-output-names", &name))
name = gcknp->name;
of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
&range);
clk = at91_clk_register_generated(regmap, &pmc_pcr_lock, name,
parent_names, num_parents,
id, &range);
if (IS_ERR(clk))
continue;
of_clk_add_provider(gcknp, of_clk_src_simple_get, clk);
}
}
static const char ** __init clkgen_mux_get_parents(struct device_node *np,
int *num_parents)
{
const char **parents;
int nparents;
nparents = of_clk_get_parent_count(np);
if (WARN_ON(nparents <= 0))
return ERR_PTR(-EINVAL);
parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
if (!parents)
return ERR_PTR(-ENOMEM);
*num_parents = of_clk_parent_fill(np, parents, nparents);
return parents;
}
static const char ** __init flexgen_get_parents(struct device_node *np,
int *num_parents)
{
const char **parents;
unsigned int nparents;
nparents = of_clk_get_parent_count(np);
if (WARN_ON(!nparents))
return NULL;
parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
if (!parents)
return NULL;
*num_parents = of_clk_parent_fill(np, parents, nparents);
return parents;
}
static const char ** __init flexgen_get_parents(struct device_node *np,
int *num_parents)
{
const char **parents;
int nparents, i;
nparents = of_clk_get_parent_count(np);
if (WARN_ON(nparents <= 0))
return NULL;
parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
if (!parents)
return NULL;
for (i = 0; i < nparents; i++)
parents[i] = of_clk_get_parent_name(np, i);
*num_parents = nparents;
return parents;
}
static void __init _of_ti_gate_clk_setup(struct device_node *node,
const struct clk_ops *ops,
const struct clk_hw_omap_ops *hw_ops)
{
struct clk *clk;
const char *parent_name;
void __iomem *reg = NULL;
u8 enable_bit = 0;
u32 val;
u32 flags = 0;
u8 clk_gate_flags = 0;
if (ops != &omap_gate_clkdm_clk_ops) {
reg = ti_clk_get_reg_addr(node, 0);
if (IS_ERR(reg))
return;
if (!of_property_read_u32(node, "ti,bit-shift", &val))
enable_bit = val;
}
if (of_clk_get_parent_count(node) != 1) {
pr_err("%s must have 1 parent\n", node->name);
return;
}
parent_name = of_clk_get_parent_name(node, 0);
if (of_property_read_bool(node, "ti,set-rate-parent"))
flags |= CLK_SET_RATE_PARENT;
if (of_property_read_bool(node, "ti,set-bit-to-disable"))
clk_gate_flags |= INVERT_ENABLE;
clk = _register_gate(NULL, node->name, parent_name, flags, reg,
enable_bit, clk_gate_flags, ops, hw_ops);
if (!IS_ERR(clk))
of_clk_add_provider(node, of_clk_src_simple_get, clk);
}
static int ti_adpll_init_inputs(struct ti_adpll_data *d)
{
const char *error = "need at least %i inputs";
struct clk *clock;
int nr_inputs;
nr_inputs = of_clk_get_parent_count(d->np);
if (nr_inputs < d->c->nr_max_inputs) {
dev_err(d->dev, error, nr_inputs);
return -EINVAL;
}
of_clk_parent_fill(d->np, d->parent_names, nr_inputs);
clock = devm_clk_get(d->dev, d->parent_names[0]);
if (IS_ERR(clock)) {
dev_err(d->dev, "could not get clkinp\n");
return PTR_ERR(clock);
}
d->parent_clocks[TI_ADPLL_CLKINP] = clock;
clock = devm_clk_get(d->dev, d->parent_names[1]);
if (IS_ERR(clock)) {
dev_err(d->dev, "could not get clkinpulow clock\n");
return PTR_ERR(clock);
}
d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock;
if (d->c->is_type_s) {
clock = devm_clk_get(d->dev, d->parent_names[2]);
if (IS_ERR(clock)) {
dev_err(d->dev, "could not get clkinphif clock\n");
return PTR_ERR(clock);
}
d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock;
}
return 0;
}
void __init of_at91sam9260_clk_slow_setup(struct device_node *np,
struct at91_pmc *pmc)
{
struct clk *clk;
const char *parent_names[2];
int num_parents;
const char *name = np->name;
num_parents = of_clk_get_parent_count(np);
if (num_parents != 2)
return;
of_clk_parent_fill(np, parent_names, num_parents);
of_property_read_string(np, "clock-output-names", &name);
clk = at91_clk_register_sam9260_slow(pmc, name, parent_names,
num_parents);
if (IS_ERR(clk))
return;
of_clk_add_provider(np, of_clk_src_simple_get, clk);
}
static void __init h8300_div_clk_setup(struct device_node *node)
{
unsigned int num_parents;
struct clk *clk;
const char *clk_name = node->name;
const char *parent_name;
void __iomem *divcr = NULL;
int width;
num_parents = of_clk_get_parent_count(node);
if (num_parents < 1) {
pr_err("%s: no parent found", clk_name);
return;
}
divcr = of_iomap(node, 0);
if (divcr == NULL) {
pr_err("%s: failed to map divide register", clk_name);
goto error;
}
parent_name = of_clk_get_parent_name(node, 0);
of_property_read_u32(node, "renesas,width", &width);
clk = clk_register_divider(NULL, clk_name, parent_name,
CLK_SET_RATE_GATE, divcr, 0, width,
CLK_DIVIDER_POWER_OF_TWO, &clklock);
if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
return;
}
pr_err("%s: failed to register %s div clock (%ld)\n",
__func__, clk_name, PTR_ERR(clk));
error:
if (divcr)
iounmap(divcr);
}
static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
struct device_node *node)
{
const struct rockchip_domain_info *pd_info;
struct rockchip_pm_domain *pd;
struct device_node *qos_node;
int i, j;
u32 id;
int error;
error = of_property_read_u32(node, "reg", &id);
if (error) {
dev_err(pmu->dev,
"%s: failed to retrieve domain id (reg): %d\n",
node->name, error);
return -EINVAL;
}
if (id >= pmu->info->num_domains) {
dev_err(pmu->dev, "%s: invalid domain id %d\n",
node->name, id);
return -EINVAL;
}
pd_info = &pmu->info->domain_info[id];
if (!pd_info) {
dev_err(pmu->dev, "%s: undefined domain id %d\n",
node->name, id);
return -EINVAL;
}
pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL);
if (!pd)
return -ENOMEM;
pd->info = pd_info;
pd->pmu = pmu;
pd->num_clks = of_clk_get_parent_count(node);
if (pd->num_clks > 0) {
pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
sizeof(*pd->clks), GFP_KERNEL);
if (!pd->clks)
return -ENOMEM;
} else {
dev_dbg(pmu->dev, "%s: doesn't have clocks: %d\n",
node->name, pd->num_clks);
pd->num_clks = 0;
}
for (i = 0; i < pd->num_clks; i++) {
pd->clks[i].clk = of_clk_get(node, i);
if (IS_ERR(pd->clks[i].clk)) {
error = PTR_ERR(pd->clks[i].clk);
dev_err(pmu->dev,
"%s: failed to get clk at index %d: %d\n",
node->name, i, error);
return error;
}
}
error = clk_bulk_prepare(pd->num_clks, pd->clks);
if (error)
goto err_put_clocks;
pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
NULL);
if (pd->num_qos > 0) {
pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
sizeof(*pd->qos_regmap),
GFP_KERNEL);
if (!pd->qos_regmap) {
error = -ENOMEM;
goto err_unprepare_clocks;
}
for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
pd->num_qos,
sizeof(u32),
GFP_KERNEL);
if (!pd->qos_save_regs[j]) {
error = -ENOMEM;
goto err_unprepare_clocks;
}
}
for (j = 0; j < pd->num_qos; j++) {
qos_node = of_parse_phandle(node, "pm_qos", j);
if (!qos_node) {
error = -ENODEV;
goto err_unprepare_clocks;
}
pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
if (IS_ERR(pd->qos_regmap[j])) {
error = -ENODEV;
of_node_put(qos_node);
goto err_unprepare_clocks;
}
of_node_put(qos_node);
}
}
error = rockchip_pd_power(pd, true);
if (error) {
dev_err(pmu->dev,
"failed to power on domain '%s': %d\n",
node->name, error);
goto err_unprepare_clocks;
}
pd->genpd.name = node->name;
pd->genpd.power_off = rockchip_pd_power_off;
pd->genpd.power_on = rockchip_pd_power_on;
pd->genpd.attach_dev = rockchip_pd_attach_dev;
pd->genpd.detach_dev = rockchip_pd_detach_dev;
pd->genpd.flags = GENPD_FLAG_PM_CLK;
if (pd_info->active_wakeup)
pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
pm_genpd_init(&pd->genpd, NULL, false);
pmu->genpd_data.domains[id] = &pd->genpd;
return 0;
err_unprepare_clocks:
clk_bulk_unprepare(pd->num_clks, pd->clks);
err_put_clocks:
clk_bulk_put(pd->num_clks, pd->clks);
return error;
}
static void __init sun8i_a23_mbus_setup(struct device_node *node)
{
int num_parents = of_clk_get_parent_count(node);
const char **parents;
const char *clk_name = node->name;
struct resource res;
struct clk_divider *div;
struct clk_gate *gate;
struct clk_mux *mux;
struct clk *clk;
void __iomem *reg;
int err;
parents = kcalloc(num_parents, sizeof(*parents), GFP_KERNEL);
if (!parents)
return;
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
pr_err("Could not get registers for sun8i-mbus-clk\n");
goto err_free_parents;
}
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
goto err_unmap;
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux)
goto err_free_div;
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate)
goto err_free_mux;
of_property_read_string(node, "clock-output-names", &clk_name);
of_clk_parent_fill(node, parents, num_parents);
gate->reg = reg;
gate->bit_idx = SUN8I_MBUS_ENABLE;
gate->lock = &sun8i_a23_mbus_lock;
div->reg = reg;
div->shift = SUN8I_MBUS_DIV_SHIFT;
div->width = SUN8I_MBUS_DIV_WIDTH;
div->lock = &sun8i_a23_mbus_lock;
mux->reg = reg;
mux->shift = SUN8I_MBUS_MUX_SHIFT;
mux->mask = SUN8I_MBUS_MUX_MASK;
mux->lock = &sun8i_a23_mbus_lock;
clk = clk_register_composite(NULL, clk_name, parents, num_parents,
&mux->hw, &clk_mux_ops,
&div->hw, &clk_divider_ops,
&gate->hw, &clk_gate_ops,
0);
if (IS_ERR(clk))
goto err_free_gate;
err = of_clk_add_provider(node, of_clk_src_simple_get, clk);
if (err)
goto err_unregister_clk;
kfree(parents); /* parents is deep copied */
/* The MBUS clocks needs to be always enabled */
__clk_get(clk);
clk_prepare_enable(clk);
return;
err_unregister_clk:
/* TODO: The composite clock stuff will leak a bit here. */
clk_unregister(clk);
err_free_gate:
kfree(gate);
err_free_mux:
kfree(mux);
err_free_div:
kfree(div);
err_unmap:
iounmap(reg);
of_address_to_resource(node, 0, &res);
release_mem_region(res.start, resource_size(&res));
err_free_parents:
kfree(parents);
}
void __init of_dra7_apll_setup(struct device_node *node)
{
const struct clk_ops *ops;
struct clk *clk;
const char *clk_name = node->name;
int num_parents;
const char **parent_names = NULL;
u8 apll_flags = 0;
struct dpll_data *ad;
u32 idlest_mask = 0x1;
u32 autoidle_mask = 0x3;
int i;
ops = &apll_ck_ops;
ad = kzalloc(sizeof(*ad), GFP_KERNEL);
if (!ad) {
pr_err("%s: could not allocate dpll_data\n", __func__);
return;
}
of_property_read_string(node, "clock-output-names", &clk_name);
num_parents = of_clk_get_parent_count(node);
if (num_parents < 1) {
pr_err("%s: omap dpll %s must have parent(s)\n",
__func__, node->name);
goto cleanup;
}
parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
for (i = 0; i < num_parents; i++)
parent_names[i] = of_clk_get_parent_name(node, i);
ad->clk_ref = of_clk_get(node, 0);
ad->clk_bypass = of_clk_get(node, 1);
if (IS_ERR(ad->clk_ref)) {
pr_err("%s: ti,clk-ref for %s not found\n", __func__,
clk_name);
goto cleanup;
}
if (IS_ERR(ad->clk_bypass)) {
pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
clk_name);
goto cleanup;
}
i = of_property_match_string(node, "reg-names", "control");
if (i >= 0)
ad->control_reg = of_iomap(node, i);
i = of_property_match_string(node, "reg-names", "idlest");
if (i >= 0)
ad->idlest_reg = of_iomap(node, i);
ad->idlest_mask = idlest_mask;
ad->enable_mask = autoidle_mask;
clk = omap_clk_register_apll(NULL, clk_name, parent_names,
num_parents, apll_flags, ad,
NULL, ops);
if (!IS_ERR(clk))
of_clk_add_provider(node, of_clk_src_simple_get, clk);
return;
cleanup:
kfree(parent_names);
kfree(ad);
return;
}
/**
* of_ti_dpll_setup - Setup function for OMAP DPLL clocks
* @node: device node containing the DPLL info
* @ops: ops for the DPLL
* @ddt: DPLL data template to use
* @init_flags: flags for controlling init types
*
* Initializes a DPLL clock from device tree data.
*/
static void __init of_ti_dpll_setup(struct device_node *node,
const struct clk_ops *ops,
const struct dpll_data *ddt,
u8 init_flags)
{
struct clk_hw_omap *clk_hw = NULL;
struct clk_init_data *init = NULL;
const char **parent_names = NULL;
struct dpll_data *dd = NULL;
int i;
u8 dpll_mode = 0;
dd = kzalloc(sizeof(*dd), GFP_KERNEL);
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
init = kzalloc(sizeof(*init), GFP_KERNEL);
if (!dd || !clk_hw || !init)
goto cleanup;
memcpy(dd, ddt, sizeof(*dd));
clk_hw->dpll_data = dd;
clk_hw->ops = &clkhwops_omap3_dpll;
clk_hw->hw.init = init;
clk_hw->flags = MEMMAP_ADDRESSING;
init->name = node->name;
init->ops = ops;
init->num_parents = of_clk_get_parent_count(node);
if (init->num_parents < 1) {
pr_err("%s must have parent(s)\n", node->name);
goto cleanup;
}
parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL);
if (!parent_names)
goto cleanup;
for (i = 0; i < init->num_parents; i++)
parent_names[i] = of_clk_get_parent_name(node, i);
init->parent_names = parent_names;
dd->control_reg = ti_clk_get_reg_addr(node, 0);
dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
if (!dd->control_reg || !dd->idlest_reg || !dd->mult_div1_reg)
goto cleanup;
if (init_flags & DPLL_HAS_AUTOIDLE) {
dd->autoidle_reg = ti_clk_get_reg_addr(node, 3);
if (!dd->autoidle_reg)
goto cleanup;
}
if (of_property_read_bool(node, "ti,low-power-stop"))
dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
if (of_property_read_bool(node, "ti,low-power-bypass"))
dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
if (of_property_read_bool(node, "ti,lock"))
dpll_mode |= 1 << DPLL_LOCKED;
if (dpll_mode)
dd->modes = dpll_mode;
ti_clk_register_dpll(&clk_hw->hw, node);
return;
cleanup:
kfree(dd);
kfree(parent_names);
kfree(init);
kfree(clk_hw);
}
static void __init of_omap2_apll_setup(struct device_node *node)
{
struct dpll_data *ad = NULL;
struct clk_hw_omap *clk_hw = NULL;
struct clk_init_data *init = NULL;
struct clk *clk;
const char *parent_name;
u32 val;
ad = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
init = kzalloc(sizeof(*init), GFP_KERNEL);
if (!ad || !clk_hw || !init)
goto cleanup;
clk_hw->dpll_data = ad;
clk_hw->hw.init = init;
init->ops = &omap2_apll_ops;
init->name = node->name;
clk_hw->ops = &omap2_apll_hwops;
init->num_parents = of_clk_get_parent_count(node);
if (init->num_parents != 1) {
pr_err("%s must have one parent\n", node->name);
goto cleanup;
}
parent_name = of_clk_get_parent_name(node, 0);
init->parent_names = &parent_name;
if (of_property_read_u32(node, "ti,clock-frequency", &val)) {
pr_err("%s missing clock-frequency\n", node->name);
goto cleanup;
}
clk_hw->fixed_rate = val;
if (of_property_read_u32(node, "ti,bit-shift", &val)) {
pr_err("%s missing bit-shift\n", node->name);
goto cleanup;
}
clk_hw->enable_bit = val;
ad->enable_mask = 0x3 << val;
ad->autoidle_mask = 0x3 << val;
if (of_property_read_u32(node, "ti,idlest-shift", &val)) {
pr_err("%s missing idlest-shift\n", node->name);
goto cleanup;
}
ad->idlest_mask = 1 << val;
ad->control_reg = ti_clk_get_reg_addr(node, 0);
ad->autoidle_reg = ti_clk_get_reg_addr(node, 1);
ad->idlest_reg = ti_clk_get_reg_addr(node, 2);
if (!ad->control_reg || !ad->autoidle_reg || !ad->idlest_reg)
goto cleanup;
clk = clk_register(NULL, &clk_hw->hw);
if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
kfree(init);
return;
}
cleanup:
kfree(ad);
kfree(clk_hw);
kfree(init);
}
static int dwc3_of_simple_probe(struct platform_device *pdev)
{
struct dwc3_of_simple *simple;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
unsigned int count;
int ret;
int i;
simple = devm_kzalloc(dev, sizeof(*simple), GFP_KERNEL);
if (!simple)
return -ENOMEM;
count = of_clk_get_parent_count(np);
if (!count)
return -ENOENT;
simple->num_clocks = count;
simple->clks = devm_kcalloc(dev, simple->num_clocks,
sizeof(struct clk *), GFP_KERNEL);
if (!simple->clks)
return -ENOMEM;
simple->dev = dev;
for (i = 0; i < simple->num_clocks; i++) {
struct clk *clk;
clk = of_clk_get(np, i);
if (IS_ERR(clk)) {
while (--i >= 0)
clk_put(simple->clks[i]);
return PTR_ERR(clk);
}
ret = clk_prepare_enable(clk);
if (ret < 0) {
while (--i >= 0) {
clk_disable_unprepare(simple->clks[i]);
clk_put(simple->clks[i]);
}
clk_put(clk);
return ret;
}
simple->clks[i] = clk;
}
ret = of_platform_populate(np, NULL, NULL, dev);
if (ret) {
for (i = 0; i < simple->num_clocks; i++) {
clk_disable_unprepare(simple->clks[i]);
clk_put(simple->clks[i]);
}
return ret;
}
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
return 0;
}
/**
* of_ti_dpll_setup - Setup function for OMAP DPLL clocks
* @node: device node containing the DPLL info
* @ops: ops for the DPLL
* @ddt: DPLL data template to use
*
* Initializes a DPLL clock from device tree data.
*/
static void __init of_ti_dpll_setup(struct device_node *node,
const struct clk_ops *ops,
const struct dpll_data *ddt)
{
struct clk_hw_omap *clk_hw = NULL;
struct clk_init_data *init = NULL;
const char **parent_names = NULL;
struct dpll_data *dd = NULL;
int i;
u8 dpll_mode = 0;
dd = kzalloc(sizeof(*dd), GFP_KERNEL);
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
init = kzalloc(sizeof(*init), GFP_KERNEL);
if (!dd || !clk_hw || !init)
goto cleanup;
memcpy(dd, ddt, sizeof(*dd));
clk_hw->dpll_data = dd;
clk_hw->ops = &clkhwops_omap3_dpll;
clk_hw->hw.init = init;
clk_hw->flags = MEMMAP_ADDRESSING;
init->name = node->name;
init->ops = ops;
init->num_parents = of_clk_get_parent_count(node);
if (init->num_parents < 1) {
pr_err("%s must have parent(s)\n", node->name);
goto cleanup;
}
parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL);
if (!parent_names)
goto cleanup;
for (i = 0; i < init->num_parents; i++)
parent_names[i] = of_clk_get_parent_name(node, i);
init->parent_names = parent_names;
dd->control_reg = ti_clk_get_reg_addr(node, 0);
/*
* Special case for OMAP2 DPLL, register order is different due to
* missing idlest_reg, also clkhwops is different. Detected from
* missing idlest_mask.
*/
if (!dd->idlest_mask) {
dd->mult_div1_reg = ti_clk_get_reg_addr(node, 1);
#ifdef CONFIG_ARCH_OMAP2
clk_hw->ops = &clkhwops_omap2xxx_dpll;
omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
#endif
} else {
dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
if (IS_ERR(dd->idlest_reg))
goto cleanup;
dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
}
if (IS_ERR(dd->control_reg) || IS_ERR(dd->mult_div1_reg))
goto cleanup;
if (dd->autoidle_mask) {
dd->autoidle_reg = ti_clk_get_reg_addr(node, 3);
if (IS_ERR(dd->autoidle_reg))
goto cleanup;
}
if (of_property_read_bool(node, "ti,low-power-stop"))
dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
if (of_property_read_bool(node, "ti,low-power-bypass"))
dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
if (of_property_read_bool(node, "ti,lock"))
dpll_mode |= 1 << DPLL_LOCKED;
omap2_init_dpll_clkdm(dd, node);
if (dpll_mode)
dd->modes = dpll_mode;
_register_dpll(&clk_hw->hw, node);
return;
cleanup:
kfree(dd);
kfree(parent_names);
kfree(init);
kfree(clk_hw);
}