static void __init sun4i_mod1_clk_setup(struct device_node *node)
{
struct clk *clk;
struct clk_mux *mux;
struct clk_gate *gate;
const char *parents[4];
const char *clk_name = node->name;
void __iomem *reg;
int i;
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg))
return;
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux)
goto err_unmap;
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate)
goto err_free_mux;
of_property_read_string(node, "clock-output-names", &clk_name);
i = of_clk_parent_fill(node, parents, SUN4I_MOD1_MAX_PARENTS);
gate->reg = reg;
gate->bit_idx = SUN4I_MOD1_ENABLE;
gate->lock = &mod1_lock;
mux->reg = reg;
mux->shift = SUN4I_MOD1_MUX;
mux->mask = BIT(SUN4I_MOD1_MUX_WIDTH) - 1;
mux->lock = &mod1_lock;
clk = clk_register_composite(NULL, clk_name, parents, i,
&mux->hw, &clk_mux_ops,
NULL, NULL,
&gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT);
if (IS_ERR(clk))
goto err_free_gate;
of_clk_add_provider(node, of_clk_src_simple_get, clk);
return;
err_free_gate:
kfree(gate);
err_free_mux:
kfree(mux);
err_unmap:
iounmap(reg);
}
void __init of_sama5d2_clk_generated_setup(struct device_node *np)
{
int num;
u32 id;
const char *name;
struct clk *clk;
unsigned int num_parents;
const char *parent_names[GENERATED_SOURCE_MAX];
struct device_node *gcknp;
struct clk_range range = CLK_RANGE(0, 0);
struct regmap *regmap;
num_parents = of_clk_get_parent_count(np);
if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
return;
of_clk_parent_fill(np, parent_names, num_parents);
num = of_get_child_count(np);
if (!num || num > PERIPHERAL_MAX)
return;
regmap = syscon_node_to_regmap(of_get_parent(np));
if (IS_ERR(regmap))
return;
for_each_child_of_node(np, gcknp) {
if (of_property_read_u32(gcknp, "reg", &id))
continue;
if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX)
continue;
if (of_property_read_string(np, "clock-output-names", &name))
name = gcknp->name;
of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
&range);
clk = at91_clk_register_generated(regmap, &pmc_pcr_lock, name,
parent_names, num_parents,
id, &range);
if (IS_ERR(clk))
continue;
of_clk_add_provider(gcknp, of_clk_src_simple_get, clk);
}
}
static __init struct clk *__socfpga_pll_init(struct device_node *node,
const struct clk_ops *ops)
{
u32 reg;
struct clk *clk;
struct socfpga_pll *pll_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
struct device_node *clkmgr_np;
int rc;
of_property_read_u32(node, "reg", ®);
pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
if (WARN_ON(!pll_clk))
return NULL;
clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
clk_mgr_base_addr = of_iomap(clkmgr_np, 0);
BUG_ON(!clk_mgr_base_addr);
pll_clk->hw.reg = clk_mgr_base_addr + reg;
of_property_read_string(node, "clock-output-names", &clk_name);
init.name = clk_name;
init.ops = ops;
init.flags = 0;
init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
init.parent_names = parent_name;
pll_clk->hw.hw.init = &init;
pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
pax_open_kernel();
*(void **)&clk_pll_ops.enable = clk_gate_ops.enable;
*(void **)&clk_pll_ops.disable = clk_gate_ops.disable;
pax_close_kernel();
clk = clk_register(NULL, &pll_clk->hw.hw);
if (WARN_ON(IS_ERR(clk))) {
kfree(pll_clk);
return NULL;
}
rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
return clk;
}
static const char ** __init clkgen_mux_get_parents(struct device_node *np,
int *num_parents)
{
const char **parents;
int nparents;
nparents = of_clk_get_parent_count(np);
if (WARN_ON(nparents <= 0))
return ERR_PTR(-EINVAL);
parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
if (!parents)
return ERR_PTR(-ENOMEM);
*num_parents = of_clk_parent_fill(np, parents, nparents);
return parents;
}
static const char ** __init flexgen_get_parents(struct device_node *np,
int *num_parents)
{
const char **parents;
unsigned int nparents;
nparents = of_clk_get_parent_count(np);
if (WARN_ON(!nparents))
return NULL;
parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
if (!parents)
return NULL;
*num_parents = of_clk_parent_fill(np, parents, nparents);
return parents;
}
static int ti_adpll_init_inputs(struct ti_adpll_data *d)
{
const char *error = "need at least %i inputs";
struct clk *clock;
int nr_inputs;
nr_inputs = of_clk_get_parent_count(d->np);
if (nr_inputs < d->c->nr_max_inputs) {
dev_err(d->dev, error, nr_inputs);
return -EINVAL;
}
of_clk_parent_fill(d->np, d->parent_names, nr_inputs);
clock = devm_clk_get(d->dev, d->parent_names[0]);
if (IS_ERR(clock)) {
dev_err(d->dev, "could not get clkinp\n");
return PTR_ERR(clock);
}
d->parent_clocks[TI_ADPLL_CLKINP] = clock;
clock = devm_clk_get(d->dev, d->parent_names[1]);
if (IS_ERR(clock)) {
dev_err(d->dev, "could not get clkinpulow clock\n");
return PTR_ERR(clock);
}
d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock;
if (d->c->is_type_s) {
clock = devm_clk_get(d->dev, d->parent_names[2]);
if (IS_ERR(clock)) {
dev_err(d->dev, "could not get clkinphif clock\n");
return PTR_ERR(clock);
}
d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock;
}
return 0;
}
void __init of_at91sam9260_clk_slow_setup(struct device_node *np,
struct at91_pmc *pmc)
{
struct clk *clk;
const char *parent_names[2];
int num_parents;
const char *name = np->name;
num_parents = of_clk_get_parent_count(np);
if (num_parents != 2)
return;
of_clk_parent_fill(np, parent_names, num_parents);
of_property_read_string(np, "clock-output-names", &name);
clk = at91_clk_register_sam9260_slow(pmc, name, parent_names,
num_parents);
if (IS_ERR(clk))
return;
of_clk_add_provider(np, of_clk_src_simple_get, clk);
}
/**
* of_ti_dpll_setup - Setup function for OMAP DPLL clocks
* @node: device node containing the DPLL info
* @ops: ops for the DPLL
* @ddt: DPLL data template to use
*
* Initializes a DPLL clock from device tree data.
*/
static void __init of_ti_dpll_setup(struct device_node *node,
const struct clk_ops *ops,
const struct dpll_data *ddt)
{
struct clk_hw_omap *clk_hw = NULL;
struct clk_init_data *init = NULL;
const char **parent_names = NULL;
struct dpll_data *dd = NULL;
u8 dpll_mode = 0;
dd = kzalloc(sizeof(*dd), GFP_KERNEL);
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
init = kzalloc(sizeof(*init), GFP_KERNEL);
if (!dd || !clk_hw || !init)
goto cleanup;
memcpy(dd, ddt, sizeof(*dd));
clk_hw->dpll_data = dd;
clk_hw->ops = &clkhwops_omap3_dpll;
clk_hw->hw.init = init;
clk_hw->flags = MEMMAP_ADDRESSING;
init->name = node->name;
init->ops = ops;
init->num_parents = of_clk_get_parent_count(node);
if (init->num_parents < 1) {
pr_err("%s must have parent(s)\n", node->name);
goto cleanup;
}
parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL);
if (!parent_names)
goto cleanup;
of_clk_parent_fill(node, parent_names, init->num_parents);
init->parent_names = parent_names;
dd->control_reg = ti_clk_get_reg_addr(node, 0);
/*
* Special case for OMAP2 DPLL, register order is different due to
* missing idlest_reg, also clkhwops is different. Detected from
* missing idlest_mask.
*/
if (!dd->idlest_mask) {
dd->mult_div1_reg = ti_clk_get_reg_addr(node, 1);
#ifdef CONFIG_ARCH_OMAP2
clk_hw->ops = &clkhwops_omap2xxx_dpll;
omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
#endif
} else {
dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
if (IS_ERR(dd->idlest_reg))
goto cleanup;
dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
}
if (IS_ERR(dd->control_reg) || IS_ERR(dd->mult_div1_reg))
goto cleanup;
if (dd->autoidle_mask) {
dd->autoidle_reg = ti_clk_get_reg_addr(node, 3);
if (IS_ERR(dd->autoidle_reg))
goto cleanup;
}
if (of_property_read_bool(node, "ti,low-power-stop"))
dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
if (of_property_read_bool(node, "ti,low-power-bypass"))
dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
if (of_property_read_bool(node, "ti,lock"))
dpll_mode |= 1 << DPLL_LOCKED;
if (dpll_mode)
dd->modes = dpll_mode;
_register_dpll(&clk_hw->hw, node);
return;
cleanup:
kfree(dd);
kfree(parent_names);
kfree(init);
kfree(clk_hw);
}
static void __init sun8i_a23_mbus_setup(struct device_node *node)
{
int num_parents = of_clk_get_parent_count(node);
const char **parents;
const char *clk_name = node->name;
struct resource res;
struct clk_divider *div;
struct clk_gate *gate;
struct clk_mux *mux;
struct clk *clk;
void __iomem *reg;
int err;
parents = kcalloc(num_parents, sizeof(*parents), GFP_KERNEL);
if (!parents)
return;
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
pr_err("Could not get registers for sun8i-mbus-clk\n");
goto err_free_parents;
}
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
goto err_unmap;
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux)
goto err_free_div;
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate)
goto err_free_mux;
of_property_read_string(node, "clock-output-names", &clk_name);
of_clk_parent_fill(node, parents, num_parents);
gate->reg = reg;
gate->bit_idx = SUN8I_MBUS_ENABLE;
gate->lock = &sun8i_a23_mbus_lock;
div->reg = reg;
div->shift = SUN8I_MBUS_DIV_SHIFT;
div->width = SUN8I_MBUS_DIV_WIDTH;
div->lock = &sun8i_a23_mbus_lock;
mux->reg = reg;
mux->shift = SUN8I_MBUS_MUX_SHIFT;
mux->mask = SUN8I_MBUS_MUX_MASK;
mux->lock = &sun8i_a23_mbus_lock;
clk = clk_register_composite(NULL, clk_name, parents, num_parents,
&mux->hw, &clk_mux_ops,
&div->hw, &clk_divider_ops,
&gate->hw, &clk_gate_ops,
0);
if (IS_ERR(clk))
goto err_free_gate;
err = of_clk_add_provider(node, of_clk_src_simple_get, clk);
if (err)
goto err_unregister_clk;
kfree(parents); /* parents is deep copied */
/* The MBUS clocks needs to be always enabled */
__clk_get(clk);
clk_prepare_enable(clk);
return;
err_unregister_clk:
/* TODO: The composite clock stuff will leak a bit here. */
clk_unregister(clk);
err_free_gate:
kfree(gate);
err_free_mux:
kfree(mux);
err_free_div:
kfree(div);
err_unmap:
iounmap(reg);
of_address_to_resource(node, 0, &res);
release_mem_region(res.start, resource_size(&res));
err_free_parents:
kfree(parents);
}