static void start_hnp(struct ohci_hcd *ohci) { const unsigned port = ohci_to_hcd(ohci)->self.otg_port - 1; unsigned long flags; u32 l; otg_start_hnp(ohci->transceiver); local_irq_save(flags); ohci->transceiver->state = OTG_STATE_A_SUSPEND; writel (RH_PS_PSS, &ohci->regs->roothub.portstatus [port]); l = omap_readl(OTG_CTRL); l &= ~OTG_A_BUSREQ; omap_writel(l, OTG_CTRL); local_irq_restore(flags); }
static void __init omap_muxtbl_set_usbbx_gpio(struct omap_muxtbl *muxtbl) { unsigned int reg_base; unsigned int reg_val; unsigned int shift; unsigned int cfg_val; unsigned int mux_val; /* not a gpio mode */ if (likely((muxtbl->mux.value & OMAP_MUX_MODE7) != OMAP_MUX_MODE3)) return; switch (muxtbl->gpio.gpio) { case 96: /* usbb1_hsic_data */ shift = OMAP4_USBB1_HSIC_DATA_WD_SHIFT; break; case 97: /* usbb1_hsic_strobe */ shift = OMAP4_USBB1_HSIC_STROBE_WD_SHIFT; break; case 169: /* usbb2_hsic_data */ shift = OMAP4_USBB2_HSIC_DATA_WD_SHIFT; break; case 170: /* usbb2_hsic_strobe */ shift = OMAP4_USBB2_HSIC_STROBE_WD_SHIFT; break; default: return; } mux_val = muxtbl->mux.value; if ((mux_val & OMAP_PIN_INPUT_PULLUP) == OMAP_PIN_INPUT_PULLUP) cfg_val = 0x1; else if ((mux_val & OMAP_PIN_INPUT_PULLDOWN) == OMAP_PIN_INPUT_PULLDOWN) cfg_val = 0x2; else if ((mux_val & OMAP_PIN_INPUT) == OMAP_PIN_INPUT) cfg_val = 0x0; else cfg_val = 0x3; reg_base = OMAP4_CTRL_MODULE_PAD_CORE; reg_val = omap_readl(reg_base + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC); reg_val &= ~(0x3 << shift); reg_val |= cfg_val << shift; omap_writel(reg_val, reg_base + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC); }
static void __init h2_init(void) { /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped * to address 0 by a dip switch), NAND on CS2B. The NAND driver will * notice whether a NAND chip is enabled at probe time. * * FIXME revC boards (and H3) support NAND-boot, with a dip switch to * put NOR on CS2B and NAND (which on H2 may be 16bit) on CS3. Try * detecting that in code here, to avoid probing every possible flash * configuration... */ h2_nor_resource.end = h2_nor_resource.start = omap_cs3_phys(); h2_nor_resource.end += SZ_32M - 1; h2_nand_resource.end = h2_nand_resource.start = OMAP_CS2B_PHYS; h2_nand_resource.end += SZ_4K - 1; if (!(omap_request_gpio(H2_NAND_RB_GPIO_PIN))) h2_nand_data.dev_ready = h2_nand_dev_ready; omap_cfg_reg(L3_1610_FLASH_CS2B_OE); omap_cfg_reg(M8_1610_FLASH_CS2B_WE); /* MMC: card detect and WP */ /* omap_cfg_reg(U19_ARMIO1); */ /* CD */ omap_cfg_reg(BALLOUT_V8_ARMIO3); /* WP */ /* Irda */ #if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE) omap_writel(omap_readl(FUNC_MUX_CTRL_A) | 7, FUNC_MUX_CTRL_A); if (!(omap_request_gpio(H2_IRDA_FIRSEL_GPIO_PIN))) { omap_set_gpio_direction(H2_IRDA_FIRSEL_GPIO_PIN, 0); h2_irda_data.transceiver_mode = h2_transceiver_mode; } #endif platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices)); spi_register_board_info(h2_spi_board_info, ARRAY_SIZE(h2_spi_board_info)); omap_board_config = h2_config; omap_board_config_size = ARRAY_SIZE(h2_config); omap_serial_init(); omap_register_i2c_bus(1, 100, h2_i2c_board_info, ARRAY_SIZE(h2_i2c_board_info)); h2_mmc_init(); omap_register_gpio_switches(h2_gpio_switches, ARRAY_SIZE(h2_gpio_switches)); }
static inline void omap1_mmc_mux(struct omap_mmc_platform_data *mmc_controller, int controller_nr) { if (controller_nr == 0) { omap_cfg_reg(MMC_CMD); omap_cfg_reg(MMC_CLK); omap_cfg_reg(MMC_DAT0); if (cpu_is_omap1710()) { omap_cfg_reg(M15_1710_MMC_CLKI); omap_cfg_reg(P19_1710_MMC_CMDDIR); omap_cfg_reg(P20_1710_MMC_DATDIR0); } if (mmc_controller->slots[0].wires == 4) { omap_cfg_reg(MMC_DAT1); /* NOTE: DAT2 can be on W10 (here) or M15 */ if (!mmc_controller->slots[0].nomux) omap_cfg_reg(MMC_DAT2); omap_cfg_reg(MMC_DAT3); } } /* Block 2 is on newer chips, and has many pinout options */ if (cpu_is_omap16xx() && controller_nr == 1) { if (!mmc_controller->slots[1].nomux) { omap_cfg_reg(Y8_1610_MMC2_CMD); omap_cfg_reg(Y10_1610_MMC2_CLK); omap_cfg_reg(R18_1610_MMC2_CLKIN); omap_cfg_reg(W8_1610_MMC2_DAT0); if (mmc_controller->slots[1].wires == 4) { omap_cfg_reg(V8_1610_MMC2_DAT1); omap_cfg_reg(W15_1610_MMC2_DAT2); omap_cfg_reg(R10_1610_MMC2_DAT3); } /* These are needed for the level shifter */ omap_cfg_reg(V9_1610_MMC2_CMDDIR); omap_cfg_reg(V5_1610_MMC2_DATDIR0); omap_cfg_reg(W19_1610_MMC2_DATDIR1); } /* Feedback clock must be set on OMAP-1710 MMC2 */ if (cpu_is_omap1710()) omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24), MOD_CONF_CTRL_1); } }
static void __init omap4_muxtbl_set_pbias_gpio_post( struct omap_mux_partition *partition, struct omap_board_mux *mux) { unsigned int reg_val; const unsigned int pad_core_base = OMAP4_CTRL_MODULE_PAD_CORE; const unsigned int pad_wkup_base = OMAP4_CTRL_MODULE_PAD_WKUP; if (partition != wkup_part || omap4_muxtbl_is_pbias_gpio(mux)) return; reg_val = omap_readl(pad_core_base + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1); reg_val &= ~(OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK | OMAP4_USBC1_DR0_SPEEDCTRL_MASK); omap_writel(reg_val, pad_core_base + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1); reg_val = omap_readl(pad_wkup_base + OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO); reg_val &= ~(OMAP4_PAD_USIM_CLK_LOW_MASK | OMAP4_PAD_USIM_RST_LOW_MASK); omap_writel(reg_val, pad_wkup_base + OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO); reg_val = omap_readl(pad_core_base + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE); reg_val &= ~(OMAP4_USIM_PBIASLITE_VMODE_MASK | OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK); omap_writel(reg_val, pad_core_base + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE); reg_val = omap_readl(pad_core_base + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE); reg_val |= (OMAP4_USIM_PBIASLITE_PWRDNZ_MASK | OMAP4_USBC1_ICUSB_PWRDNZ_MASK); omap_writel(reg_val, pad_core_base + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE); reg_val = omap_readl(pad_wkup_base + OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO); reg_val |= OMAP4_USIM_PWRDNZ_MASK; omap_writel(reg_val, pad_wkup_base + OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO); reg_val = omap_readl(pad_core_base + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE); reg_val |= (OMAP4_USIM_PBIASLITE_PWRDNZ_MASK | OMAP4_USBC1_ICUSB_PWRDNZ_MASK); omap_writel(reg_val, pad_core_base + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE); }
static void tahvo_usb_become_peripheral(struct tahvo_usb *tu) { u32 l; /* Clear system and transceiver controlled bits * and enable ID to mark peripheral mode and * BSESSEND to mark no Vbus */ tahvo_otg_init(); l = omap_readl(OTG_CTRL); l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK | OTG_BSESSVLD); l |= OTG_ID | OTG_BSESSEND; omap_writel(l, OTG_CTRL); /* Power up transceiver and set it in USB perhiperal mode */ tahvo_write_reg(tu->dev, TAHVO_REG_USBR, USBR_SLAVE_CONTROL | USBR_REGOUT | USBR_NSUSPEND | USBR_SLAVE_SW); tu->otg.state = OTG_STATE_B_IDLE; check_vbus_state(tu); }
static void _set_timing(int div, int tw0, int tw1) { u32 l; #ifdef VERBOSE dev_dbg(sossi.fbdev->dev, "Using TW0 = %d, TW1 = %d, div = %d\n", tw0 + 1, tw1 + 1, div + 1); #endif l = omap_readl(MOD_CONF_CTRL_1); l &= ~(7 << 17); l |= div << 17; omap_writel(l, MOD_CONF_CTRL_1); l = sossi_read_reg(SOSSI_INIT1_REG); l &= ~((0x0f << 20) | (0x3f << 24)); l |= (tw0 << 20) | (tw1 << 24); sossi_write_reg(SOSSI_INIT1_REG, l); }
void __init usb_musb_init(void) { #ifdef CONFIG_USB_MUSB_SOC /* OMAP35x new EVM can source 500mA */ if (get_omap3evm_board_rev() >= OMAP3EVM_BOARD_GEN_2) musb_plat.power = 250; #ifdef CONFIG_NOP_USB_XCEIV nop_xceiv_register(); #endif if (platform_device_register(&musb_device) < 0) { printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); return; } #endif /* Enable smartidle on MUSB to improve C1 wakeup latency */ if (cpu_is_omap34xx()) omap_writel(AUTOIDLE, OTG_SYSCONFIG); }
/** * hp3a_histogram_isr - ISR for the histogram done interrupt. * * No return value. **/ static void hp3a_histogram_isr(unsigned long status, isp_vbq_callback_ptr arg1, void *arg2) { u32 *hist_buffer; u32 i; struct hp3a_internal_buffer *ibuffer = NULL; if (unlikely((HIST_DONE & status) != HIST_DONE)) { return; } omap_writel(omap_readl(ISPHIST_PCR) & ~(ISPHIST_PCR_EN), ISPHIST_PCR); if (unlikely(g_tc.v4l2_streaming == 0)) { return; } if (hp3a_dequeue(&g_tc.hist_hw_queue, &ibuffer) == 0) { /* If there is a buffer available then fill it. */ hist_buffer = (u32 *)phys_to_virt(page_to_phys(ibuffer->pages[0])); omap_writel((omap_readl(ISPHIST_CNT)) | \ ISPHIST_CNT_CLR_EN, ISPHIST_CNT); for (i = g_tc.hist_bin_size; i--;) { *hist_buffer = omap_readl(ISPHIST_DATA); ++hist_buffer; } omap_writel((omap_readl(ISPHIST_CNT)) & ~ISPHIST_CNT_CLR_EN, ISPHIST_CNT); } else { /* There are no buffers availavle so just clear internal histogram memory. */ for (i = g_tc.hist_bin_size; i--;) { omap_writel(0, ISPHIST_DATA); } } /* Set memory HW memory address and enable. */ omap_writel(0, ISPHIST_ADDR); if (g_tc.hist_hw_enable == 1) { /* Enable histogram. */ omap_writel(omap_readl(ISPHIST_PCR) | (ISPHIST_PCR_EN), ISPHIST_PCR); } g_tc.hist_done = 1; /* Release the tasks waiting for stats. */ wake_up(&g_tc.stats_done); }
static int tahvo_usb_set_host(struct otg_transceiver *otg, struct usb_bus *host) { struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg); u32 l; dev_dbg(&tu->pt_dev->dev, "set_host %p\n", host); if (otg == NULL) return -ENODEV; #if defined(CONFIG_USB_OTG) || !defined(CONFIG_USB_GADGET_OMAP) mutex_lock(&tu->serialize); if (host == NULL) { if (TAHVO_MODE(tu) == TAHVO_MODE_HOST) tahvo_usb_power_off(tu); tu->otg.host = NULL; mutex_unlock(&tu->serialize); return 0; } l = omap_readl(OTG_SYSCON_1); l &= ~(OTG_IDLE_EN | HST_IDLE_EN | DEV_IDLE_EN); omap_writel(l, OTG_SYSCON_1); if (TAHVO_MODE(tu) == TAHVO_MODE_HOST) { tu->otg.host = NULL; tahvo_usb_become_host(tu); } else host_suspend(tu); tu->otg.host = host; mutex_unlock(&tu->serialize); #else /* No host mode configured, so do not allow host controlled to be set */ return -EINVAL; #endif return 0; }
/* * omap16xx_gpio_init needs to be done before * machine_init functions access gpio APIs. * Hence omap16xx_gpio_init is a postcore_initcall. */ static int __init omap16xx_gpio_init(void) { int i; void __iomem *base; struct resource *res; struct platform_device *pdev; struct omap_gpio_platform_data *pdata; if (!cpu_is_omap16xx()) return -EINVAL; /* * Enable system clock for GPIO module. * The CAM_CLK_CTRL *is* really the right place. */ omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) { pdev = omap16xx_gpio_dev[i]; pdata = pdev->dev.platform_data; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (unlikely(!res)) { dev_err(&pdev->dev, "Invalid mem resource.\n"); return -ENODEV; } base = ioremap(res->start, resource_size(res)); if (unlikely(!base)) { dev_err(&pdev->dev, "ioremap failed.\n"); return -ENOMEM; } __raw_writel(SYSCONFIG_WORD, base + OMAP1610_GPIO_SYSCONFIG); iounmap(base); platform_device_register(omap16xx_gpio_dev[i]); } return 0; }
static void tahvo_usb_become_host(struct tahvo_usb *tu) { u32 l; /* Clear system and transceiver controlled bits * also mark the A-session is always valid */ tahvo_otg_init(); l = omap_readl(OTG_CTRL); l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK); l |= OTG_ASESSVLD; omap_writel(l, OTG_CTRL); /* Power up the transceiver in USB host mode */ tahvo_write_reg(tu->dev, TAHVO_REG_USBR, USBR_REGOUT | USBR_NSUSPEND | USBR_MASTER_SW2 | USBR_MASTER_SW1); tu->otg.state = OTG_STATE_A_IDLE; check_vbus_state(tu); }
static int tahvo_usb_start_srp(struct otg_transceiver *dev) { struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg); u32 otg_ctrl; dev_dbg(&tu->pt_dev->dev, "start_srp\n"); if (!dev || tu->otg.state != OTG_STATE_B_IDLE) return -ENODEV; otg_ctrl = omap_readl(OTG_CTRL); if (!(otg_ctrl & OTG_BSESSEND)) return -EINVAL; otg_ctrl |= OTG_B_BUSREQ; otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_SYS_MASK; omap_writel(otg_ctrl, OTG_CTRL); tu->otg.state = OTG_STATE_B_SRP_INIT; return 0; }
// This code is yanked from arch/arm/mach-omap2/prcm.c void machine_emergency_restart(void) { s16 prcm_offs; u32 l; // delay here to allow eMMC to finish any internal housekeeping before reset // even if mdelay fails to work correctly, 8 second button press should work // this used to be an msleep but scheduler is gone here and calling msleep // will cause a panic mdelay(1600); prcm_offs = OMAP3430_GR_MOD; l = ('B' << 24) | ('M' << 16) | 'h'; /* Reserve the first word in scratchpad for communicating * with the boot ROM. A pointer to a data structure * describing the boot process can be stored there, * cf. OMAP34xx TRM, Initialization / Software Booting * Configuration. */ omap_writel(l, OMAP343X_SCRATCHPAD + 4); omap3_configure_core_dpll_warmreset(); }
void musb_disable_idle(int on) { u32 reg; if (!cpu_is_omap34xx()) return; reg = omap_readl(OMAP34XX_HSUSB_OTG_BASE + OTG_SYSCONFIG); if (on) { reg &= ~SMARTSTDBY; /* remove possible smartstdby */ reg |= NOSTDBY; /* enable no standby */ reg |= NOIDLE; /* enable no idle */ } else { reg &= ~NOSTDBY; /* remove possible nostdby */ reg &= ~NOIDLE; /* remove possible noidle */ reg |= SMARTSTDBY; /* enable smart standby */ } omap_writel(reg, OMAP34XX_HSUSB_OTG_BASE + OTG_SYSCONFIG); }
static void __init htcoxygen_usb_enable(void) { unsigned int tries = 20; printk("trying to enable USB.\n"); /* force USB_EN GPIO to 0 */ do { omap_set_gpio_direction(33, 0); /* output */ omap_set_gpio_dataout(33, 0); /* low */ --tries; } while(omap_get_gpio_datain(33) && tries); if (tries) { printk("unable to reset USB_EN GPIO after 20 tries.\n"); printk("I will try to continue anyway: USB may not be available.\n"); } printk("USB_EN to 0 after %i tries.\n", tries); omap_set_gpio_dataout(73, 0); omap_set_gpio_direction(HTCWIZARD_GPIO_DM, 1); /* input */ /* get uart control from GSM */ /* select GPIO35 for D_MCLK_OUT */ /* select GPIO36 for D_CRESET */ omap_writel(omap_readl(OMAP730_IO_CONF_3) & 0xffffffcc, OMAP730_IO_CONF_3); omap_writel(omap_readl(OMAP730_IO_CONF_3) | 0x000000cc, OMAP730_IO_CONF_3); omap_set_gpio_direction(HTCWIZARD_GPIO_DP, 1); /* input */ /* select D_DM, D_DP for D_DM and disable PE_DM control */ omap_writel(omap_readl(OMAP730_IO_CONF_2) & 0xff1fffff, OMAP730_IO_CONF_2); omap_writel(omap_readl(OMAP730_IO_CONF_2) | 0x00100000, OMAP730_IO_CONF_2); mdelay(100); /* select USB_VBUSI for D_VBUSI, enable PE_VIBUSI pull enable control */ omap_writel(omap_readl(OMAP730_IO_CONF_2) & 0xf1ffffff, OMAP730_IO_CONF_2); omap_writel(omap_readl(OMAP730_IO_CONF_2) | 0x01000000, OMAP730_IO_CONF_2); /* set USB_VBUS_CTRL */ omap_writel(omap_readl(OMAP730_MODE_1) | (1 << 25), OMAP730_MODE_1); }
void omap_set_dma_priority(int lch, int dst_port, int priority) { unsigned long reg; u32 l; if (cpu_class_is_omap1()) { switch (dst_port) { case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ reg = OMAP_TC_OCPT1_PRIOR; break; case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */ reg = OMAP_TC_OCPT2_PRIOR; break; case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */ reg = OMAP_TC_EMIFF_PRIOR; break; case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */ reg = OMAP_TC_EMIFS_PRIOR; break; default: BUG(); return; } l = omap_readl(reg); l &= ~(0xf << 8); l |= (priority & 0xf) << 8; omap_writel(l, reg); } if (cpu_class_is_omap2()) { u32 ccr; ccr = dma_read(CCR(lch)); if (priority) ccr |= (1 << 6); else ccr &= ~(1 << 6); dma_write(ccr, CCR(lch)); } }
/* Resets clock rates and reboots the system. Only called from system.h */ void omap_prcm_arch_reset(char mode, const char *cmd) { s16 prcm_offs; omap2_clk_prepare_for_reboot(); if (cpu_is_omap24xx()) { prcm_offs = WKUP_MOD; prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL); } else if (cpu_is_omap34xx()) { u32 l; /* Copy cmd into scratchpad memmory if any */ if(cmd != 0) { u16 counter = 0; while((counter < (OMAP343X_SCRATCHPAD_BCB_SIZE-1)) && (cmd[counter]!='\0')) { omap_writeb(cmd[counter], OMAP343X_SCRATCHPAD_BCB + counter); counter++; } omap_writeb('\0', OMAP343X_SCRATCHPAD_BCB + counter); } prcm_offs = OMAP3430_GR_MOD; l = ('B' << 24) | ('M' << 16) | mode; /* Reserve the first word in scratchpad for communicating * with the boot ROM. A pointer to a data structure * describing the boot process can be stored there, * cf. OMAP34xx TRM, Initialization / Software Booting * Configuration. */ omap_writel(l, OMAP343X_SCRATCHPAD + 4); omap3_configure_core_dpll_warmreset(); } else WARN_ON(1); }
/* * OMAP4 does not allow aggressive DSS clock cutting, so we must keep the * clocks enabled during display use. These next two methods on OMAP4 * enable and disable all DSS clocks (main and needed optional). */ int dss_mainclk_enable() { int ret = 0; if (!dss.mainclk_state) { if (cpu_is_omap44xx() || cpu_is_omap34xx()) ret = dss_opt_clock_enable(); if (ret) dss_opt_clock_disable(); #ifdef CONFIG_PM_RUNTIME else { ret = pm_runtime_get_sync(&dss.pdev->dev); /* Work around added by Shankar * some time pm_runtime_get_sync fails to enable DSS clock */ { #define CM_DSS_DSS_CLKCTRL 0x4A009120 int val =0; val = omap_readl(CM_DSS_DSS_CLKCTRL); if (((val & 0x02) != 0x02) && ret == 0 ){ val = val | (1<<1); omap_writel(val, CM_DSS_DSS_CLKCTRL); printk("%s[%d] pm_runtime_get_sync failed set DSS clk reg, setting it forcefully clk=0x%x \n", __func__, __LINE__, omap_readl(CM_DSS_DSS_CLKCTRL)); } } } #endif if (!ret) dss.mainclk_state = true; } else { return -EBUSY; } return ret; }
static int justin_panel_enable_hdmi(struct omap_dss_device *dssdev) { //[[ 20120521 [email protected] for HDMI start int MaximumCount = 10; while ( hdmi_power_initialize==1 && MaximumCount-->0) msleep(100); hdmi_power_initialize =1; // CONTROL_PADCONF_DSS_PCLK omap_writel(omap_readl(0x480020D4) & ~0x7, 0x480020D4); extern void lp8720_reinit(); lp8720_reinit(); mdelay(20); //justin_panel_power_enable(1); justin_hdmi_reset_enable(1); mdelay(20); //2010-5-8 [email protected] sub-PMIC Power on #if 0 //20120521 [email protected] for HDMI subpm_set_output(SWREG,1); subpm_output_enable(); #endif subpm_set_output(LDO1,1); subpm_output_enable(); /* 20110531 comment by [email protected] subpm_set_output(LDO2,1); subpm_output_enable(); */ if(HDMI_DSS_DBG) printk(KERN_INFO "%s :: Enable_hdmi\n",__func__); msleep(20); return 0; }
static void b_peripheral(struct isp1301 *isp) { u32 l; l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS; omap_writel(l, OTG_CTRL); usb_gadget_vbus_connect(isp->otg.gadget); #ifdef CONFIG_USB_OTG enable_vbus_draw(isp, 8); otg_update_isp(isp); #else enable_vbus_draw(isp, 100); /* UDC driver just set OTG_BSESSVLD */ isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_DP_PULLUP); isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_DP_PULLDOWN); isp->otg.state = OTG_STATE_B_PERIPHERAL; pr_debug(" --> b_peripheral\n"); dump_regs(isp, "2periph"); #endif }
static void htcoxygen_lcd_init(void) { u32 reg; /* disable controller if active */ reg = omap_readl(OMAP_LCDC_CONTROL); if (reg & OMAP_LCDC_CTRL_LCD_EN) { reg &= ~OMAP_LCDC_CTRL_LCD_EN; omap_writel(reg, OMAP_LCDC_CONTROL); /* wait for end of frame */ while (!(omap_readl(OMAP_LCDC_STATUS) & OMAP_LCDC_STAT_DONE)); /* turn off DMA */ reg = omap_readw(OMAP_DMA_LCD_CCR); reg &= ~(1 << 7); omap_writew(reg, OMAP_DMA_LCD_CCR); reg = omap_readw(OMAP_DMA_LCD_CTRL); reg &= ~(1 << 8); omap_writew(reg, OMAP_DMA_LCD_CTRL); } }
/* called from irq handlers */ static void b_idle(struct isp1301 *isp, const char *tag) { u32 l; if (isp->otg.state == OTG_STATE_B_IDLE) return; isp->otg.default_a = 0; if (isp->otg.host) { isp->otg.host->is_b_host = 1; host_suspend(isp); } if (isp->otg.gadget) { isp->otg.gadget->is_a_peripheral = 0; gadget_suspend(isp); } isp->otg.state = OTG_STATE_B_IDLE; l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS; omap_writel(l, OTG_CTRL); isp->last_otg_ctrl = l; pr_debug(" --> %s/%s\n", state_name(isp), tag); }
static void __init htcoxygen_spi_mux(void) { /* Setup MUX config for SPI */ omap_writel(omap_readl(OMAP850_IO_CONF_6) | 0x00088880, OMAP850_IO_CONF_6); omap_writel(omap_readl(OMAP850_IO_CONF_6) & ~0x00077770, OMAP850_IO_CONF_6); omap_writel(omap_readl(OMAP850_IO_CONF_8) | 0x01000000, OMAP850_IO_CONF_8); omap_writel(omap_readl(OMAP850_IO_CONF_8) & ~0x10110000, OMAP850_IO_CONF_8); omap_writel(omap_readl(OMAP850_IO_CONF_9) | 0x00000010, OMAP850_IO_CONF_9); omap_writel(omap_readl(OMAP850_IO_CONF_9) & ~0x00000001, OMAP850_IO_CONF_9); /* configure spi setup registers */ omap_writew(0xfffe, OMAP850_SPI2_BASE + 0x02); omap_writew(0x0000, OMAP850_SPI2_BASE + 0x08); omap_writew(0x7ff8, OMAP850_SPI2_BASE + 0x0e); }
static int omap_ehci_bus_resume(struct usb_hcd *hcd) { struct ehci_hcd_omap *omap; unsigned long flags; int ret = 0; u32 reg; omap = ((struct ehci_hcd *) ((char *)hcd_to_ehci(hcd)))->omap_p; spin_lock_irqsave(&sus_res_lock, flags); if(omap->suspended){ clk_enable(omap->usbtll_fck); reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF); reg |=1; ehci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF, reg); clk_enable(omap->usbhost_fck); clk_enable(omap->usbhost_fs_fck); omap_writel(OHCI_HC_CTRL_RESUME, OHCI_HC_CONTROL); reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG); reg &= ~(3 << 12); reg &= ~(3 << 3); reg |= (1 << 12); reg |= (1 << 3); ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg); omap->suspended = 0; ehci_omap_writel(omap->tll_base, OMAP_USBTLL_IRQENABLE, 0); } ret = ehci_bus_resume(hcd); spin_unlock_irqrestore(&sus_res_lock, flags); return 0; }
/* Resets clock rates and reboots the system. Only called from system.h */ void omap_prcm_arch_reset(char mode) { s16 prcm_offs; omap2_clk_prepare_for_reboot(); if (cpu_is_omap24xx()) prcm_offs = WKUP_MOD; else if (cpu_is_omap34xx()) { u32 l; prcm_offs = OMAP3430_GR_MOD; l = ('B' << 24) | ('M' << 16) | mode; /* Reserve the first word in scratchpad for communicating * with the boot ROM. A pointer to a data structure * describing the boot process can be stored there, * cf. OMAP34xx TRM, Initialization / Software Booting * Configuration. */ omap_writel(l, OMAP343X_SCRATCHPAD + 4); } else WARN_ON(1); prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL); }
/* Sets the sensor related settings in ISPCTRL registers */ int camispcfg_set_ispif(unsigned char addr, unsigned int val) { unsigned int old_val; isp_get(); switch(addr) { case GET_ADDRESS(CAM_ISPIF_CTRL): { old_val = omap_readl(ISP_CTRL); old_val &= ~CAM_ISPIF_CTRL_MASK; val &= CAM_ISPIF_CTRL_MASK; omap_writel(old_val | val,ISP_CTRL); printk("oldval = 0x%x, val = 0x%x", old_val, val); printk(" ispctrl val = 0x%x", omap_readl(ISP_CTRL)); } break; default: break; }; isp_put(); return 0; }
/* * Set shared ports for using dark frame (lens shading) */ static void prev_set_isp_ctrl(u16 mode) { u32 val; val = omap_readl(ISP_CTRL); isp_ctrl = val; /* Read port used by preview module data read */ val &= ~ISP_CTRL_SBL_SHARED_RPORTA; if (mode & (PREV_DARK_FRAME_SUBTRACT | PREV_LENS_SHADING)) { /* Read port used by preview module dark frame read */ val &= ~ISP_CTRL_SBL_SHARED_RPORTB; } BIT_SET(val, SBL_RD_RAM_EN, 0x1, 0x1); /* write ISP CTRL register */ omap_writel(val, ISP_CTRL); prv_wsdr_addr = omap_readl(ISPPRV_WSDR_ADDR); }
/* Sets the sensor related settings in CCDC registers */ int camispcfg_set_ccdc(unsigned char addr, unsigned int val) { unsigned int old_val; isp_get(); switch(addr) { case GET_ADDRESS(CAM_CCDC_SYNCMODE): { old_val = omap_readl(ISPCCDC_SYN_MODE); old_val &= ~CAM_CCDC_SYNCMODE_MASK; val &= CAM_CCDC_SYNCMODE_MASK; omap_writel(old_val | val,ISPCCDC_SYN_MODE); printk("oldval = 0x%x, val = 0x%x", old_val, val); printk(" ccdc sync mode val = 0x%x", omap_readl(ISPCCDC_SYN_MODE)); } break; default: break; }; isp_put(); return 0; }
int latona_wifi_power(int on) { #if 0 //lewislee //#define CONTROL_PADCONF_ETK_D9 0x480025EC /* WLAN_EN */ //#define CONTROL_PADCONF_ETK_D10 0x480025F0 /* WLAN_IRQ */ //#define CONTROL_PADCONF_GPIO_OE 0x48310034 /* WLAN_EN GPIO OE */ //#define CONTROL_PADCONF_MMC3_CLK 0x480025D8 /* mmc3_cmd */ //#define CONTROL_PADCONF_MMC3_CMD 0x480025D8 /* mmc3_cmd */ omap_writel(0x480025EC, 0x361c0000); #endif pr_info("%s: %d\n", __func__, on); gpio_set_value(LATONA_WIFI_PMENA_GPIO, on); latona_wifi_power_state = on; msleep(300); return 0; }