Пример #1
0
void init_bootmode_straps(void)
{
#ifdef __PRE_RAM__
    u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
    u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
    u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
    u32 gp_lvl = inl(gpio_base + GP_LVL);
    u32 flags = 0;

    /* Write Protect: GPIO68 = CHP3_SPI_WP, active high */
    if (gp_lvl3 & (1 << (GPIO_SPI_WP-64)))
        flags |= (1 << FLAG_SPI_WP);
    /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
    if (!(gp_lvl2 & (1 << (GPIO_REC_MODE-32))))
        flags |= (1 << FLAG_REC_MODE);
    /* Developer: GPIO17 = KBC3_DVP_MODE, active high */
    if (gp_lvl & (1 << GPIO_DEV_MODE))
        flags |= (1 << FLAG_DEV_MODE);

    pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
#endif
}
Пример #2
0
static void ide_init(struct device *dev)
{
	struct southbridge_nvidia_ck804_config *conf;
	u32 dword;
	u16 word;
	u8 byte;

	conf = dev->chip_info;

	word = pci_read_config16(dev, 0x50);
	/* Ensure prefetch is disabled. */
	word &= ~((1 << 15) | (1 << 13));
	if (conf->ide1_enable) {
		/* Enable secondary IDE interface. */
		word |= (1 << 0);
		printk(BIOS_DEBUG, "IDE1 \t");
	}
	if (conf->ide0_enable) {
		/* Enable primary IDE interface. */
		word |= (1 << 1);
		printk(BIOS_DEBUG, "IDE0\n");
	}

	word |= (1 << 12);
	word |= (1 << 14);

	pci_write_config16(dev, 0x50, word);

	byte = 0x20;		/* Latency: 64 --> 32 */
	pci_write_config8(dev, 0xd, byte);

	dword = pci_read_config32(dev, 0xf8);
	dword |= 12;
	pci_write_config32(dev, 0xf8, dword);

#if CONFIG_PCI_ROM_RUN
	pci_dev_init(dev);
#endif
}
Пример #3
0
static void vga_init(device_t dev)
{
	u8 reg8;

	mainboard_interrupt_handlers(0x15, &via_cx700_int15_handler);

	//*
	pci_write_config8(dev, 0x04, 0x07);
	pci_write_config8(dev, 0x3e, 0x02);
	pci_write_config8(dev, 0x0d, 0x40);
	pci_write_config32(dev, 0x10, 0xa0000008);
	pci_write_config32(dev, 0x14, 0xdd000000);
	pci_write_config8(dev, 0x3c, 0x0b);
	//*/

	printk(BIOS_DEBUG, "Initializing VGA...\n");

	pci_dev_init(dev);

	if (pci_read_config32(dev, PCI_ROM_ADDRESS) != 0xc0000) return;

	printk(BIOS_DEBUG, "Enable VGA console\n");
	vga_enable_console();

	/* It's not clear if these need to be programmed before or after
	 * the VGA bios runs. Try both, clean up later */
	/* Set memory rate to 200MHz */
	outb(0x3d, CRTM_INDEX);
	reg8 = inb(CRTM_DATA);
	reg8 &= 0x0f;
	reg8 |= (0x3 << 4);
	outb(0x3d, CRTM_INDEX);
	outb(reg8, CRTM_DATA);

	/* Set framebuffer size to 32mb */
	reg8 = (32 / 4);
	outb(0x39, SR_INDEX);
	outb(reg8, SR_DATA);
}
Пример #4
0
static void usb_ehci_set_subsystem(device_t dev, unsigned vendor,
				   unsigned device)
{
	u8 access_cntl;

	access_cntl = pci_read_config8(dev, 0x80);

	/* Enable writes to protected registers. */
	pci_write_config8(dev, 0x80, access_cntl | 1);

	if (!vendor || !device) {
		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
				   pci_read_config32(dev, PCI_VENDOR_ID));
	} else {
		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
				   ((device & 0xffff) << 16) | (vendor &
								0xffff));
	}

	/* Restore protection. */
	pci_write_config8(dev, 0x80, access_cntl);
}
Пример #5
0
void intel_pch_finalize_smm(void)
{
	/* Set SPI opcode menu */
	RCBA16(0x3894) = SPI_OPPREFIX;
	RCBA16(0x3896) = SPI_OPTYPE;
	RCBA32(0x3898) = SPI_OPMENU_LOWER;
	RCBA32(0x389c) = SPI_OPMENU_UPPER;

	/* Lock SPIBAR */
	RCBA32_OR(0x3804, (1 << 15));

#if CONFIG_SPI_FLASH_SMM
	/* Re-init SPI driver to handle locked BAR */
	spi_init();
#endif

	/* TCLOCKDN: TC Lockdown */
	RCBA32_OR(0x0050, (1 << 31));

	/* BIOS Interface Lockdown */
	RCBA32_OR(0x3410, (1 << 0));

	/* Function Disable SUS Well Lockdown */
	RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));

	/* Global SMI Lock */
	pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);

	/* GEN_PMCON Lock */
	pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));

	/* R/WO registers */
	RCBA32(0x21a4) = RCBA32(0x21a4);
	pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
		    pci_read_config32(PCI_DEV(0, 27, 0), 0x74));

	/* Indicate finalize step with post code */
	outb(POST_OS_BOOT, 0x80);
}
Пример #6
0
static void
chrome_init(struct device *dev)
{
	uint32_t fb_size, fb_address;

	fb_size = k8m890_host_fb_size_get();
	if (!fb_size) {
		printk(BIOS_WARNING, "Chrome: Device has not been initialised in the"
			       " ramcontroller!\n");
		return;
	}

	fb_address = pci_read_config32(dev, 0x10);
	fb_address &= ~0x0F;
	if (!fb_address) {
		printk(BIOS_WARNING, "Chrome: No FB BAR assigned!\n");
		return;
	}

	printk(BIOS_INFO, "Chrome: Using %dMB Framebuffer at 0x%08X.\n",
		    fb_size, fb_address);

	//k8m890_host_fb_direct_set(fb_address);

#if CONFIG_VGA
	/* Now set up the VGA console */
	vga_io_init(); /* Enable full IO access */

	chrome_vga_init(dev);

	vga_textmode_init();

	printk(BIOS_INFO, "Chrome VGA Textmode initialized.\n");

	/* if we don't have console, at least print something... */
	vga_line_write(0, "Chrome VGA Textmode initialized.");
#endif /* CONFIG_VGA */
}
Пример #7
0
static void ide_init(struct device *dev)
{
	struct southbridge_amd_sb800_config *conf;
	/* Enable ide devices so the linux ide driver will work */
	u32 dword;
	u8 byte;

	conf = dev->chip_info;

	/* RPR9.1 disable MSI */
	/* TODO: For A14, it should set as 1. I doubt it. */
	dword = pci_read_config32(dev, 0x70);
	dword &= ~(1 << 16);
	pci_write_config32(dev, 0x70, dword);

	/* Ultra DMA mode */
	/* enable UDMA */
	byte = pci_read_config8(dev, 0x54);
	byte |= 1 << 0;
	pci_write_config8(dev, 0x54, byte);

	/* Enable I/O Access&& Bus Master */
	dword = pci_read_config16(dev, 0x4);
	dword |= 1 << 2;
	pci_write_config16(dev, 0x4, dword);

	/* set ide as primary, if you want to boot from IDE, you'd better set it
	 * in mainboard/Config.lb */
	if (conf->boot_switch_sata_ide == 1) {
		byte = pci_read_config8(dev, 0xAD);
		byte |= 1 << 4;
		pci_write_config8(dev, 0xAD, byte);
	}

#if CONFIG_PCI_ROM_RUN == 1
	pci_dev_init(dev);
#endif
}
Пример #8
0
static void enable_hpet(struct device *dev)
{
	const unsigned long hpet_address = 0xfed00000;

	uint32_t dword;
	uint32_t code = (0 & 0x3);

	dword = pci_read_config32(dev, GEN_CNTL);
	dword |= (1 << 17); /* enable hpet */

	/* Bits [16:15]  Memory Address Range
	 *	    00   FED0_0000h - FED0_03FFh
	 *	    01   FED0_1000h - FED0_13FFh
	 *	    10   FED0_2000h - FED0_23FFh
	 *	    11   FED0_3000h - FED0_33FFh
	 */

	dword &= ~(3 << 15); /* clear it */
	dword |= (code<<15);
	pci_write_config32(dev, GEN_CNTL, dword);

	printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address | (code <<12) );
}
Пример #9
0
static void native_init(struct device *dev)
{
	struct resource *lfb_res;
	struct resource *pio_res;
	u32 physbase;
	struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
	struct northbridge_intel_x4x_config *conf = dev->chip_info;

	lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2);
	pio_res = find_resource(dev, PCI_BASE_ADDRESS_4);
	physbase = pci_read_config32(dev, 0x5c) & ~0xf;

	if (gtt_res && gtt_res->base) {
		printk(BIOS_SPEW,
			"Initializing VGA without OPROM. MMIO 0x%llx\n",
			gtt_res->base);
		intel_gma_init(conf, res2mmio(gtt_res, 0, 0),
			physbase, pio_res->base, lfb_res->base);
	}

	/* Linux relies on VBT for panel info.  */
	generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE");
}
Пример #10
0
unsigned long acpi_fill_madt(unsigned long current)
{
	device_t dev;
	u32 dword;
	u32 gsi_base=0;
	/* create all subtables for processors */
	current = acpi_create_madt_lapics(current);

	/* Write SB700 IOAPIC, only one */
	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
					   IO_APIC_ADDR, gsi_base);
	/* IOAPIC on rs5690 */
	gsi_base += 24;		/* SB700 has 24 IOAPIC entries. */
	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
	if (dev) {
		pci_write_config32(dev, 0xF8, 0x1);
		dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2+1,
						   dword, gsi_base);
	}


	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
						current, 0, 0, 2, 0);
	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
						current, 0, 9, 9, 0xF);
	/* 0: mean bus 0--->ISA */
	/* 0: PIC 0 */
	/* 2: APIC 2 */
	/* 5 mean: 0101 --> Edge-triggered, Active high */

	/* create all subtables for processors */
	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
	/* 1: LINT1 connect to NMI */

	return current;
}
Пример #11
0
/*******************************************************
* Optimize k8 with UMA.
* See BKDG_NPT_0F guide for details.
* The processor node is addressed by its Node ID on the HT link and can be
* accessed with a device number in the PCI configuration space on Bus0.
* The Node ID 0 is mapped to Device 24 (0x18), the Node ID 1 is mapped
* to Device 25, and so on.
* The processor implements configuration registers in PCI configuration
* space using the following four headers
*	Function0: HT technology configuration
*	Function1: Address map configuration
*	Function2: DRAM and HT technology Trace mode configuration
*	Function3: Miscellaneous configuration
*******************************************************/
static void k8_optimization(void)
{
	pci_devfn_t k8_f0, k8_f2, k8_f3;
	msr_t msr;

	printk(BIOS_INFO, "k8_optimization()\n");
	k8_f0 = PCI_DEV(0, 0x18, 0);
	k8_f2 = PCI_DEV(0, 0x18, 2);
	k8_f3 = PCI_DEV(0, 0x18, 3);

	/* 8.6.6 K8 Buffer Allocation Settings */
	pci_write_config32(k8_f0, 0x90, 0x01700169);	/* CIM NPT_Optimization */
	set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28);
	set_nbcfg_enable_bits(k8_f0, 0x68, 3 << 26, 3 << 26);
	set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11);
	/* set_nbcfg_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15); */	/* TODO */

	pci_write_config32(k8_f3, 0x70, 0x51220111);
	pci_write_config32(k8_f3, 0x74, 0x50404021);
	pci_write_config32(k8_f3, 0x78, 0x08002A00);
	if (pci_read_config32(k8_f3, 0xE8) & 0x3<<12)
		pci_write_config32(k8_f3, 0x7C, 0x0000211A); /* dual core */
	else
		pci_write_config32(k8_f3, 0x7C, 0x0000212B); /* single core */
	set_nbcfg_enable_bits_8(k8_f3, 0xDC, 0xFF, 0x25);

	set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
	set_nbcfg_enable_bits(k8_f2, 0x94, 0xF << 24, 7 << 24);
	set_nbcfg_enable_bits(k8_f2, 0x90, 1 << 10, 0 << 10);
	set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2);
	set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);

	msr = rdmsr(NB_CFG_MSR);
	msr.lo &= ~(1 << 9);
	msr.hi &= ~(1 << 4);
	wrmsr(NB_CFG_MSR, msr);
}
Пример #12
0
static void sdram_set_registers(const struct mem_controller *ctrl)
{
	static const u32 register_values[] = {
		PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
		PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07420001 | DEVPRES_CONFIG,
		PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
		PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
		PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffffffff, 0x0040003a,
		PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, (uintptr_t)BAR | 0,
	};
	int i;

	for (i = 0; i < ARRAY_SIZE(register_values); i += 3) {
		device_t dev;
		u32 where;
		u32 reg;
		dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
		where = register_values[i] & 0xff;
		reg = pci_read_config32(dev, where);
		reg &= register_values[i+1];
		reg |= register_values[i+2];
		pci_write_config32(dev, where, reg);
	}
}
Пример #13
0
static void usb_init(struct device *dev)
{
        printk(BIOS_DEBUG, "USB 1.1 INIT:---------->\n");

//-------------- enable USB1.1 (SiS7001) -------------------------
{
        uint8_t  temp8;
        int i=0;

	 while(SiS_SiS7001_init[i][0] != 0)
	 {				temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]);
					temp8 &= SiS_SiS7001_init[i][1];
					temp8 |= SiS_SiS7001_init[i][2];
					pci_write_config8(dev, SiS_SiS7001_init[i][0], temp8);
					i++;
	 };
}
//-----------------------------------------------------------

#if DEBUG_USB
{
        int i;

        printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******");
        printk(BIOS_DEBUG, "\n    03020100  07060504  0B0A0908  0F0E0D0C");

        for(i=0;i<0xff;i+=4){
                if((i%16)==0)
                        printk(BIOS_DEBUG, "\n%02x: ", i);
                printk(BIOS_DEBUG, "%08x  ", pci_read_config32(dev,i));
        }
        printk(BIOS_DEBUG, "\n");
}
#endif
        printk(BIOS_DEBUG, "USB 1.1 INIT:<----------\n");
}
Пример #14
0
/*
 * set gpio40 gfx
 */
static void set_gpio40_gfx(void)
{
	u8 byte;
//	u16 word;
	u32 dword;
	struct device *sm_dev;
	/* disable the GPIO40 as CLKREQ2# function */
	byte = pm_ioread(0xd3);
	byte &= ~(1 << 7);
	pm_iowrite(0xd3, byte);

	/* disable the GPIO40 as CLKREQ3# function */
	byte = pm_ioread(0xd4);
	byte &= ~(1 << 0);
	pm_iowrite(0xd4, byte);

	/* enable pull up for GPIO68 */
	byte = pm2_ioread(0xf1);
	byte &=	~(1 << 4);
	pm2_iowrite(0xf1, byte);

	/* access the smbus extended register */
	sm_dev = pcidev_on_root(0x14, 0);

	/* set the gfx to 1x16 lanes */
	printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
	/* when the gpio40 is configured as GPIO, this will enable the output */
	pci_write_config32(sm_dev, 0xf8, 0x4);
	dword = pci_read_config32(sm_dev, 0xfc);
	dword &= ~(1 << 10);

        /* When the gpio40 is configured as GPIO, this will represent the output value*/
	/* 1 :enable two x8  , 0 : master slot enable only */
	dword &=  ~(1 << 26);
	pci_write_config32(sm_dev, 0xfc, dword);
}
Пример #15
0
static void ide_init(struct device *dev)
{
	struct southbridge_amd_sb700_config *conf;
	/* Enable ide devices so the linux ide driver will work */
	u32 dword;
	u8 byte;

	conf = dev->chip_info;

	/* RPR9.1 disable MSI */
	/* TODO: For A14, it should set as 1. I doubt it. */
	dword = pci_read_config32(dev, 0x70);
	dword &= ~(1 << 16);
	pci_write_config32(dev, 0x70, dword);

	/* Enable UDMA on all devices, it will become UDMA0 (default PIO is PIO0) */
	byte = pci_read_config8(dev, 0x54);
	byte |= 0xf;
	pci_write_config8(dev, 0x54, byte);

	/* Enable I/O Access&& Bus Master */
	dword = pci_read_config16(dev, 0x4);
	dword |= 1 << 2;
	pci_write_config16(dev, 0x4, dword);

	/* set ide as primary, if you want to boot from IDE, you'd better set it
	 * in $vendor/$mainboard/devicetree.cb */


	if (conf->boot_switch_sata_ide == 1) {
		struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
		byte = pci_read_config8(sm_dev, 0xAD);
		byte |= 1 << 4;
		pci_write_config8(sm_dev, 0xAD, byte);
	}
}
Пример #16
0
void igd_compute_ggc(sysinfo_t *const sysinfo)
{
	const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);

	const u32 capid = pci_read_config32(mch_dev, D0F0_CAPID0 + 4);
	if (!sysinfo->enable_igd || (capid & (1 << (33 - 32))))
		sysinfo->ggc = 0x0002;
	else {
		u8 gfxsize;

		/* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled,
		   2MB GTT + 2MB shadow GTT (0x0b00) else. */
		if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
			/* 4 for 32MB, default if not set in cmos */
			gfxsize = 4;
		}
		/* Handle invalid cmos settings */
		if (gfxsize > 12)
			gfxsize = 4;
		sysinfo->ggc = 0x0300 | ((gfxsize + 1) << 4);
		if (!(capid & (1 << (48 - 32))))
			sysinfo->ggc |= 0x0800;
	}
}
Пример #17
0
static void mainboard_init(device_t dev)
{
	struct southbridge_intel_i82801gx_config *config;
	device_t dev0, idedev;

#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
	/* Install custom int15 handler for VGA OPROM */
	mainboard_interrupt_handlers(0x15, &int15_handler);
#endif

	/* If we're resuming from suspend, blink suspend LED */
	dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
	if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
		ec_write(0x0c, 0xc7);

	idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));

	if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) {
		/* legacy I/O connected */
		pmh7_ultrabay_power_enable(1);
		ec_write(0x0c, 0x84);
	} else if (idedev && idedev->chip_info &&
		   h8_ultrabay_device_present()) {
		config = idedev->chip_info;
		config->ide_enable_primary = 1;
		pmh7_ultrabay_power_enable(1);
		ec_write(0x0c, 0x84);
	} else {
		pmh7_ultrabay_power_enable(0);
		ec_write(0x0c, 0x04);
	}

	/* set dock status led */
	ec_write(0x0c, 0x08);
	ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09);
}
Пример #18
0
unsigned long acpi_fill_madt(unsigned long current)
{
	device_t dev;
	u32 dword;
	u32 gsi_base = 0;
	u32 apicid_sp5100;
	u32 apicid_sr5650;

	/*
	 * AGESA v5 Apply apic enumeration rules
	 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
	 * put the local-APICs at m..z
	 * For systems with < 16 APICs, put the Local-APICs at 0..n and
	 * put the IO-APICs at (n + 1)..z
	 */
	if (CONFIG_MAX_CPUS >= 16)
		apicid_sp5100 = 0x0;
	else
		apicid_sp5100 = CONFIG_MAX_CPUS + 1;
	apicid_sr5650 = apicid_sp5100 + 1;

	/* create all subtables for processors */
	current = acpi_create_madt_lapics(current);

	/* Write sp5100 IOAPIC, only one */
	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
			apicid_sp5100,
			IO_APIC_ADDR,
			0
			);

	/* IOAPIC on rs5690 */
	gsi_base += IO_APIC_INTERRUPTS;  /* SP5100 has 24 IOAPIC entries. */
	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
	if (dev) {
		pci_write_config32(dev, 0xF8, 0x1);
		dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
				apicid_sr5650,
				dword,
				gsi_base
				);
	}

	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current,
			0, //BUS
			0, //SOURCE
			2, //gsirq
			0  //flags
			);

	/* 0: mean bus 0--->ISA */
	/* 0: PIC 0 */
	/* 2: APIC 2 */
	/* 5 mean: 0101 --> Edge-triggered, Active high */

	/* create all subtables for processors */
	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
	/* 1: LINT1 connect to NMI */

	return current;
}
Пример #19
0
static void *smp_write_config_table(void *v)
{
        struct mp_config_table *mc;

	int i, bus_isa;
	struct mb_sysconf_t *m;

        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

	mptable_init(mc, LAPIC_ADDR);

        smp_write_processors(mc);

	get_bus_conf();
	m = sysconf.mb;

	mptable_write_buses(mc, NULL, &bus_isa);

/*I/O APICs:   APIC ID Version State           Address*/
        {
		device_t dev = 0;
               struct resource *res;
               for(i=0; i<3; i++) {
                       dev = dev_find_device(0x1166, 0x0235, dev);
                       if (dev) {
                               res = find_resource(dev, PCI_BASE_ADDRESS_0);
                               if (res) {
                                       smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
                               }
                       }
               }

       }

	mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0);

//IDE
       outb(0x02, 0xc00); outb(0x0e, 0xc01);

       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); // IDE

//SATA
       outb(0x07, 0xc00); outb(0x0f, 0xc01);
        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xf);

//USB
       outb(0x01, 0xc00); outb(0x0a, 0xc01);
        for(i=0;i<3;i++) {
                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); //
        }



        /* enable int */
        /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
        {
                device_t dev;
                dev = dev_find_device(0x1166, 0x0205, 0);
                if(dev) {
                        uint32_t dword;
                        dword = pci_read_config32(dev, 0x6c);
                        dword |= (1<<4); // enable interrupts
                        pci_write_config32(dev, 0x6c, dword);
                }
                }

//First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
       // AIC 8130 Galileo Technology...
        for(i=0;i<4;i++) {
                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6<<2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); //
        }


//pci slot (on bcm5785)
        for(i=0;i<4;i++) {
                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5<<2)|i, m->apicid_bcm5785[1], 8+i%4); //
        }


//onboard ati
        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4<<2)|0, m->apicid_bcm5785[1], 0x1);

//PCI-X on bcm5780
        for(i=0;i<4;i++) {
                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4<<2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); //
        }

//onboard Broadcom
        for(i=0;i<2;i++) {
                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4<<2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); //
        }


// First PCI-E x8
        for(i=0;i<4;i++) {
                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0<<2)|i, m->apicid_bcm5785[1], 0xe); //
        }


// Second PCI-E x8
        for(i=0;i<4;i++) {
                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0<<2)|i, m->apicid_bcm5785[1], 0xc); //
        }

// Third PCI-E x1
        for(i=0;i<4;i++) {
                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0<<2)|i, m->apicid_bcm5785[1], 0xd); //
        }

/*Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
       smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
       smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
       /* There is no extension information... */

       /* Compute the checksums */
       mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
       mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
       printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
               mc, smp_next_mpe_entry(mc));
       return smp_next_mpe_entry(mc);
}
Пример #20
0
int sch_port_access_read(int port, int reg, int bytes)
{
	pci_write_config32(PCI_DEV(0, 0, 0), MCR,
			   (MSG_OPCODE_READ | (port << 16) | (reg << 8)));
	return pci_read_config32(PCI_DEV(0, 0, 0), MDR);
}
Пример #21
0
/**
 * @brief Enable resources for children devices
 *
 * @param dev the device whose children's resources are to be enabled
 *
 */
void lpc_enable_childrens_resources(device_t dev)
{
    struct bus *link;
    u32 reg, reg_x;
    int var_num = 0;
    u16 reg_var[3];

    printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__);
    reg = pci_read_config32(dev, 0x44);
    reg_x = pci_read_config32(dev, 0x48);

    for (link = dev->link_list; link; link = link->next) {
        device_t child;
        for (child = link->children; child;
                child = child->sibling) {
            if (child->enabled
                    && (child->path.type == DEVICE_PATH_PNP)) {
                struct resource *res;
                for (res = child->resource_list; res; res = res->next) {
                    u32 base, end;	/*  don't need long long */
                    if (!(res->flags & IORESOURCE_IO))
                        continue;
                    base = res->base;
                    end = resource_end(res);
                    /*
                    					printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n",
                    					     dev_path(child), base, end);
                    */
                    switch (base) {
                    case 0x60:	/*  KB */
                    case 0x64:	/*  MS */
                        reg |= (1 << 29);
                        break;
                    case 0x3f8:	/*  COM1 */
                        reg |= (1 << 6);
                        break;
                    case 0x2f8:	/*  COM2 */
                        reg |= (1 << 7);
                        break;
                    case 0x378:	/*  Parallel 1 */
                        reg |= (1 << 0);
                        break;
                    case 0x3f0:	/*  FD0 */
                        reg |= (1 << 26);
                        break;
                    case 0x220:	/*  Audio 0 */
                        reg |= (1 << 8);
                        break;
                    case 0x300:	/*  Midi 0 */
                        reg |= (1 << 18);
                        break;
                    case 0x400:
                        reg_x |= (1 << 16);
                        break;
                    case 0x480:
                        reg_x |= (1 << 17);
                        break;
                    case 0x500:
                        reg_x |= (1 << 18);
                        break;
                    case 0x580:
                        reg_x |= (1 << 19);
                        break;
                    case 0x4700:
                        reg_x |= (1 << 22);
                        break;
                    case 0xfd60:
                        reg_x |= (1 << 23);
                        break;
                    default:
                        if (var_num >= 3)
                            continue;	/* only 3 var ; compact them ? */
                        switch (var_num) {
                        case 0:
                            reg_x |= (1 << 2);
                            break;
                        case 1:
                            reg_x |= (1 << 24);
                            break;
                        case 2:
                            reg_x |= (1 << 25);
                            break;
                        }
                        reg_var[var_num++] =
                            base & 0xffff;
                    }
                }
            }
        }
    }
    pci_write_config32(dev, 0x44, reg);
    pci_write_config32(dev, 0x48, reg_x);
    /* Set WideIO for as many IOs found (fall through is on purpose) */
    switch (var_num) {
    case 2:
        pci_write_config16(dev, 0x90, reg_var[2]);
    case 1:
        pci_write_config16(dev, 0x66, reg_var[1]);
    case 0:
        //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata
        break;
    }
    printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__);
}
Пример #22
0
static void pci_init(device_t dev)
{
	u32 dword;
	u16 word;
	u8 byte;

	/* RPR 5.1 Enables the PCI-bridge subtractive decode */
	/* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */
	printk_info("Enables the PCI-bridge subtractive decode\n");
	byte = pci_read_config8(dev, 0x4B);
	byte |= 1 << 7;
	pci_write_config8(dev, 0x4B, byte);
	byte = pci_read_config8(dev, 0x40);
	byte |= 1 << 5;
	pci_write_config8(dev, 0x40, byte);

#ifdef USE_780E_VGA
//vga pci card support   //lycheng
	/* PCI Command: Enable IO response */
	byte = pci_read_config8(dev, 0x04);
	byte |= (1 << 0)|(1 << 5)|(1 << 1)|(1 << 2);
	pci_write_config8(dev, 0x04, byte);
	/* PCI Command: VGA enable */
	byte = pci_read_config8(dev, 0x3e);
	byte |= (1 << 3);
	pci_write_config8(dev, 0x3e, byte);
//end vga pci card support
#endif

	/* RPR5.2 PCI-bridge upstream dual address window */
	/* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */
	printk_info("PCI-bridge upstream dual address window\n");
	byte = pci_read_config8(dev, 0x50);
	//byte |= 1 << 0;
	byte &= ~(1 << 0);
	pci_write_config8(dev, 0x50, byte);

	/* RPR 5.3 PCI bus 64-byte DMA read access */
	/* Enhance the PCI bus DMA performance */
	printk_info("PCI bus 64-byte DMA read access\n");
	byte = pci_read_config8(dev, 0x4B);
	byte |= 1 << 4;
	pci_write_config8(dev, 0x4B, byte);

	/* RPR 5.4 Enables the PCIB writes to be cacheline aligned. */
	/* The size of the writes will be set in the Cacheline Register */
	printk_info("Enables the PCIB writes to be cacheline aligned.\n");
	byte = pci_read_config8(dev, 0x40);
	byte |= 1 << 1;
	pci_write_config8(dev, 0x40, byte);

	/* RPR 5.5 Enables the PCIB to retain ownership of the bus on the Primary side and on the Secondary side when GNT# is deasserted */
	printk_info("Enables the PCIB to retain ownership of the bus\n");
	pci_write_config8(dev, 0x0D, 0x40);
	pci_write_config8(dev, 0x1B, 0x40);

	/* RPR 5.6 Enable the command matching checking function on "Memory Read" & "Memory Read Line" commands */
	printk_info("Enable the command matching checking function\n");
	byte = pci_read_config8(dev, 0x4B);
	byte |= 1 << 6;
	pci_write_config8(dev, 0x4B, byte);

	/* RPR 5.7 When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT# */
	printk_info("the PCI arbiter checks for the Bus Idle before asserting GNT#\n");
	byte = pci_read_config8(dev, 0x4B);
	byte |= 1 << 0;
	pci_write_config8(dev, 0x4B, byte);

	/* RPR 5.8 Adjusts the GNT# de-assertion time */
	printk_info("Adjusts the GNT# de-assertion time\n");
	word = pci_read_config16(dev, 0x64);
	word |= 1 << 12;
	pci_write_config16(dev, 0x64, word);

	/* RPR 5.9 Fast Back to Back transactions support */
	printk_info("Fast Back to Back transactions support\n");
	byte = pci_read_config8(dev, 0x48);
	byte |= 1 << 2;
	/* pci_write_config8(dev, 0x48, byte); */

	/* RPR 5.10 Enable Lock Operation */
	/* byte = pci_read_config8(dev, 0x48); */
	byte |= 1 << 3;
	pci_write_config8(dev, 0x48, byte);

	/* RPR 5.11 Enable additional optional PCI clock */
	printk_info("Enable additional optional PCI clock\n");
	word = pci_read_config16(dev, 0x64);
	word |= 1 << 8;
	pci_write_config16(dev, 0x64, word);

	/* RPR 5.12 Enable One-Prefetch-Channel Mode */
	printk_info("Enable One-Prefetch-Channel Mode\n");
	dword = pci_read_config32(dev, 0x64);
	dword |= 1 << 20;
	pci_write_config32(dev, 0x64, dword);

	/* RPR 5.13 Disable PCIB MSI Capability */
	printk_info("Disable PCIB MSI Capability\n");
	byte = pci_read_config8(dev, 0x40);
	byte &= ~(1 << 3);
	pci_write_config8(dev, 0x40, byte);

	/* rpr5.14 Adjusting CLKRUN# */
	printk_info("Adjusting CLKRUN\n");
	dword = pci_read_config32(dev, 0x64);
	dword |= (1 << 15);
	pci_write_config32(dev, 0x64, dword);
}
Пример #23
0
static void pci_domain_set_resources(device_t dev)
{
    uint64_t tom, me_base, touud;
    uint32_t tseg_base, uma_size, tolud;
    uint16_t ggc;
    unsigned long long tomk;

    /* Total Memory 2GB example:
     *
     *  00000000  0000MB-1992MB  1992MB  RAM     (writeback)
     *  7c800000  1992MB-2000MB     8MB  TSEG    (SMRR)
     *  7d000000  2000MB-2002MB     2MB  GFX GTT (uncached)
     *  7d200000  2002MB-2034MB    32MB  GFX UMA (uncached)
     *  7f200000   2034MB TOLUD
     *  7f800000   2040MB MEBASE
     *  7f800000  2040MB-2048MB     8MB  ME UMA  (uncached)
     *  80000000   2048MB TOM
     * 100000000  4096MB-4102MB     6MB  RAM     (writeback)
     *
     * Total Memory 4GB example:
     *
     *  00000000  0000MB-2768MB  2768MB  RAM     (writeback)
     *  ad000000  2768MB-2776MB     8MB  TSEG    (SMRR)
     *  ad800000  2776MB-2778MB     2MB  GFX GTT (uncached)
     *  ada00000  2778MB-2810MB    32MB  GFX UMA (uncached)
     *  afa00000   2810MB TOLUD
     *  ff800000   4088MB MEBASE
     *  ff800000  4088MB-4096MB     8MB  ME UMA  (uncached)
     * 100000000   4096MB TOM
     * 100000000  4096MB-5374MB  1278MB  RAM     (writeback)
     * 14fe00000   5368MB TOUUD
     */

    /* Top of Upper Usable DRAM, including remap */
    touud = pci_read_config32(dev, TOUUD+4);
    touud <<= 32;
    touud |= pci_read_config32(dev, TOUUD);

    /* Top of Lower Usable DRAM */
    tolud = pci_read_config32(dev, TOLUD);

    /* Top of Memory - does not account for any UMA */
    tom = pci_read_config32(dev, 0xa4);
    tom <<= 32;
    tom |= pci_read_config32(dev, 0xa0);

    printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",
           touud, tolud, tom);

    /* ME UMA needs excluding if total memory <4GB */
    me_base = pci_read_config32(dev, 0x74);
    me_base <<= 32;
    me_base |= pci_read_config32(dev, 0x70);

    printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base);

    tomk = tolud >> 10;
    if (me_base == tolud) {
        /* ME is from MEBASE-TOM */
        uma_size = (tom - me_base) >> 10;
        /* Increment TOLUD to account for ME as RAM */
        tolud += uma_size << 10;
        /* UMA starts at old TOLUD */
        uma_memory_base = tomk * 1024ULL;
        uma_memory_size = uma_size * 1024ULL;
        printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n",
               me_base, uma_size >> 10);
    }
Пример #24
0
static u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index)
{
	pci_write_config32(dev, index_reg, index);
	return pci_read_config32(dev, index_reg + 0x4);
}
Пример #25
0
void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base)
{
	u32 i;

#if RES_DEBUG
	print_debug("setting up resource map ex offset....");

#endif

#if RES_DEBUG
	print_debug("\n");
#endif
	for(i = 0; i < max; i += 4) {
#if RES_DEBUG
		printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
			i/4, register_values[i],
			register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
			register_values[i+2],
			register_values[i+3] + ( ( (register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0)
			);
#endif
		switch (register_values[i]) {
		case RES_PCI_IO: //PCI
			{
			device_t dev;
			u32 where;
			u32 reg;
			dev = (register_values[i+1] & ~0xfff) + offset_pci_dev;
			where = register_values[i+1] & 0xfff;
			reg = pci_read_config32(dev, where);
			reg &= register_values[i+2];
			reg |= register_values[i+3];
			pci_write_config32(dev, where, reg);
			}
			break;
		case RES_PORT_IO_8: // io 8
			{
			u32 where;
			u32 reg;
			where = register_values[i+1] + offset_io_base;
			reg = inb(where);
			reg &= register_values[i+2];
			reg |= register_values[i+3];
			outb(reg, where);
			}
			break;
		case RES_PORT_IO_32:  //io32
			{
			u32 where;
			u32 reg;
			where = register_values[i+1] + offset_io_base;
			reg = inl(where);
			reg &= register_values[i+2];
			reg |= register_values[i+3];
			outl(reg, where);
			}
			break;
		} // switch


	}

#if RES_DEBUG
	print_debug("done.\n");
#endif
}
Пример #26
0
void rs780_htinit(void)
{
	/*
	 * About HT, it has been done in enumerate_ht_chain().
	 */
	pci_devfn_t cpu_f0, rs780_f0, clk_f1;
	u32 reg;
	u8 cpu_ht_freq, ibias;

	cpu_f0 = PCI_DEV(0, 0x18, 0);
	/************************
	* get cpu's ht freq, in cpu's function 0, offset 0x88
	* bit11-8, specifics the maximum operation frequency of the link's transmitter clock.
	* The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero
	* value to this reg, and that value takes effect on the next warm reset or
	* LDTSTOP_L disconnect sequence.
	* please see the table rs780_ibias about the value and its corresponding frequency.
	************************/
	reg = pci_read_config32(cpu_f0, 0x88);
	cpu_ht_freq = (reg & 0xf00) >> 8;
	printk(BIOS_INFO, "rs780_htinit cpu_ht_freq=%x.\n", cpu_ht_freq);
	rs780_f0 = PCI_DEV(0, 0, 0);
	//set_nbcfg_enable_bits(rs780_f0, 0xC8, 0x7<<24 | 0x7<<28, 1<<24 | 1<<28);

	clk_f1 = PCI_DEV(0, 0, 1); /* We need to make sure the F1 is accessible. */

	ibias = rs780_ibias[cpu_ht_freq];

	/* If HT freq>1GHz, we assume the CPU is fam10, else it is K8.
	 * Is it appropriate?
	 * Frequency is 1GHz, i.e. cpu_ht_freq is 6, in most cases.
	 * So we check 6 only, it would be faster. */
	if ((cpu_ht_freq == 0x6) || (cpu_ht_freq == 0x5) || (cpu_ht_freq == 0x4) ||
		(cpu_ht_freq == 0x2) || (cpu_ht_freq == 0x0)) {
		printk(BIOS_INFO, "rs780_htinit: HT1 mode\n");

		/* HT1 mode, RPR 8.4.2 */
		/* set IBIAS code */
		set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias);
		/* Optimizes chipset HT transmitter drive strength */
		set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1);
	} else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) {
		printk(BIOS_INFO, "rs780_htinit: HT3 mode\n");

		#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
		/* HT3 mode, RPR 8.4.3 */
		set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0);

		/* set IBIAS code */
		set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias);
		/* Optimizes chipset HT transmitter drive strength */
		set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1);
		/* Enables error-retry mode */
		set_nbcfg_enable_bits(rs780_f0, 0x44, 0x1, 0x1);
		/* Enables scrambling and Disables command throttling */
		set_nbcfg_enable_bits(rs780_f0, 0xac, (1 << 3) | (1 << 14), (1 << 3) | (1 << 14));
		/* Enables transmitter de-emphasis */
		set_nbcfg_enable_bits(rs780_f0, 0xa4, 1 << 31, 1 << 31);
		/* Enables transmitter de-emphasis level */
		/* Sets training 0 time */
		set_nbcfg_enable_bits(rs780_f0, 0xa0, 0x3F, 0x14);

		/* Enables strict TM4 detection */
		set_htiu_enable_bits(rs780_f0, 0x15, 0x1 << 22, 0x1 << 22);
		/* Enables proper DLL reset sequence */
		set_htiu_enable_bits(rs780_f0, 0x16, 0x1 << 10, 0x1 << 10);

		/* HyperTransport 3 Processor register settings to be done in northbridge */
		/* Enables error-retry mode */
		set_fam10_ext_cfg_enable_bits(cpu_f0, 0x130, 1 << 0, 1 << 0);
		/* Enables scrambling */
		set_fam10_ext_cfg_enable_bits(cpu_f0, 0x170, 1 << 3, 1 << 3);
		/* Enables transmitter de-emphasis
		 * This depends on the PCB design and the trace */
		/* TODO: */
		/* Disables command throttling */
		set_fam10_ext_cfg_enable_bits(cpu_f0, 0x168, 1 << 10, 1 << 10);
		/* Sets Training 0 Time. See T0Time table for encodings */
		set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x20);
		/* TODO: */
		#endif	/* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
	}
}
Пример #27
0
void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base)
{
	u32 i;

	if (IS_ENABLED(RES_DEBUG))
		printk(BIOS_DEBUG, "setting up resource map ex offset....\n");

	for (i = 0; i < max; i += 4) {
		if (IS_ENABLED(RES_DEBUG))
			printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
				i/4, register_values[i],
				register_values[i+1] + ((register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
				register_values[i+2],
				register_values[i+3] + (((register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0)
				);
		switch (register_values[i]) {
		case RES_PCI_IO: //PCI
			{
			pci_devfn_t dev;
			u32 where;
			u32 reg;
			dev = (register_values[i+1] & ~0xfff) + offset_pci_dev;
			where = register_values[i+1] & 0xfff;
			reg = pci_read_config32(dev, where);
			if (IS_ENABLED(RES_DEBUG))
				printk(BIOS_SPEW, "WAS: %08x\n", reg);
			reg &= register_values[i+2];
			reg |= register_values[i+3];
			pci_write_config32(dev, where, reg);
			if (IS_ENABLED(RES_DEBUG))
				printk(BIOS_SPEW, "NOW: %08x\n", reg);
			}
			break;
		case RES_PORT_IO_8: // io 8
			{
			u32 where;
			u32 reg;
			where = register_values[i+1] + offset_io_base;
			reg = inb(where);
			if (IS_ENABLED(RES_DEBUG))
				printk(BIOS_SPEW, "WAS: %08x\n", reg);
			reg &= register_values[i+2];
			reg |= register_values[i+3];
			outb(reg, where);
			if (IS_ENABLED(RES_DEBUG))
				printk(BIOS_SPEW, "NOW: %08x\n", reg);
			}
			break;
		case RES_PORT_IO_32:  //io32
			{
			u32 where;
			u32 reg;
			where = register_values[i+1] + offset_io_base;
			reg = inl(where);
			if (IS_ENABLED(RES_DEBUG))
				printk(BIOS_SPEW, "WAS: %08x\n", reg);
			reg &= register_values[i+2];
			reg |= register_values[i+3];
			outl(reg, where);
			if (IS_ENABLED(RES_DEBUG))
				printk(BIOS_SPEW, "NOW: %08x\n", reg);
			}
			break;
		}
	}

	if (IS_ENABLED(RES_DEBUG))
		printk(BIOS_DEBUG, "done.\n");
}
Пример #28
0
static void i82801ix_power_options(device_t dev)
{
	u8 reg8;
	u16 reg16, pmbase;
	u32 reg32;
	const char *state;
	/* Get the chip configuration */
	config_t *config = dev->chip_info;

	int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
	int nmi_option;

	/* BIOS must program... */
	reg32 = pci_read_config32(dev, 0xac);
	pci_write_config32(dev, 0xac, reg32 | (1 << 30) | (3 << 8));

	/* Which state do we want to goto after g3 (power restored)?
	 * 0 == S0 Full On
	 * 1 == S5 Soft Off
	 *
	 * If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
	 */
	if (get_option(&pwr_on, "power_on_after_fail") != CB_SUCCESS)
		pwr_on = MAINBOARD_POWER_ON;

	reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3);
	reg8 &= 0xfe;
	switch (pwr_on) {
	case MAINBOARD_POWER_OFF:
		reg8 |= 1;
		state = "off";
		break;
	case MAINBOARD_POWER_ON:
		reg8 &= ~1;
		state = "on";
		break;
	case MAINBOARD_POWER_KEEP:
		reg8 &= ~1;
		state = "state keep";
		break;
	default:
		state = "undefined";
	}

	reg8 |= (3 << 4);	/* avoid #S4 assertions */
	reg8 &= ~(1 << 3);	/* minimum asssertion is 1 to 2 RTCCLK */

	pci_write_config8(dev, D31F0_GEN_PMCON_3, reg8);
	printk(BIOS_INFO, "Set power %s after power failure.\n", state);

	/* Set up NMI on errors. */
	reg8 = inb(0x61);
	reg8 &= 0x0f;		/* Higher Nibble must be 0 */
	reg8 &= ~(1 << 3);	/* IOCHK# NMI Enable */
	// reg8 &= ~(1 << 2);	/* PCI SERR# Enable */
	reg8 |= (1 << 2); /* PCI SERR# Disable for now */
	outb(reg8, 0x61);

	reg8 = inb(0x74); /* Read from 0x74 as 0x70 is write only. */
	nmi_option = NMI_OFF;
	get_option(&nmi_option, "nmi");
	if (nmi_option) {
		printk(BIOS_INFO, "NMI sources enabled.\n");
		reg8 &= ~(1 << 7);	/* Set NMI. */
	} else {
		printk(BIOS_INFO, "NMI sources disabled.\n");
		reg8 |= ( 1 << 7);	/* Can't mask NMI from PCI-E and NMI_NOW */
	}
	outb(reg8, 0x70);

	/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
	reg16 = pci_read_config16(dev, D31F0_GEN_PMCON_1);
	reg16 &= ~(3 << 0);	// SMI# rate 1 minute
	reg16 |= (1 << 2);	// CLKRUN_EN - Mobile/Ultra only
	reg16 |= (1 << 3);	// Speedstep Enable - Mobile/Ultra only
	reg16 |= (1 << 5);	// CPUSLP_EN Desktop only

	if (config->c4onc3_enable)
		reg16 |= (1 << 7);

	// another laptop wants this?
	// reg16 &= ~(1 << 10);	// BIOS_PCI_EXP_EN - Desktop/Mobile only
	reg16 |= (1 << 10);	// BIOS_PCI_EXP_EN - Desktop/Mobile only
#if DEBUG_PERIODIC_SMIS
	/* Set DEBUG_PERIODIC_SMIS in i82801ix.h to debug using
	 * periodic SMIs.
	 */
	reg16 |= (3 << 0); // Periodic SMI every 8s
#endif
	if (config->c5_enable)
		reg16 |= (1 << 11); /* Enable C5, C6 and PMSYNC# */
	pci_write_config16(dev, D31F0_GEN_PMCON_1, reg16);

	/* Set exit timings for C5/C6. */
	if (config->c5_enable) {
		reg8 = pci_read_config8(dev, D31F0_C5_EXIT_TIMING);
		reg8 &= ~((7 << 3) | (7 << 0));
		if (config->c6_enable)
			reg8 |= (5 << 3) | (3 << 0); /* 38-44us PMSYNC# to STPCLK#,
							95-102us DPRSTP# to STP_CPU# */
		else
			reg8 |= (0 << 3) | (1 << 0); /* 16-17us PMSYNC# to STPCLK#,
							34-40us DPRSTP# to STP_CPU# */
		pci_write_config8(dev, D31F0_C5_EXIT_TIMING, reg8);
	}

	// Set the board's GPI routing.
	i82801ix_gpi_routing(dev);

	pmbase = pci_read_config16(dev, 0x40) & 0xfffe;

	outl(config->gpe0_en, pmbase + 0x28);
	outw(config->alt_gp_smi_en, pmbase + 0x38);

	/* Set up power management block and determine sleep mode */
	reg16 = inw(pmbase + 0x00); /* PM1_STS */
	outw(reg16, pmbase + 0x00); /* Clear status bits. At least bit11 (power
				       button override) must be cleared or SCI
				       will be constantly fired and OSPM must
				       not know about it (ACPI spec says to
				       ignore the bit). */
	reg32 = inl(pmbase + 0x04); // PM1_CNT
	reg32 &= ~(7 << 10);	// SLP_TYP
	outl(reg32, pmbase + 0x04);

	/* Set duty cycle for hardware throttling (defaults to 0x0: 50%). */
	reg32 = inl(pmbase + 0x10);
	reg32 &= ~(7 << 5);
	reg32 |= (config->throttle_duty & 7) << 5;
	outl(reg32, pmbase + 0x10);
}
Пример #29
0
static u32 f1_read_config32(unsigned reg)
{
	if (fx_devs == 0)
		get_fx_devs();
	return pci_read_config32(__f1_dev[0], reg);
}
Пример #30
0
/* Put device in D3Hot Power State */
static void pch_enable_d3hot(device_t dev)
{
    u32 reg32 = pci_read_config32(dev, PCH_PCS);
    reg32 |= PCH_PCS_PS_D3HOT;
    pci_write_config32(dev, PCH_PCS, reg32);
}