static void tc6393xb_nand_irq(TC6393xbState *s) { qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND], (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr)); }
static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) { sysctrl_t *sysctrl = opaque; trace_prep_io_800_writeb(addr - PPC_IO_BASE, val); switch (addr) { case 0x0092: /* Special port 92 */ /* Check soft reset asked */ if (val & 0x01) { qemu_irq_raise(sysctrl->reset_irq); } else { qemu_irq_lower(sysctrl->reset_irq); } /* Check LE mode */ if (val & 0x02) { sysctrl->endian = 1; } else { sysctrl->endian = 0; } break; case 0x0800: /* Motorola CPU configuration register : read-only */ break; case 0x0802: /* Motorola base module feature register : read-only */ break; case 0x0803: /* Motorola base module status register : read-only */ break; case 0x0808: /* Hardfile light register */ if (val & 1) sysctrl->state |= STATE_HARDFILE; else sysctrl->state &= ~STATE_HARDFILE; break; case 0x0810: /* Password protect 1 register */ if (sysctrl->nvram != NULL) { NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); (k->toggle_lock)(sysctrl->nvram, 1); } break; case 0x0812: /* Password protect 2 register */ if (sysctrl->nvram != NULL) { NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); (k->toggle_lock)(sysctrl->nvram, 2); } break; case 0x0814: /* L2 invalidate register */ // tlb_flush(first_cpu, 1); break; case 0x081C: /* system control register */ sysctrl->syscontrol = val & 0x0F; break; case 0x0850: /* I/O map type register */ sysctrl->contiguous_map = val & 0x01; qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map); break; default: printf("ERROR: unaffected IO port write: %04" PRIx32 " => %02" PRIx32"\n", addr, val); break; } }
static void at91_pmc_update_irq(PMCState *s) { qemu_set_irq(s->parent_irq, !!(s->sr & s->imr)); }
static void gptm_update_irq(gptm_state *s) { int level; level = (s->state & s->mask) != 0; qemu_set_irq(s->irq, level); }
static void r2d_pci_set_irq(qemu_irq *p, int n, int l) { qemu_set_irq(p[n], l); }
static void pci_vpb_set_irq(void *opaque, int irq_num, int level) { qemu_irq *pic = opaque; qemu_set_irq(pic[irq_num], level); }
static void sh_serial_write(void *opaque, uint32_t offs, uint32_t val) { sh_serial_state *s = opaque; unsigned char ch; #ifdef DEBUG_SERIAL printf("sh_serial: write offs=0x%02x val=0x%02x\n", offs, val); #endif switch(offs) { case 0x00: /* SMR */ s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff); return; case 0x04: /* BRR */ s->brr = val; return; case 0x08: /* SCR */ /* TODO : For SH7751, SCIF mask should be 0xfb. */ s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff); if (!(val & (1 << 5))) s->flags |= SH_SERIAL_FLAG_TEND; if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) { qemu_set_irq(s->txi, val & (1 << 7)); } if (!(val & (1 << 6))) { qemu_set_irq(s->rxi, 0); } return; case 0x0c: /* FTDR / TDR */ if (s->chr) { ch = val; qemu_chr_fe_write(s->chr, &ch, 1); } s->dr = val; s->flags &= ~SH_SERIAL_FLAG_TDE; return; #if 0 case 0x14: /* FRDR / RDR */ ret = 0; break; #endif } if (s->feat & SH_SERIAL_FEAT_SCIF) { switch(offs) { case 0x10: /* FSR */ if (!(val & (1 << 6))) s->flags &= ~SH_SERIAL_FLAG_TEND; if (!(val & (1 << 5))) s->flags &= ~SH_SERIAL_FLAG_TDE; if (!(val & (1 << 4))) s->flags &= ~SH_SERIAL_FLAG_BRK; if (!(val & (1 << 1))) s->flags &= ~SH_SERIAL_FLAG_RDF; if (!(val & (1 << 0))) s->flags &= ~SH_SERIAL_FLAG_DR; if (!(val & (1 << 1)) || !(val & (1 << 0))) { if (s->rxi) { qemu_set_irq(s->rxi, 0); } } return; case 0x18: /* FCR */ s->fcr = val; switch ((val >> 6) & 3) { case 0: s->rtrg = 1; break; case 1: s->rtrg = 4; break; case 2: s->rtrg = 8; break; case 3: s->rtrg = 14; break; } if (val & (1 << 1)) { sh_serial_clear_fifo(s); s->sr &= ~(1 << 1); } return; case 0x20: /* SPTR */ s->sptr = val & 0xf3; return; case 0x24: /* LSR */ return; } } else { switch(offs) {
static void exynos4210_gic_set_irq(void *opaque, int irq, int level) { Exynos4210GicState *s = (Exynos4210GicState *)opaque; qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); }
static void arm_sysctl_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) { arm_sysctl_state *s = (arm_sysctl_state *)opaque; switch (offset) { case 0x08: /* LED */ s->leds = val; break; case 0x0c: /* OSC0 */ case 0x10: /* OSC1 */ case 0x14: /* OSC2 */ case 0x18: /* OSC3 */ case 0x1c: /* OSC4 */ /* ??? */ break; case 0x20: /* LOCK */ if (val == LOCK_VALUE) s->lockval = val; else s->lockval = val & 0x7fff; break; case 0x28: /* CFGDATA1 */ /* ??? Need to implement this. */ s->cfgdata1 = val; break; case 0x2c: /* CFGDATA2 */ /* ??? Need to implement this. */ s->cfgdata2 = val; break; case 0x30: /* FLAGSSET */ s->flags |= val; break; case 0x34: /* FLAGSCLR */ s->flags &= ~val; break; case 0x38: /* NVFLAGSSET */ s->nvflags |= val; break; case 0x3c: /* NVFLAGSCLR */ s->nvflags &= ~val; break; case 0x40: /* RESETCTL */ switch (board_id(s)) { case BOARD_ID_PB926: if (s->lockval == LOCK_VALUE) { s->resetlevel = val; if (val & 0x100) { qemu_system_reset_request(); } } break; case BOARD_ID_PBX: case BOARD_ID_PBA8: if (s->lockval == LOCK_VALUE) { s->resetlevel = val; if (val & 0x04) { qemu_system_reset_request(); } } break; case BOARD_ID_VEXPRESS: case BOARD_ID_EB: default: /* reserved: RAZ/WI */ break; } break; case 0x44: /* PCICTL */ /* nothing to do. */ break; case 0x4c: /* FLASH */ break; case 0x50: /* CLCD */ switch (board_id(s)) { case BOARD_ID_PB926: /* On 926 bits 13:8 are R/O, bits 1:0 control * the mux that defines how to interpret the PL110 * graphics format, and other bits are r/w but we * don't implement them to do anything. */ s->sys_clcd &= 0x3f00; s->sys_clcd |= val & ~0x3f00; qemu_set_irq(s->pl110_mux_ctrl, val & 3); break; case BOARD_ID_EB: /* The EB is the same except that there is no mux since * the EB has a PL111. */ s->sys_clcd &= 0x3f00; s->sys_clcd |= val & ~0x3f00; break; case BOARD_ID_PBA8: case BOARD_ID_PBX: /* On PBA8 and PBX bit 7 is r/w and all other bits * are either r/o or RAZ/WI. */ s->sys_clcd &= (1 << 7); s->sys_clcd |= val & ~(1 << 7); break; case BOARD_ID_VEXPRESS: default: /* On VExpress this register is unimplemented and will RAZ/WI */ break; } break; case 0x54: /* CLCDSER */ case 0x64: /* DMAPSR0 */ case 0x68: /* DMAPSR1 */ case 0x6c: /* DMAPSR2 */ case 0x70: /* IOSEL */ case 0x74: /* PLDCTL */ case 0x80: /* BUSID */ case 0x84: /* PROCID0 */ case 0x88: /* PROCID1 */ case 0x8c: /* OSCRESET0 */ case 0x90: /* OSCRESET1 */ case 0x94: /* OSCRESET2 */ case 0x98: /* OSCRESET3 */ case 0x9c: /* OSCRESET4 */ break; case 0xa0: /* SYS_CFGDATA */ if (board_id(s) != BOARD_ID_VEXPRESS) { goto bad_reg; } s->sys_cfgdata = val; return; case 0xa4: /* SYS_CFGCTRL */ if (board_id(s) != BOARD_ID_VEXPRESS) { goto bad_reg; } /* Undefined bits [19:18] are RAZ/WI, and writing to * the start bit just triggers the action; it always reads * as zero. */ s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31)); if (val & (1 << 31)) { /* Start bit set -- actually do something */ unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4); unsigned int function = extract32(s->sys_cfgctrl, 20, 6); unsigned int site = extract32(s->sys_cfgctrl, 16, 2); unsigned int position = extract32(s->sys_cfgctrl, 12, 4); unsigned int device = extract32(s->sys_cfgctrl, 0, 12); s->sys_cfgstat = 1; /* complete */ if (s->sys_cfgctrl & (1 << 30)) { if (!vexpress_cfgctrl_write(s, dcc, function, site, position, device, s->sys_cfgdata)) { s->sys_cfgstat |= 2; /* error */ } } else { uint32_t val; if (!vexpress_cfgctrl_read(s, dcc, function, site, position, device, &val)) { s->sys_cfgstat |= 2; /* error */ } else { s->sys_cfgdata = val; } } } s->sys_cfgctrl &= ~(1 << 31); return; case 0xa8: /* SYS_CFGSTAT */ if (board_id(s) != BOARD_ID_VEXPRESS) { goto bad_reg; } s->sys_cfgstat = val & 3; return; default: bad_reg: qemu_log_mask(LOG_GUEST_ERROR, "arm_sysctl_write: Bad register offset 0x%x\n", (int)offset); return; } }
static void prep_set_irq(qemu_irq *pic, int irq_num, int level) { qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level); }
static void pl031_update(pl031_state *s) { qemu_set_irq(s->irq, s->is & s->im); }
static void pci_vpb_set_irq(qemu_irq *pic, int irq_num, int level) { qemu_set_irq(pic[pci_vpb_irq + irq_num], level); }
static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s) { qemu_set_irq(s->irq, s->irqst & s->irqen); }
void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active) { qemu_set_irq(env->irq_inputs[env->config->timerint[id]], active); }
static void r2d_pci_set_irq(void *opaque, int n, int l) { qemu_irq *p = opaque; qemu_set_irq(p[n], l); }
static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { IMXSPIState *s = opaque; uint32_t index = offset >> 2; uint32_t change_mask; if (index >= ECSPI_MAX) { qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset); return; } DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index), (uint32_t)value); change_mask = s->regs[index] ^ value; switch (index) { case ECSPI_RXDATA: qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to write to RX FIFO\n", TYPE_IMX_SPI, __func__); break; case ECSPI_TXDATA: case ECSPI_MSGDATA: /* Is there any difference between TXDATA and MSGDATA ? */ /* I'll have to look in the linux driver */ if (!imx_spi_is_enabled(s)) { /* Ignore writes if device is disabled */ break; } else if (fifo32_is_full(&s->tx_fifo)) { /* Ignore writes if queue is full */ break; } fifo32_push(&s->tx_fifo, (uint32_t)value); if (imx_spi_channel_is_master(s) && (s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC)) { /* * Start emitting if current channel is master and SMC bit is * set. */ imx_spi_flush_txfifo(s); } break; case ECSPI_STATREG: /* the RO and TC bits are write-one-to-clear */ value &= ECSPI_STATREG_RO | ECSPI_STATREG_TC; s->regs[ECSPI_STATREG] &= ~value; break; case ECSPI_CONREG: s->regs[ECSPI_CONREG] = value; if (!imx_spi_is_enabled(s)) { /* device is disabled, so this is a reset */ imx_spi_reset(DEVICE(s)); return; } if (imx_spi_channel_is_master(s)) { int i; /* We are in master mode */ for (i = 0; i < 4; i++) { qemu_set_irq(s->cs_lines[i], i == imx_spi_selected_channel(s) ? 0 : 1); } if ((value & change_mask & ECSPI_CONREG_SMC) && !fifo32_is_empty(&s->tx_fifo)) { /* SMC bit is set and TX FIFO has some slots filled in */ imx_spi_flush_txfifo(s); } else if ((value & change_mask & ECSPI_CONREG_XCH) && !(value & ECSPI_CONREG_SMC)) { /* This is a request to start emitting */ imx_spi_flush_txfifo(s); } } break; default: s->regs[index] = value; break; } imx_spi_update_irq(s); }
static void atlantronic_usart_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) { struct atlantronic_usart_state* s = opaque; switch(offset) { case offsetof(USART_TypeDef, SR): s->usart.SR &= (val | 0xfffffc9f); break; case offsetof(USART_TypeDef, DR): // usart actif et transmission activée if( (s->usart.CR1 & USART_CR1_UE) && (s->usart.CR1 & USART_CR1_TE)) { // mode half duplex et reception activée if( (s->usart.CR3 & USART_CR3_HDSEL ) && (s->usart.CR1 & USART_CR1_RE) ) { s->usart.DR = val & 0x1ff; s->usart.SR |= USART_SR_RXNE; if( s->usart.CR1 & USART_CR1_RXNEIE ) { // it reception : un octet a lire qemu_set_irq(s->irq[ATLANTRONIC_USART_IRQ_HW], 1); } if( s->usart.CR3 & USART_CR3_DMAR ) { // buffer dma de reception => it dmar : un octet a lire qemu_set_irq(s->irq[ATLANTRONIC_USART_IRQ_DMAR], 1); } } // IT device qemu_set_irq(s->irq[ATLANTRONIC_USART_IRQ_DEVICE_RX], val & 0x1ff); s->usart.SR |= USART_SR_TXE; if( s->usart.CR1 & USART_CR1_TXEIE) { // si TXEIE => it usart : on a traité l'octet qemu_set_irq(s->irq[ATLANTRONIC_USART_IRQ_HW], 1); } } break; case offsetof(USART_TypeDef, BRR): s->usart.BRR = val & 0xffff; break; case offsetof(USART_TypeDef, CR1): s->usart.CR1 = val & 0x3fff; break; case offsetof(USART_TypeDef, CR2): s->usart.CR2 = val & 0x7f7f; break; case offsetof(USART_TypeDef, CR3): s->usart.CR3 = val & 0x7ff; break; case offsetof(USART_TypeDef, GTPR): s->usart.GTPR = val & 0xffff; break; default: printf("Error : USART forbiden write acces offset %lx, val %lx\n", offset, val); break; } }
static void mipsnet_update_irq(MIPSnetState *s) { int isr = !!s->intctl; trace_mipsnet_irq(isr, s->intctl); qemu_set_irq(s->irq, isr); }
static inline void strongarm_rtc_int_update(StrongARMRTCState *s) { qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL); qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ); }
static void bcm2835_aux_update(BCM2835AuxState *s) { bool status = (s->rx_int_enable && s->read_count != 0) || s->tx_int_enable; qemu_set_irq(s->irq, status); }
static void syborg_int_update(SyborgIntState *s) { DPRINTF("pending %d\n", s->pending_count); qemu_set_irq(s->parent_irq, s->pending_count > 0); }
static void ppc4xx_pci_set_irq(qemu_irq *pci_irqs, int irq_num, int level) { DPRINTF("%s: PCI irq %d\n", __func__, irq_num); qemu_set_irq(pci_irqs[irq_num], level); }
static void omap_mmc_interrupts_update(struct omap_mmc_s *s) { qemu_set_irq(s->irq, !!(s->status & s->mask)); }
static void a15mp_priv_set_irq(void *opaque, int irq, int level) { A15MPPrivState *s = (A15MPPrivState *)opaque; qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); }
static void pmc_anlg_imr_update_irq(PmcAnalog *s) { bool pending = s->regs[R_PMC_ANLG_ISR] & ~s->regs[R_PMC_ANLG_IMR]; qemu_set_irq(s->irq_pmc_anlg_imr, pending); }
static void prep_set_irq(void *opaque, int irq_num, int level) { qemu_irq *pic = opaque; qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level); }
static void syborg_keyboard_update(SyborgKeyboardState *s) { int level = s->read_count && s->int_enabled; DPRINTF("Update IRQ %d\n", level); qemu_set_irq(s->irq, level); }
static void stellaris_enet_update(stellaris_enet_state *s) { qemu_set_irq(s->irq, (s->ris & s->im) != 0); }
static void retu_interrupt_update(CBusRetu *s) { qemu_set_irq(s->irq, s->irqst & ~s->irqen); }
static void uart_update_status(UartState *s) { s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); }