int rtltool_ioctl(struct rtl8168_private *tp, struct ifreq *ifr)
{
struct rtltool_cmd my_cmd;
unsigned long flags;
int ret;
if (copy_from_user(&my_cmd, ifr->ifr_data, sizeof(my_cmd)))
return -EFAULT;
ret = 0;
switch (my_cmd.cmd) {
case RTLTOOL_READ_MAC:
if (!capable(CAP_NET_ADMIN))
return -EPERM;
if (my_cmd.len==1)
my_cmd.data = readb(tp->mmio_addr+my_cmd.offset);
else if (my_cmd.len==2)
my_cmd.data = readw(tp->mmio_addr+(my_cmd.offset&~1));
else if (my_cmd.len==4)
my_cmd.data = readl(tp->mmio_addr+(my_cmd.offset&~3));
else {
ret = -EOPNOTSUPP;
break;
}
if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) {
ret = -EFAULT;
break;
}
break;
case RTLTOOL_WRITE_MAC:
if (!capable(CAP_NET_ADMIN))
return -EPERM;
if (my_cmd.len==1)
writeb(my_cmd.data, tp->mmio_addr+my_cmd.offset);
else if (my_cmd.len==2)
writew(my_cmd.data, tp->mmio_addr+(my_cmd.offset&~1));
else if (my_cmd.len==4)
writel(my_cmd.data, tp->mmio_addr+(my_cmd.offset&~3));
else {
ret = -EOPNOTSUPP;
break;
}
break;
case RTLTOOL_READ_PHY:
if (!capable(CAP_NET_ADMIN))
return -EPERM;
spin_lock_irqsave(&tp->phy_lock, flags);
my_cmd.data = mdio_read(tp, my_cmd.offset);
spin_unlock_irqrestore(&tp->phy_lock, flags);
if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) {
ret = -EFAULT;
break;
}
break;
case RTLTOOL_WRITE_PHY:
if (!capable(CAP_NET_ADMIN))
return -EPERM;
spin_lock_irqsave(&tp->phy_lock, flags);
mdio_write(tp, my_cmd.offset, my_cmd.data);
spin_unlock_irqrestore(&tp->phy_lock, flags);
break;
case RTLTOOL_READ_EPHY:
if (!capable(CAP_NET_ADMIN))
return -EPERM;
my_cmd.data = rtl8168_ephy_read(tp->mmio_addr, my_cmd.offset);
if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) {
ret = -EFAULT;
break;
}
break;
case RTLTOOL_WRITE_EPHY:
if (!capable(CAP_NET_ADMIN))
return -EPERM;
rtl8168_ephy_write(tp->mmio_addr, my_cmd.offset, my_cmd.data);
break;
case RTLTOOL_READ_PCI:
if (!capable(CAP_NET_ADMIN))
return -EPERM;
my_cmd.data = 0;
if (my_cmd.len==1)
pci_read_config_byte(tp->pci_dev, my_cmd.offset,
(u8 *)&my_cmd.data);
else if (my_cmd.len==2)
pci_read_config_word(tp->pci_dev, my_cmd.offset,
(u16 *)&my_cmd.data);
else if (my_cmd.len==4)
pci_read_config_dword(tp->pci_dev, my_cmd.offset,
&my_cmd.data);
else {
ret = -EOPNOTSUPP;
break;
}
if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) {
ret = -EFAULT;
break;
}
break;
case RTLTOOL_WRITE_PCI:
if (!capable(CAP_NET_ADMIN))
return -EPERM;
if (my_cmd.len==1)
pci_write_config_byte(tp->pci_dev, my_cmd.offset,
my_cmd.data);
else if (my_cmd.len==2)
pci_write_config_word(tp->pci_dev, my_cmd.offset,
my_cmd.data);
else if (my_cmd.len==4)
pci_write_config_dword(tp->pci_dev, my_cmd.offset,
my_cmd.data);
else {
ret = -EOPNOTSUPP;
break;
}
break;
case RTLTOOL_READ_EEPROM:
if (!capable(CAP_NET_ADMIN))
return -EPERM;
my_cmd.data = rtl_eeprom_read_sc(tp, my_cmd.offset);
if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) {
ret = -EFAULT;
break;
}
break;
case RTLTOOL_WRITE_EEPROM:
if (!capable(CAP_NET_ADMIN))
return -EPERM;
rtl_eeprom_write_sc(tp->mmio_addr, my_cmd.offset, my_cmd.data);
break;
case RTL_ARP_NS_OFFLOAD:
break;
case RTL_SET_OOB_IPMAC:
ret = OOB_set_ip_mac(tp,
(struct sockaddr_in *)&my_cmd.ifru_addr,
my_cmd.ifru_hwaddr.sa_data);
break;
case RTL_READ_OOB_MAC:
if (!capable(CAP_NET_ADMIN))
return -EPERM;
my_cmd.data = OCP_read(tp, 0xf, my_cmd.offset);
if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) {
ret = -EFAULT;
break;
}
break;
break;
case RTL_WRITE_OOB_MAC:
if (!capable(CAP_NET_ADMIN))
return -EPERM;
OOB_mutex_lock(tp);
if (my_cmd.len == 1)
OCP_write(tp, 0x1, my_cmd.offset, my_cmd.data);
else if (my_cmd.len == 2)
OCP_write(tp, 0x3, my_cmd.offset, my_cmd.data);
else if (my_cmd.len == 4)
OCP_write(tp, 0xf, my_cmd.offset, my_cmd.data);
else {
ret = -EOPNOTSUPP;
}
OOB_mutex_unlock(tp);
break;
break;
default:
ret = -EOPNOTSUPP;
break;
}
return ret;
}
/* Display Register dump */
void calypso_sim_regdump(void)
{
#ifdef DEBUG
unsigned int regVal;
#define SIM_DEBUG_OUTPUTDELAY 200
puts("\n\n\n");
puts("====================== CALYPSO SIM REGISTER DUMP =====================\n");
puts("Reg_sim_cmd register (R/W) - FFFE:0000\n");
regVal = readw(REG_SIM_CMD);
printf(" |-REG_SIM_CMD = %04x\n", readw(REG_SIM_CMD));
if(regVal & REG_SIM_CMD_CMDCARDRST)
puts(" | |-REG_SIM_CMD_CMDCARDRST = 1 ==> SIM card reset sequence enabled.\n");
else
puts(" | |-REG_SIM_CMD_CMDCARDRST = 0 ==> SIM card reset sequence disabled.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_CMD_CMDIFRST)
puts(" | |-REG_SIM_CMD_CMDIFRST = 1\n");
else
puts(" | |-REG_SIM_CMD_CMDIFRST = 0\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_CMD_CMDSTOP)
puts(" | |-REG_SIM_CMD_CMDSTOP = 1\n");
else
puts(" | |-REG_SIM_CMD_CMDSTOP = 0\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_CMD_CMDSTART)
puts(" | |-REG_SIM_CMD_CMDSTART = 1 ==> SIM card start procedure active.\n");
else
puts(" | |-REG_SIM_CMD_CMDSTART = 0\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_CMD_CMDSTART)
puts(" | |-REG_SIM_CMD_MODULE_CLK_EN = 1 ==> Clock of the module enabled.\n");
else
puts(" | |-REG_SIM_CMD_MODULE_CLK_EN = 0 ==> Clock of the module disabled.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
regVal = readw(REG_SIM_STAT);
printf(" |-REG_SIM_STAT = %04x\n", regVal);
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_STAT_STATNOCARD)
puts(" | |-REG_SIM_STAT_STATNOCARD = 1 ==> No card!\n");
else
puts(" | |-REG_SIM_STAT_STATNOCARD = 0 ==> Card detected!\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_STAT_STATTXPAR)
puts(" | |-REG_SIM_STAT_STATTXPAR = 1 ==> Parity ok!\n");
else
puts(" | |-REG_SIM_STAT_STATTXPAR = 0 ==> Parity error!\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_STAT_STATFIFOFULL)
puts(" | |-REG_SIM_STAT_STATFIFOFULL = 1 ==> Fifo full!\n");
else
puts(" | |-REG_SIM_STAT_STATFIFOFULL = 0\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_STAT_STATFIFOEMPTY)
puts(" | |-REG_SIM_STAT_STATFIFOEMPTY = 1 ==> Fifo empty!\n");
else
puts(" | |-REG_SIM_STAT_STATFIFOEMPTY = 0\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
regVal = readw(REG_SIM_CONF1);
printf(" |-REG_SIM_CONF1 = %04x\n", regVal);
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_CONF1_CONFCHKPAR)
puts(" | |-REG_SIM_CONF1_CONFCHKPAR = 1 ==> Parity check on reception enabled.\n");
else
puts(" | |-REG_SIM_CONF1_CONFCHKPAR = 0 ==> Parity check on reception disabled.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_CONF1_CONFCODCONV)
puts(" | |-REG_SIM_CONF1_CONFCODCONV = 1 ==> Coding convention is inverse.\n");
else
puts(" | |-REG_SIM_CONF1_CONFCODCONV = 0 ==> Coding convention is direct (normal).\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_CONF1_CONFTXRX)
puts(" | |-REG_SIM_CONF1_CONFTXRX = 1 ==> SIO line direction is in transmit mode.\n");
else
puts(" | |-REG_SIM_CONF1_CONFTXRX = 0 ==> SIO line direction is in receive mode.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_CONF1_CONFSCLKEN)
puts(" | |-REG_SIM_CONF1_CONFSCLKEN = 1 ==> SIM clock in normal mode.\n");
else
puts(" | |-REG_SIM_CONF1_CONFSCLKEN = 0 ==> SIM clock in standby mode.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_CONF1_reserved)
puts(" | |-REG_SIM_CONF1_reserved = 1 ==> ETU period is 4*1/Fsclk.\n");
else
puts(" | |-REG_SIM_CONF1_reserved = 0 ==> ETU period is CONFETUPERIOD.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_CONF1_CONFSCLKDIV)
puts(" | |-REG_SIM_CONF1_CONFSCLKDIV = 1 ==> SIM clock frequency is 13/8 Mhz.\n");
else
puts(" | |-REG_SIM_CONF1_CONFSCLKDIV = 0 ==> SIM clock frequency is 13/4 Mhz.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_CONF1_CONFSCLKLEV)
puts(" | |-REG_SIM_CONF1_CONFSCLKLEV = 1 ==> SIM clock idle level is high.\n");
else
puts(" | |-REG_SIM_CONF1_CONFSCLKLEV = 0 ==> SIM clock idle level is low.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_CONF1_CONFETUPERIOD)
puts(" | |-REG_SIM_CONF1_CONFETUPERIOD = 1 ==> ETU period is 512/8*1/Fsclk.\n");
else
puts(" | |-REG_SIM_CONF1_CONFETUPERIOD = 0 ==> ETU period is 372/8*1/Fsclk.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_CONF1_CONFBYPASS)
puts(" | |-REG_SIM_CONF1_CONFBYPASS = 1 ==> Hardware timers and start and stop sequences are bypassed.\n");
else
puts(" | |-REG_SIM_CONF1_CONFBYPASS = 0 ==> Hardware timers and start and stop sequences are normal.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_CONF1_CONFSVCCLEV)
puts(" | |-REG_SIM_CONF1_CONFSVCCLEV = 1 ==> SVCC Level is high (Only valid when CONFBYPASS = 1).\n");
else
puts(" | |-REG_SIM_CONF1_CONFSVCCLEV = 0 ==> SVCC Level is low (Only valid when CONFBYPASS = 1).\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_CONF1_CONFSRSTLEV)
puts(" | |-REG_SIM_CONF1_CONFSRSTLEV = 1 ==> SRST Level is high (Only valid when CONFBYPASS = 1).\n");
else
puts(" | |-REG_SIM_CONF1_CONFSRSTLEV = 0 ==> SRST Level is low (Only valid when CONFBYPASS = 1).\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
printf(" | |-REG_SIM_CONF1_CONFTRIG = 0x%x (FIFO trigger level)\n",(regVal >> REG_SIM_CONF1_CONFTRIG) & REG_SIM_CONF1_CONFTRIG_MASK);
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_CONF1_CONFSIOLOW)
puts(" | |-REG_SIM_CONF1_CONFSIOLOW = 1 ==> I/O is forced to low.\n");
else
puts(" | |-REG_SIM_CONF1_CONFSIOLOW = 0\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
regVal = readw(REG_SIM_CONF2);
printf(" |-REG_SIM_CONF2 = %04x\n", regVal);
printf(" | |-REG_SIM_CONF2_CONFTFSIM = 0x%x (time delay for filtering of SIM_CD)\n",(regVal >> REG_SIM_CONF2_CONFTFSIM) & REG_SIM_CONF2_CONFTFSIM_MASK);
printf(" | |-REG_SIM_CONF2_CONFTDSIM = 0x%x (time delay for contact activation/deactivation)\n",(regVal >> REG_SIM_CONF2_CONFTDSIM) & REG_SIM_CONF2_CONFTDSIM_MASK);
printf(" | |-REG_SIM_CONF2_CONFWAITI = 0x%x (CONFWAITI overflow wait time between two received chars)\n",(regVal >> REG_SIM_CONF2_CONFWAITI) & REG_SIM_CONF2_CONFWAITI_MASK);
delay_ms(SIM_DEBUG_OUTPUTDELAY);
regVal = readw(REG_SIM_IT);
printf(" |-REG_SIM_IT = %04x\n", regVal);
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_IT_SIM_NATR)
puts(" | |-REG_SIM_IT_SIM_NATR = 1 ==> No answer to reset!\n");
else
puts(" | |-REG_SIM_IT_SIM_NATR = 0 ==> On read access to REG_SIM_IT.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_IT_SIM_WT)
puts(" | |-REG_SIM_IT_SIM_WT = 1 ==> Character underflow!\n");
else
puts(" | |-REG_SIM_IT_SIM_WT = 0 ==> On read access to REG_SIM_IT.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_IT_SIM_OV)
puts(" | |-REG_SIM_IT_SIM_OV = 1 ==> Receive overflow!\n");
else
puts(" | |-REG_SIM_IT_SIM_OV = 0 ==> On read access to REG_SIM_IT.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_IT_SIM_TX)
puts(" | |-REG_SIM_IT_SIM_TX = 1 ==> Waiting for character to transmit...\n");
else
{
puts(" | |-REG_SIM_IT_SIM_TX = 0 ==> On write access to REG_SIM_DTX or on switching\n");
puts(" | | from transmit to receive mode (CONFTXRX bit)\n");
}
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_IT_SIM_RX)
puts(" | |-REG_SIM_IT_SIM_RX = 1 ==> Waiting characters to be read...\n");
else
puts(" | |-REG_SIM_IT_SIM_RX = 0 ==> On read access to REG_SIM_DRX.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
regVal = readw(REG_SIM_DRX);
printf(" |-REG_SIM_DRX = %04x\n", regVal);
delay_ms(SIM_DEBUG_OUTPUTDELAY);
printf(" | |-REG_SIM_DRX_SIM_DRX = 0x%x (next data byte in FIFO available for reading)\n",(regVal >> REG_SIM_DRX_SIM_DRX) & REG_SIM_DRX_SIM_DRX_MASK);
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_DRX_STATRXPAR)
puts(" | |-REG_SIM_DRX_STATRXPAR = 1 ==> Parity Ok.\n");
else
puts(" | |-REG_SIM_DRX_STATRXPAR = 0 ==> Parity error!\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
regVal = readw(REG_SIM_DTX);
printf(" |-REG_SIM_DTX = %02x (next data byte to be transmitted)\n", regVal);
delay_ms(SIM_DEBUG_OUTPUTDELAY);
regVal = readw(REG_SIM_MASKIT);
printf(" |-REG_SIM_MASKIT = %04x\n", regVal);
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_MASKIT_MASK_SIM_NATR)
puts(" | |-REG_SIM_MASKIT_MASK_SIM_NATR = 1 ==> No-answer-to-reset interrupt is masked.\n");
else
puts(" | |-REG_SIM_MASKIT_MASK_SIM_NATR = 0 ==> No-answer-to-reset interrupt is unmasked.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_MASKIT_MASK_SIM_WT)
puts(" | |-REG_SIM_MASKIT_MASK_SIM_WT = 1 ==> Character wait-time overflow interrupt is masked.\n");
else
puts(" | |-REG_SIM_MASKIT_MASK_SIM_WT = 0 ==> Character wait-time overflow interrupt is unmasked.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_MASKIT_MASK_SIM_OV)
puts(" | |-REG_SIM_MASKIT_MASK_SIM_OV = 1 ==> Receive overflow interrupt is masked.\n");
else
puts(" | |-REG_SIM_MASKIT_MASK_SIM_OV = 0 ==> Receive overflow interrupt is unmasked.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_MASKIT_MASK_SIM_TX)
puts(" | |-REG_SIM_MASKIT_MASK_SIM_TX = 1 ==> Waiting characters to be transmit interrupt is masked.\n");
else
puts(" | |-REG_SIM_MASKIT_MASK_SIM_TX = 0 ==> Waiting characters to be transmit interrupt is unmasked.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_MASKIT_MASK_SIM_RX)
puts(" | |-REG_SIM_MASKIT_MASK_SIM_RX = 1 ==> Waiting characters to be read interrupt is masked.\n");
else
puts(" | |-REG_SIM_MASKIT_MASK_SIM_RX = 0 ==> Waiting characters to be read interrupt is unmasked.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
if(regVal & REG_SIM_MASKIT_MASK_SIM_CD)
puts(" | |-REG_SIM_MASKIT_MASK_SIM_CD = 1 ==> SIM card insertion/extraction interrupt is masked.\n");
else
puts(" | |-REG_SIM_MASKIT_MASK_SIM_CD = 0 ==> SIM card insertion/extraction interrupt is unmasked.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
regVal = REG_SIM_IT_CD;
printf(" |-REG_SIM_IT_CD = %04x\n", regVal);
if(regVal & REG_SIM_IT_CD_IT_CD)
puts(" |-REG_SIM_IT_CD_IT_CD = 1 ==> SIM card insertion/extraction interrupt is masked.\n");
else
puts(" |-REG_SIM_IT_CD_IT_CD = 0 ==> SIM card insertion/extraction interrupt is unmasked.\n");
delay_ms(SIM_DEBUG_OUTPUTDELAY);
#endif
return;
}
static int __devinit
rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct net_device *dev;
struct netdev_private *np;
static int card_idx;
int chip_idx = ent->driver_data;
int err, irq;
long ioaddr;
static int version_printed;
void *ring_space;
dma_addr_t ring_dma;
if (!version_printed++)
printk ("%s", version);
err = pci_enable_device (pdev);
if (err)
return err;
irq = pdev->irq;
err = pci_request_regions (pdev, "dl2k");
if (err)
goto err_out_disable;
pci_set_master (pdev);
dev = alloc_etherdev (sizeof (*np));
if (!dev) {
err = -ENOMEM;
goto err_out_res;
}
SET_NETDEV_DEV(dev, &pdev->dev);
#ifdef MEM_MAPPING
ioaddr = pci_resource_start (pdev, 1);
ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
if (!ioaddr) {
err = -ENOMEM;
goto err_out_dev;
}
#else
ioaddr = pci_resource_start (pdev, 0);
#endif
dev->base_addr = ioaddr;
dev->irq = irq;
np = netdev_priv(dev);
np->chip_id = chip_idx;
np->pdev = pdev;
spin_lock_init (&np->tx_lock);
spin_lock_init (&np->rx_lock);
/* Parse manual configuration */
np->an_enable = 1;
np->tx_coalesce = 1;
if (card_idx < MAX_UNITS) {
if (media[card_idx] != NULL) {
np->an_enable = 0;
if (strcmp (media[card_idx], "auto") == 0 ||
strcmp (media[card_idx], "autosense") == 0 ||
strcmp (media[card_idx], "0") == 0 ) {
np->an_enable = 2;
} else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
strcmp (media[card_idx], "4") == 0) {
np->speed = 100;
np->full_duplex = 1;
} else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
strcmp (media[card_idx], "3") == 0) {
np->speed = 100;
np->full_duplex = 0;
} else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
strcmp (media[card_idx], "2") == 0) {
np->speed = 10;
np->full_duplex = 1;
} else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
strcmp (media[card_idx], "1") == 0) {
np->speed = 10;
np->full_duplex = 0;
} else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
strcmp (media[card_idx], "6") == 0) {
np->speed=1000;
np->full_duplex=1;
} else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
strcmp (media[card_idx], "5") == 0) {
np->speed = 1000;
np->full_duplex = 0;
} else {
np->an_enable = 1;
}
}
if (jumbo[card_idx] != 0) {
np->jumbo = 1;
dev->mtu = MAX_JUMBO;
} else {
np->jumbo = 0;
if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
dev->mtu = mtu[card_idx];
}
np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
vlan[card_idx] : 0;
if (rx_coalesce > 0 && rx_timeout > 0) {
np->rx_coalesce = rx_coalesce;
np->rx_timeout = rx_timeout;
np->coalesce = 1;
}
np->tx_flow = (tx_flow == 0) ? 0 : 1;
np->rx_flow = (rx_flow == 0) ? 0 : 1;
if (tx_coalesce < 1)
tx_coalesce = 1;
else if (tx_coalesce > TX_RING_SIZE-1)
tx_coalesce = TX_RING_SIZE - 1;
}
dev->netdev_ops = &netdev_ops;
dev->watchdog_timeo = TX_TIMEOUT;
SET_ETHTOOL_OPS(dev, ðtool_ops);
#if 0
dev->features = NETIF_F_IP_CSUM;
#endif
pci_set_drvdata (pdev, dev);
ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
if (!ring_space)
goto err_out_iounmap;
np->tx_ring = (struct netdev_desc *) ring_space;
np->tx_ring_dma = ring_dma;
ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
if (!ring_space)
goto err_out_unmap_tx;
np->rx_ring = (struct netdev_desc *) ring_space;
np->rx_ring_dma = ring_dma;
/* Parse eeprom data */
parse_eeprom (dev);
/* Find PHY address */
err = find_miiphy (dev);
if (err)
goto err_out_unmap_rx;
/* Fiber device? */
np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
np->link_status = 0;
/* Set media and reset PHY */
if (np->phy_media) {
/* default Auto-Negotiation for fiber deivices */
if (np->an_enable == 2) {
np->an_enable = 1;
}
mii_set_media_pcs (dev);
} else {
/* Auto-Negotiation is mandatory for 1000BASE-T,
IEEE 802.3ab Annex 28D page 14 */
if (np->speed == 1000)
np->an_enable = 1;
mii_set_media (dev);
}
err = register_netdev (dev);
if (err)
goto err_out_unmap_rx;
card_idx++;
printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
dev->name, np->name, dev->dev_addr, irq);
if (tx_coalesce > 1)
printk(KERN_INFO "tx_coalesce:\t%d packets\n",
tx_coalesce);
if (np->coalesce)
printk(KERN_INFO
"rx_coalesce:\t%d packets\n"
"rx_timeout: \t%d ns\n",
np->rx_coalesce, np->rx_timeout*640);
if (np->vlan)
printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
return 0;
err_out_unmap_rx:
pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
err_out_unmap_tx:
pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
err_out_iounmap:
#ifdef MEM_MAPPING
iounmap ((void *) ioaddr);
err_out_dev:
#endif
free_netdev (dev);
err_out_res:
pci_release_regions (pdev);
err_out_disable:
pci_disable_device (pdev);
return err;
}
/**
* load_ani() - loads an animation
* @nr: number of the animation
*/
void Cseg027::load_ani(const signed short nr)
{
struct sm_file smf;
unsigned short bytes;
Bit32u off_imdata, off_palette;
Bit16u width, height;
Bit8u compression_type;
Bit8u palette_size;
Bit8u num_elements;
int off_elements;
Bit8u* ptr_elements;
//signed int area_size;
int len;
signed int len_3, len_4;
unsigned int offset, offset_2;
Bit8u *dst, *p6;
int ani_off, ani_len;/*
Bit8u *p5;
signed int p4;
signed int p3;*/
Bit8u *p2;
Bit8u *p1;
Bit32u ani_buffer;
Bit8u *ani_main_ptr;
Bit8u *palette_ptr;
/*
unsigned short ems_handle;
Bit8u *p_area;
unsigned short i;
unsigned short fd;
signed short area_changes;
signed short area_pics;
unsigned short i_area;
signed short di;
/* sanity check */
if (nr == -1)
return;
if (nr > 36)
return;
/* no need to reload the same ani*/
//if (nr == globvars->current_ani)
// return;
//ds_writew(0x29ae, 0);
/* set the new ani nr*/
globvars->current_ani=nr;
/* clear the old ani */
//clear_ani(); seg004
if (!anis_loaded[nr-1]){
/* load ANIS.TAB */
load_archive_file(0x17,&smf);
bytes = read_archive_file(&smf, buffer, 148);
fclose(smf.fd);
ani_off = readd(buffer - 4 + nr * 4);
ani_len = readd(buffer + nr * 4) - ani_off;
/* load ANIS */
load_archive_file(0x16,&smf);//fd = load_archive_file(0x16);
/* seek to ordered ani */
fseek(smf.fd, smf.off + ani_off, SEEK_SET);//seg002_0c72(fd, ani_off);
bytes = read_archive_file(&smf, buffer, (unsigned short)ani_len);//fd, Real2Host(ds_readd(0xc3db)),
fclose(smf.fd);
off_imdata = readd(buffer);//ds_readd(0xc3db);
off_palette = readd(buffer+4);
width = readw(buffer+8);
height = readb(buffer+10);
num_elements = readb(buffer+11);
//für jedes Element:
off_elements = readd(buffer+12);
ptr_elements = buffer + off_elements;
//posx = readw(ptr_elements+4);
//posy = readb(ptr_elements+6);
//width = readb(ptr_elements+7);
//height = readb(ptr_elements+8);
//anz = readb(ptr_elements+11);
//for i<anz
//posx = readb(ptr_elements+12+i*4);
//posy = readb(ptr_elements+12+i*4+1);
//anzanim = readw(ptr_elements+12+anz*4);
//for i<anzanim
//index = readw(ptr_elements+12+anz*4 + 4*i);
//delay = readw(ptr_elements+12+anz*4 + 4*i+2);
/* set start of picture data */
ani_main_ptr = buffer + off_imdata;
//ds_writed(ANI_MAIN_PTR,
//host_readd(Real2Host(ds_readd(0xc3db))) + ani_buffer);
/* set start of palette */
palette_ptr = buffer + off_palette + 6;//palette ist hier //??? src_rle = ani_main_ptr + readd(buffer+4) + 6;
//ds_writed(0xce3b,
//host_readd(Real2Host(ds_readd(0xc3db)) + 4) + ani_buffer + 6);
/* read some bytes between data and palette */
//word_313A9 = readw(src_rle-6);
//ds_writew(0xc3e9,
//host_readw(Real2Host(ds_readd(0xce3b)) - 6));
//word_313AB = readw(src_rle-4);
//ds_writew(0xc3eb,
//host_readw(Real2Host(ds_readd(0xce3b)) - 4));
/* compression type */
compression_type = readw(palette_ptr-1);
//ds_writeb(0xce39,
//host_readb(Real2Host(ds_readd(0xce3b)) - 1));
/* palette size*/
palette_size = readw(palette_ptr-2);
sm_set_palette(palette_ptr,0,palette_size);
//ds_writeb(0xce3a,
//host_readb(Real2Host(ds_readd(0xce3b)) - 2));
//p6 = src_rle + palette_size * 3; //pointer auf end
/* set picture size /
00 0d
ds_writew(0xc3e7, host_readw(Real2Host(ds_readd(0xc3db) + 8)));
87
ds_writeb(0xc3ed, host_readb(Real2Host(ds_readd(0xc3db) + 10)));
/* set number of areas /
01
ds_writeb(0xc3ee, host_readb(Real2Host(ds_readd(0xc3db) + 11)));
/* Process Main Picture */
if (compression_type != 0) {
len_4 = readd(ani_main_ptr);//host_readd(Real2Host(ds_readd(ANI_MAIN_PTR)));
//p1 = ani_main_ptr;
//p1 += (len_4 - 4);
//len_3 = readd(p1);
//len_3 = swap_u32(len_3) >> 8;
decomp_pp20(ani_main_ptr,gataosao,ani_main_ptr+4,len_4);
//decomp_pp20(Real2Host(ds_readd(ANI_MAIN_PTR)),
// Real2Host(ds_readd(0xd303)),
// Real2Host(ds_readd(ANI_MAIN_PTR)) + 4,
// len_4);
//offset = len_3 - len_4;
//dst = ani_main_ptr;
//dst += len_4;
//len = p6 - dst;
//memcpy(p6 + offset, dst, len);
//memcpy(Real2Host(ds_readd(ANI_MAIN_PTR)),
//Real2Host(ds_readd(0xd303)), len_3);
//memcpy(ani_main_ptr, gataosao, len_3);
//dst += offset;
//memcpy(dst, p6 + offset, len);
//src_rle = src_rle + offset;
//ds_writed(0xce3b, ds_readd(0xce3b) + offset);
//p6 += offset;
printf("anis decompressed: %d\n",nr);
}
sm_images_init_anis(nr-1,gataosao);
anis_loaded[nr-1]=true;
printf("anis loaded: %d\n",nr);
}
/* Process the Areas */
//for (i_area = 0; (signed char)ds_readb(0xc3ee) > i_area; i_area++) {
//for (i_area = 0; i_area < num_elements; i_area++) {
//p5 = Real2Host(RealMake(datseg, 0xc3ef + i_area * 0x107));
//p3 = host_readd(Real2Host(ds_readd(0xc3db) + i_area * 4 + 0xc));
//p_area = Real2Host(ds_readd(0xc3db) + p3);
//p_area = buffer + off_elements + i_area * 4;
//strncpy((char*)p5, (char*)p_area, 4);
//host_writew(p5 + 5, host_readw(p_area + 4));
//host_writeb(p5 + 7, host_readb(p_area + 6));
//host_writeb(p5 + 8, host_readb(p_area + 7));
//host_writew(p5 + 9, host_readw(p_area + 8));
//host_writeb(p5 + 0x0b, host_readb(p_area + 0x0a));
/*
area_pics = (signed char)host_readb(p_area + 0x0b);
host_writeb(p5 + 0x0c, (unsigned char)area_pics);
if (ds_readb(0xce39) != 0) {
p4 = host_readd(p_area + 0xc);
p4 += offset;
p1 = Real2Host(ds_readd(0xc3db) + p4);
len_4 = host_readd(p1);
p1 += (len_4 - 4);
area_size = host_readd(p1);
area_size = swap_u32(area_size) >> 8;
decomp_pp20(Real2Host(ds_readd(0xc3db)) + p4,
Real2Host(ds_readd(0xd303)),
Real2Host(ds_readd(0xc3db)) + p4 + 4,
len_4);
offset_2 = area_size - len_4;
offset += offset_2;
dst = Real2Host(ds_readd(0xc3db));
dst += p4;
dst += len_4;
len = p6 - dst;
memcpy(p6 + offset_2, dst, (unsigned short)len);
memcpy(Real2Host(ds_readd(0xc3db)) + p4,
Real2Host(ds_readd(0xd303)), (unsigned short)area_size);
dst += offset_2;
memcpy(dst, p6 + offset_2, (unsigned short)len);
ds_writed(0xce3b, ds_readd(0xce3b) + offset_2);
p6 += offset_2;
area_size = (unsigned char)host_readb(p5 + 8)
* (signed short)host_readw(p5 + 9);
for (di = 0; di < area_pics; di++) {
host_writed(p5 + di * 4 + 0xd,
ds_readd(0xc3db) + p4 + di * area_size);
}
} else {
for (di = 0; di < area_pics; di++) {
p4 = host_readd(p_area + di * 4 + 0xc);
host_writed(p5 + di * 4 + 0x0d,
ds_readd(0xc3db) + p4);
}
}
/*
area_changes = host_readw(p_area + area_pics * 4 + 0x0c);
host_writew(p5 + 0x5d, area_changes);
p2 = p_area + area_pics * 4 + 0x0e;
for (di = 0; di < area_changes; di++) {
host_writew(p5 + 0x5f + di * 4,
host_readw(p2 + di * 4));
host_writew(p5 + 0x61 + di * 4,
host_readw(p2 + di * 4 + 2));
}
}
ani_len = p6 - Real2Host(ds_readd(0xc3db));
/* this is always true /
if (ani_len > (signed int)ds_readd(0xce43)) {
ds_writew(0x2ccb, 0xffff);
}*/
}
/*
* imx_keypad_check_for_events is the timer handler.
*/
static void imx_keypad_check_for_events(unsigned long data)
{
struct imx_keypad *keypad = (struct imx_keypad *) data;
unsigned short matrix_volatile_state[MAX_MATRIX_KEY_COLS];
unsigned short reg_val;
bool state_changed, is_zero_matrix;
int i;
memset(matrix_volatile_state, 0, sizeof(matrix_volatile_state));
imx_keypad_scan_matrix(keypad, matrix_volatile_state);
state_changed = false;
for (i = 0; i < MAX_MATRIX_KEY_COLS; i++) {
if ((keypad->cols_en_mask & (1 << i)) == 0)
continue;
if (keypad->matrix_unstable_state[i] ^ matrix_volatile_state[i]) {
state_changed = true;
break;
}
}
/*
* If the matrix state is changed from the previous scan
* (Re)Begin the debouncing process, saving the new state in
* keypad->matrix_unstable_state.
* else
* Increase the count of number of scans with a stable state.
*/
if (state_changed) {
memcpy(keypad->matrix_unstable_state, matrix_volatile_state,
sizeof(matrix_volatile_state));
keypad->stable_count = 0;
} else
keypad->stable_count++;
/*
* If the matrix is not as stable as we want reschedule scan
* in the near future.
*/
if (keypad->stable_count < IMX_KEYPAD_SCANS_FOR_STABILITY) {
mod_timer(&keypad->check_matrix_timer,
jiffies + msecs_to_jiffies(10));
return;
}
/*
* If the matrix state is stable, fire the events and save the new
* stable state. Note, if the matrix is kept stable for longer
* (keypad->stable_count > IMX_KEYPAD_SCANS_FOR_STABILITY) all
* events have already been generated.
*/
if (keypad->stable_count == IMX_KEYPAD_SCANS_FOR_STABILITY) {
imx_keypad_fire_events(keypad, matrix_volatile_state);
memcpy(keypad->matrix_stable_state, matrix_volatile_state,
sizeof(matrix_volatile_state));
}
is_zero_matrix = true;
for (i = 0; i < MAX_MATRIX_KEY_COLS; i++) {
if (matrix_volatile_state[i] != 0) {
is_zero_matrix = false;
break;
}
}
if (is_zero_matrix) {
/*
* All keys have been released. Enable only the KDI
* interrupt for future key presses (clear the KDI
* status bit and its sync chain before that).
*/
reg_val = readw(keypad->mmio_base + KPSR);
reg_val |= KBD_STAT_KPKD | KBD_STAT_KDSC;
writew(reg_val, keypad->mmio_base + KPSR);
reg_val = readw(keypad->mmio_base + KPSR);
reg_val |= KBD_STAT_KDIE;
reg_val &= ~KBD_STAT_KRIE;
writew(reg_val, keypad->mmio_base + KPSR);
} else {
/*
* Some keys are still pressed. Schedule a rescan in
* attempt to detect multiple key presses and enable
* the KRI interrupt to react quickly to key release
* event.
*/
mod_timer(&keypad->check_matrix_timer,
jiffies + msecs_to_jiffies(60));
reg_val = readw(keypad->mmio_base + KPSR);
reg_val |= KBD_STAT_KPKR | KBD_STAT_KRSS;
writew(reg_val, keypad->mmio_base + KPSR);
reg_val = readw(keypad->mmio_base + KPSR);
reg_val |= KBD_STAT_KRIE;
reg_val &= ~KBD_STAT_KDIE;
writew(reg_val, keypad->mmio_base + KPSR);
}
}
static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
int last)
{
struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
u16 val, tcr_val;
int ret;
unsigned long wait_result;
u32 xfer_len = 0;
if (!(pmsg->flags & I2C_M_NOSTART)) {
ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
if (ret < 0)
return ret;
}
val = readw(i2c_dev->base + REG_CR);
val &= ~CR_TX_END;
writew(val, i2c_dev->base + REG_CR);
val = readw(i2c_dev->base + REG_CR);
val &= ~CR_TX_NEXT_NO_ACK;
writew(val, i2c_dev->base + REG_CR);
if (!(pmsg->flags & I2C_M_NOSTART)) {
val = readw(i2c_dev->base + REG_CR);
val |= CR_CPU_RDY;
writew(val, i2c_dev->base + REG_CR);
}
if (pmsg->len == 1) {
val = readw(i2c_dev->base + REG_CR);
val |= CR_TX_NEXT_NO_ACK;
writew(val, i2c_dev->base + REG_CR);
}
reinit_completion(&i2c_dev->complete);
if (i2c_dev->mode == I2C_MODE_STANDARD)
tcr_val = TCR_STANDARD_MODE;
else
tcr_val = TCR_FAST_MODE;
tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
writew(tcr_val, i2c_dev->base + REG_TCR);
if (pmsg->flags & I2C_M_NOSTART) {
val = readw(i2c_dev->base + REG_CR);
val |= CR_CPU_RDY;
writew(val, i2c_dev->base + REG_CR);
}
while (xfer_len < pmsg->len) {
wait_result = wait_for_completion_timeout(&i2c_dev->complete,
msecs_to_jiffies(500));
if (!wait_result)
return -ETIMEDOUT;
ret = wmt_check_status(i2c_dev);
if (ret)
return ret;
pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
xfer_len++;
if (xfer_len == pmsg->len - 1) {
val = readw(i2c_dev->base + REG_CR);
val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY);
writew(val, i2c_dev->base + REG_CR);
} else {
val = readw(i2c_dev->base + REG_CR);
val |= CR_CPU_RDY;
writew(val, i2c_dev->base + REG_CR);
}
}
return 0;
}
static inline u16
ad1889_readw(struct snd_ad1889 *chip, unsigned reg)
{
return readw(chip->iobase + reg);
}
static __u16 sa1100_read16(struct map_info *map, unsigned long ofs)
{
return readw(map->map_priv_1 + ofs);
}
static unsigned long bgpio_read16(void __iomem *reg)
{
return readw(reg);
}
unsigned int ioread16(void __iomem *addr)
{
return readw(addr);
}
static inline int
NCR5380_pread(struct Scsi_Host *host, unsigned char *addr, int len)
{
unsigned long *laddr;
void __iomem *dma = priv(host)->dma + 0x2000;
if(!len) return 0;
writeb(0x00, priv(host)->base + CTRL);
laddr = (unsigned long *)addr;
while(len >= 32)
{
unsigned int status;
status = readb(priv(host)->base + STAT);
if(status & 0x80)
goto end;
if(!(status & 0x40))
continue;
*laddr++ = readw(dma) | (readw(dma) << 16);
*laddr++ = readw(dma) | (readw(dma) << 16);
*laddr++ = readw(dma) | (readw(dma) << 16);
*laddr++ = readw(dma) | (readw(dma) << 16);
*laddr++ = readw(dma) | (readw(dma) << 16);
*laddr++ = readw(dma) | (readw(dma) << 16);
*laddr++ = readw(dma) | (readw(dma) << 16);
*laddr++ = readw(dma) | (readw(dma) << 16);
len -= 32;
if(len == 0)
break;
}
addr = (unsigned char *)laddr;
writeb(0x10, priv(host)->base + CTRL);
while(len > 0)
{
unsigned int status;
status = readb(priv(host)->base + STAT);
if(status & 0x80)
goto end;
if(status & 0x40)
{
*addr++ = readb(dma);
if(--len == 0)
break;
}
status = readb(priv(host)->base + STAT);
if(status & 0x80)
goto end;
if(status & 0x40)
{
*addr++ = readb(dma);
if(--len == 0)
break;
}
}
end:
writeb(priv(host)->ctrl | 0x40, priv(host)->base + CTRL);
return len;
}
void apple_bc_enable(struct usb_hcd *hcd, bool enable, int mode, int *pBackup)
{
if(hcd->bc_base == 0)
{
printk("This IC do not support USB BC funciton (%s)\n", __func__);
return;
}
if (enable) {
if (hcd->bc_apple_enable_flag == false) {
printk("Apple BC enable \n");
//disable init.
if (hcd->ehc_base)
{
*pBackup = readb((void *)(hcd->ehc_base+(0x18*2)));
writeb(readb((void *)(hcd->ehc_base+(0x18*2))) & (~0x3F) , (void *)(hcd->ehc_base+(0x18*2)));
}
else if (hcd->xhci_base)
{
writeb(readb((void *)(hcd->xhci_base+0x2020)) & (~0x2) , (void *)(hcd->xhci_base+0x2020));
}
writeb(readb((void *)(hcd->utmi_base)) | 0x2, (void *)(hcd->utmi_base)); // [1]re_term_override
#if defined(USB_BATTERY_CHARGE_SETTING_1)
writew(readw((void *)(hcd->bc_base+(0x2*2))) | 0x5080, (void *)(hcd->bc_base+(0x2*2))); //[14] reg_host_bc_en=1, [12]reg_bc_debug_mask=1
if (mode == REG_BC_MODE_IPAD)
writeb(readb((void *)(hcd->bc_base+(0x8*2))) | 0x2, (void *)(hcd->bc_base+(0x8*2)));
if (mode == REG_BC_MODE_IPHONE)
writeb(readb((void *)(hcd->bc_base+(0x8*2))) | 0x1, (void *)(hcd->bc_base+(0x8*2)));
#else
writeb(readb((void *)(hcd->bc_base+(0x3*2-1))) | 0x50, (void *)(hcd->bc_base+(0x3*2-1))); //[14] reg_host_bc_en=1, [12]reg_bc_debug_mask=1
#endif
writeb(readb((void *)(hcd->bc_base+(0xc*2))) | 0x40, (void *)(hcd->bc_base+(0xc*2))); // [6]= reg_into_host_bc_sw_tri
writew(0x00FF, (void *)(hcd->bc_base)); // [15:0] = bc_ctl_ov_en
writeb(readb((void *)(hcd->bc_base+(0xe*2))) | (mode|0x1), (void *)(hcd->bc_base+(0xe*2))); //[0]reg_apple_bc_en=1, [1:2]=2b'10,ipad mode, [1:2]=2b'01,iphone mode
hcd->bc_apple_enable_flag = true;
}
}
else {
if (hcd->bc_apple_enable_flag == true) {
printk("Apple BC disable \n");
writeb(readb((void *)(hcd->utmi_base)) & (~0x2), (void *)(hcd->utmi_base)); // [1]re_term_override
writew(0x0000, (void *)(hcd->bc_base)); // [15:0] = bc_ctl_ov_en
writeb(readb((void *)(hcd->bc_base+(0xc*2))) & (~0x40), (void *)(hcd->bc_base+(0xc*2))); // [6]= reg_into_host_bc_sw_tri
#if defined(USB_BATTERY_CHARGE_SETTING_1)
writew(readw((void *)(hcd->bc_base+(0x2*2))) & (~0x5080), (void *)(hcd->bc_base+(0x2*2))); //[14] reg_host_bc_en=1, [12]reg_bc_debug_mask=1
if (mode == REG_BC_MODE_IPAD)
writeb(readb((void *)(hcd->bc_base+(0x8*2))) & (~0x2), (void *)(hcd->bc_base+(0x8*2)));
if (mode == REG_BC_MODE_IPHONE)
writeb(readb((void *)(hcd->bc_base+(0x8*2))) & (~0x1), (void *)(hcd->bc_base+(0x8*2)));
#else
writeb(readb((void *)(hcd->bc_base+(0x3*2-1))) & (~0x50), (void *)(hcd->bc_base+(0x3*2-1))); // [6]= reg_host_bc_en
#endif
writeb(readb((void *)(hcd->bc_base+(0xe*2))) & (~0x1), (void *)(hcd->bc_base+(0xe*2))); //[0]reg_apple_bc_en=1
/// hcd->bc_apple_enable_flag = false; //disable it later.
//enable init.
if (hcd->ehc_base)
{
writeb(readb((void *)(hcd->ehc_base+(0x18*2))) | (*pBackup) , (void *)(hcd->ehc_base+(0x18*2)));
}
else if (hcd->xhci_base)
{
writeb(readb((void *)(hcd->xhci_base+0x2020)) | 0x2 , (void *)(hcd->xhci_base+0x2020));
}
hcd->bc_apple_enable_flag = false;
}
}
}
static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
{
return readw(c->onenand.base + reg);
}
/*!
* zasevb_modinit() - linux module initialization
*
* This needs to initialize the hcd, pcd and tcd drivers. This includes tcd and possibly hcd
* for some architectures.
*
*/
static int zasevb_modinit (void)
{
struct otg_instance *otg = NULL;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15)
struct clk *clk = clk_get(NULL, "usb_clk");
clk_enable(clk);
clk_put(clk);
#endif
THROW_UNLESS((otg = otg_create()), error);
mxc_pcd_ops_init();
#if !defined(OTG_C99)
pcd_global_init();
fs_ocd_global_init();
zasevb_tcd_global_init();
fs_pcd_global_init();
#endif /* !defined(OTG_C99) */
ZAS = otg_trace_obtain_tag(otg, "zas");
mxc_procfs_init();
TRACE_MSG0(ZAS, "1. ZAS");
#if 0
/* ZAS EVB Platform setup
*/
TRACE_MSG4(ZAS, "BCTRL Version: %04x Status: %04x 1: %04x 2: %04x",
readw(PBC_BASE_ADDRESS ),
readw(PBC_BASE_ADDRESS + PBC_BSTAT),
readw(PBC_BASE_ADDRESS + PBC_BCTRL1_SET),
readw(PBC_BASE_ADDRESS + PBC_BCTRL2_SET));
#endif
/* ZAS EVB Clock setup
*/
#if defined(CONFIG_ARCH_ARGONPLUS) || defined(CONFIG_ARCH_ARGONLV)
#define ZASEVB_MULTIPLIER 12
#define ZASEVB_DIVISOR 775 // ~10.
#else
#define ZASEVB_MULTIPLIER 12
#define ZASEVB_DIVISOR 155
#endif
TRACE_MSG0(ZAS, "2. Setup GPT");
THROW_UNLESS(ocd_instance = otg_set_ocd_ops(otg, &ocd_ops), error);
REMOVE_OCD = ocd_instance->TAG;
// XXX THROW_IF((ocd_ops.mod_init ? ocd_ops.mod_init() : 0), error);
#if defined(CONFIG_OTG_GPTR)
mxc_gptcr_mod_init(ZASEVB_DIVISOR, ZASEVB_MULTIPLIER);
#endif /* defined(CONFIG_OTG_GPTR) */
#if defined(CONFIG_OTG_HRT)
mxc_hrt_mod_init(otg, ZASEVB_DIVISOR, ZASEVB_MULTIPLIER);
#endif /* defined(CONFIG_OTG_GPTR) */
#if !defined(CONFIG_USB_HOST)
TRACE_MSG0(ZAS, "3. PCD");
THROW_UNLESS(REMOVE_pcd_instance = otg_set_pcd_ops(otg, &pcd_ops), error);
REMOVE_PCD = REMOVE_pcd_instance->TAG;
// XXX THROW_IF((pcd_ops.mod_init ? pcd_ops.mod_init() : 0), error);
#else /* !defined(CONFIG_USB_HOST) */
printk(KERN_INFO"%s: PCD DRIVER N/A\n", __FUNCTION__);
#endif /* !defined(CONFIG_USB_HOST) */
TRACE_MSG0(ZAS, "4. TCD");
THROW_UNLESS(REMOVE_tcd_instance = otg_set_tcd_ops(otg, &tcd_ops), error);
REMOVE_TCD = REMOVE_tcd_instance->TAG;
// XXX THROW_IF((tcd_ops.mod_init ? tcd_ops.mod_init() : 0), error);
#ifdef OTG_USE_I2C
TRACE_MSG0(ZAS, "0. I2C");
i2c_mod_init(otg);
#endif
#if defined(CONFIG_OTG_USB_HOST) || defined(CONFIG_OTG_USB_PERIPHERAL_OR_HOST)|| defined(CONFIG_OTG_DEVICE)
TRACE_MSG0(ZAS, "5. Host");
THROW_UNLESS(hcd_instance = otg_set_hcd_ops(otg, &hcd_ops), error);
HCD = hcd_instance->TAG;
// XXX THROW_IF((hcd_ops.mod_init) ? hcd_ops.mod_init() : 0, error);
#else /* defined(CONFIG_OTG_USB_HOST) || defined(CONFIG_OTG_USB_PERIPHERAL_OR_HOST)|| defined(CONFIG_OTG_DEVICE) */
printk(KERN_INFO"%s: HCD DRIVER N/A\n", __FUNCTION__);
#endif /* defined(CONFIG_OTG_USB_HOST) || defined(CONFIG_OTG_USB_PERIPHERAL_OR_HOST)|| defined(CONFIG_OTG_DEVICE) */
TRACE_MSG0(ZAS, "6. Init & check");
THROW_IF((ocd_ops.mod_init ? ocd_ops.mod_init(otg) : 0), error);
#if !defined(CONFIG_USB_HOST)
THROW_IF((pcd_ops.mod_init ? pcd_ops.mod_init(otg) : 0), error);
#endif /* !defined(CONFIG_USB_HOST) */
THROW_IF((tcd_ops.mod_init ? tcd_ops.mod_init(otg) : 0), error);
#if defined(CONFIG_OTG_USB_HOST) || defined(CONFIG_OTG_USB_PERIPHERAL_OR_HOST)|| defined(CONFIG_OTG_DEVICE)
THROW_IF((hcd_ops.mod_init) ? hcd_ops.mod_init(otg) : 0, error);
#endif /* defined(CONFIG_OTG_USB_HOST) || defined(CONFIG_OTG_USB_PERIPHERAL_OR_HOST)|| defined(CONFIG_OTG_DEVICE) */
THROW_UNLESS(ocd_instance && (otg = ocd_instance->otg), error);
TRACE_MSG0(ZAS, "7. otg_init");
if (MODPARM(serial_number_str) && strlen(MODPARM(serial_number_str))) {
TRACE_MSG1(ZAS, "serial_number_str: %s", MODPARM(serial_number_str));
otg_serial_number (otg, MODPARM(serial_number_str));
}
otg_init(otg);
return 0;
CATCH(error) {
//zasevb_modexit();
return -EINVAL;
}
return 0;
}
static inline u16 shpc_readw(struct controller *ctrl, int reg)
{
return readw(ctrl->creg + reg);
}
void RIOFixPhbs(struct rio_info *p, struct Host *HostP, unsigned int unit)
{
unsigned short link, port;
struct Port *PortP;
unsigned long flags;
int PortN = HostP->Mapping[unit].SysPort;
rio_dprintk(RIO_DEBUG_ROUTE, "RIOFixPhbs unit %d sysport %d\n", unit, PortN);
if (PortN != -1) {
unsigned short dest_unit = HostP->Mapping[unit].ID2;
/*
** Get the link number used for the 1st 8 phbs on this unit.
*/
PortP = p->RIOPortp[HostP->Mapping[dest_unit - 1].SysPort];
link = readw(&PortP->PhbP->link);
for (port = 0; port < PORTS_PER_RTA; port++, PortN++) {
unsigned short dest_port = port + 8;
u16 __iomem *TxPktP;
struct PKT __iomem *Pkt;
PortP = p->RIOPortp[PortN];
rio_spin_lock_irqsave(&PortP->portSem, flags);
/*
** If RTA is not powered on, the tx packets will be
** unset, so go no further.
*/
if (!PortP->TxStart) {
rio_dprintk(RIO_DEBUG_ROUTE, "Tx pkts not set up yet\n");
rio_spin_unlock_irqrestore(&PortP->portSem, flags);
break;
}
/*
** For the second slot of a 16 port RTA, the driver needs to
** sort out the phb to port mappings. The dest_unit for this
** group of 8 phbs is set to the dest_unit of the accompanying
** 8 port block. The dest_port of the second unit is set to
** be in the range 8-15 (i.e. 8 is added). Thus, for a 16 port
** RTA with IDs 5 and 6, traffic bound for port 6 of unit 6
** (being the second map ID) will be sent to dest_unit 5, port
** 14. When this RTA is deleted, dest_unit for ID 6 will be
** restored, and the dest_port will be reduced by 8.
** Transmit packets also have a destination field which needs
** adjusting in the same manner.
** Note that the unit/port bytes in 'dest' are swapped.
** We also need to adjust the phb and rup link numbers for the
** second block of 8 ttys.
*/
for (TxPktP = PortP->TxStart; TxPktP <= PortP->TxEnd; TxPktP++) {
/*
** *TxPktP is the pointer to the transmit packet on the host
** card. This needs to be translated into a 32 bit pointer
** so it can be accessed from the driver.
*/
Pkt = (struct PKT __iomem *) RIO_PTR(HostP->Caddr, readw(TxPktP));
/*
** If the packet is used, reset it.
*/
Pkt = (struct PKT __iomem *) ((unsigned long) Pkt & ~PKT_IN_USE);
writeb(dest_unit, &Pkt->dest_unit);
writeb(dest_port, &Pkt->dest_port);
}
rio_dprintk(RIO_DEBUG_ROUTE, "phb dest: Old %x:%x New %x:%x\n", readw(&PortP->PhbP->destination) & 0xff, (readw(&PortP->PhbP->destination) >> 8) & 0xff, dest_unit, dest_port);
writew(dest_unit + (dest_port << 8), &PortP->PhbP->destination);
writew(link, &PortP->PhbP->link);
rio_spin_unlock_irqrestore(&PortP->portSem, flags);
}
/*
** Now make sure the range of ports to be serviced includes
** the 2nd 8 on this 16 port RTA.
*/
if (link > 3)
return;
if (((unit * 8) + 7) > readw(&HostP->LinkStrP[link].last_port)) {
rio_dprintk(RIO_DEBUG_ROUTE, "last port on host link %d: %d\n", link, (unit * 8) + 7);
writew((unit * 8) + 7, &HostP->LinkStrP[link].last_port);
}
}
static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
int last)
{
struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
u16 val, tcr_val;
int ret;
unsigned long wait_result;
int xfer_len = 0;
if (!(pmsg->flags & I2C_M_NOSTART)) {
ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
if (ret < 0)
return ret;
}
if (pmsg->len == 0) {
/*
* We still need to run through the while (..) once, so
* start at -1 and break out early from the loop
*/
xfer_len = -1;
writew(0, i2c_dev->base + REG_CDR);
} else {
writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
}
if (!(pmsg->flags & I2C_M_NOSTART)) {
val = readw(i2c_dev->base + REG_CR);
val &= ~CR_TX_END;
writew(val, i2c_dev->base + REG_CR);
val = readw(i2c_dev->base + REG_CR);
val |= CR_CPU_RDY;
writew(val, i2c_dev->base + REG_CR);
}
reinit_completion(&i2c_dev->complete);
if (i2c_dev->mode == I2C_MODE_STANDARD)
tcr_val = TCR_STANDARD_MODE;
else
tcr_val = TCR_FAST_MODE;
tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
writew(tcr_val, i2c_dev->base + REG_TCR);
if (pmsg->flags & I2C_M_NOSTART) {
val = readw(i2c_dev->base + REG_CR);
val |= CR_CPU_RDY;
writew(val, i2c_dev->base + REG_CR);
}
while (xfer_len < pmsg->len) {
wait_result = wait_for_completion_timeout(&i2c_dev->complete,
msecs_to_jiffies(500));
if (wait_result == 0)
return -ETIMEDOUT;
ret = wmt_check_status(i2c_dev);
if (ret)
return ret;
xfer_len++;
val = readw(i2c_dev->base + REG_CSR);
if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
return -EIO;
}
if (pmsg->len == 0) {
val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
writew(val, i2c_dev->base + REG_CR);
break;
}
if (xfer_len == pmsg->len) {
if (last != 1)
writew(CR_ENABLE, i2c_dev->base + REG_CR);
} else {
writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
REG_CDR);
writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
}
}
return 0;
}
static inline u16 sossi_read_reg16(int reg)
{
return readw(sossi.base + reg);
}
static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
{
offset <<= up->port.regshift;
return readw(up->port.membase + offset);
}
static __u16 armflash_read16(struct map_info *map, unsigned long ofs)
{
return readw(ofs + map->map_priv_2);
}
static int snd_msnd_init_sma(struct snd_msnd *chip)
{
static int initted;
u16 mastVolLeft, mastVolRight;
unsigned long flags;
#ifdef MSND_CLASSIC
outb(chip->memid, chip->io + HP_MEMM);
#endif
outb(HPBLKSEL_0, chip->io + HP_BLKS);
/* Motorola 56k shared memory base */
chip->SMA = chip->mappedbase + SMA_STRUCT_START;
if (initted) {
mastVolLeft = readw(chip->SMA + SMA_wCurrMastVolLeft);
mastVolRight = readw(chip->SMA + SMA_wCurrMastVolRight);
} else
mastVolLeft = mastVolRight = 0;
memset_io(chip->mappedbase, 0, 0x8000);
/* Critical section: bank 1 access */
spin_lock_irqsave(&chip->lock, flags);
outb(HPBLKSEL_1, chip->io + HP_BLKS);
memset_io(chip->mappedbase, 0, 0x8000);
outb(HPBLKSEL_0, chip->io + HP_BLKS);
spin_unlock_irqrestore(&chip->lock, flags);
/* Digital audio play queue */
chip->DAPQ = chip->mappedbase + DAPQ_OFFSET;
snd_msnd_init_queue(chip->DAPQ, DAPQ_DATA_BUFF, DAPQ_BUFF_SIZE);
/* Digital audio record queue */
chip->DARQ = chip->mappedbase + DARQ_OFFSET;
snd_msnd_init_queue(chip->DARQ, DARQ_DATA_BUFF, DARQ_BUFF_SIZE);
/* MIDI out queue */
chip->MODQ = chip->mappedbase + MODQ_OFFSET;
snd_msnd_init_queue(chip->MODQ, MODQ_DATA_BUFF, MODQ_BUFF_SIZE);
/* MIDI in queue */
chip->MIDQ = chip->mappedbase + MIDQ_OFFSET;
snd_msnd_init_queue(chip->MIDQ, MIDQ_DATA_BUFF, MIDQ_BUFF_SIZE);
/* DSP -> host message queue */
chip->DSPQ = chip->mappedbase + DSPQ_OFFSET;
snd_msnd_init_queue(chip->DSPQ, DSPQ_DATA_BUFF, DSPQ_BUFF_SIZE);
/* Setup some DSP values */
#ifndef MSND_CLASSIC
writew(1, chip->SMA + SMA_wCurrPlayFormat);
writew(chip->play_sample_size, chip->SMA + SMA_wCurrPlaySampleSize);
writew(chip->play_channels, chip->SMA + SMA_wCurrPlayChannels);
writew(chip->play_sample_rate, chip->SMA + SMA_wCurrPlaySampleRate);
#endif
writew(chip->play_sample_rate, chip->SMA + SMA_wCalFreqAtoD);
writew(mastVolLeft, chip->SMA + SMA_wCurrMastVolLeft);
writew(mastVolRight, chip->SMA + SMA_wCurrMastVolRight);
#ifndef MSND_CLASSIC
writel(0x00010000, chip->SMA + SMA_dwCurrPlayPitch);
writel(0x00000001, chip->SMA + SMA_dwCurrPlayRate);
#endif
writew(0x303, chip->SMA + SMA_wCurrInputTagBits);
initted = 1;
return 0;
}
/**
* Start the FEC engine
* @param[in] dev Our device to handle
*/
static int fec_open(struct eth_device *edev)
{
struct fec_priv *fec = (struct fec_priv *)edev->priv;
int speed;
uint32_t addr, size;
int i;
debug("fec_open: fec_open(dev)\n");
/* full-duplex, heartbeat disabled */
writel(1 << 2, &fec->eth->x_cntrl);
fec->rbd_index = 0;
/* Invalidate all descriptors */
for (i = 0; i < FEC_RBD_NUM - 1; i++)
fec_rbd_clean(0, &fec->rbd_base[i]);
fec_rbd_clean(1, &fec->rbd_base[i]);
/* Flush the descriptors into RAM */
size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
ARCH_DMA_MINALIGN);
addr = (uint32_t)fec->rbd_base;
flush_dcache_range(addr, addr + size);
#ifdef FEC_QUIRK_ENET_MAC
/* Enable ENET HW endian SWAP */
writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
&fec->eth->ecntrl);
/* Enable ENET store and forward mode */
writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
&fec->eth->x_wmrk);
#endif
/*
* Enable FEC-Lite controller
*/
writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
&fec->eth->ecntrl);
#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
udelay(100);
/*
* setup the MII gasket for RMII mode
*/
/* disable the gasket */
writew(0, &fec->eth->miigsk_enr);
/* wait for the gasket to be disabled */
while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
udelay(2);
/* configure gasket for RMII, 50 MHz, no loopback, and no echo */
writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
/* re-enable the gasket */
writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
/* wait until MII gasket is ready */
int max_loops = 10;
while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
if (--max_loops <= 0) {
printf("WAIT for MII Gasket ready timed out\n");
break;
}
}
#endif
#ifdef CONFIG_PHYLIB
{
/* Start up the PHY */
int ret = phy_startup(fec->phydev);
if (ret) {
printf("Could not initialize PHY %s\n",
fec->phydev->dev->name);
return ret;
}
speed = fec->phydev->speed;
}
#else
miiphy_wait_aneg(edev);
speed = miiphy_speed(edev->name, fec->phy_id);
miiphy_duplex(edev->name, fec->phy_id);
#endif
#ifdef FEC_QUIRK_ENET_MAC
{
u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
if (speed == _1000BASET)
ecr |= FEC_ECNTRL_SPEED;
else if (speed != _100BASET)
rcr |= FEC_RCNTRL_RMII_10T;
writel(ecr, &fec->eth->ecntrl);
writel(rcr, &fec->eth->r_cntrl);
}
#endif
debug("%s:Speed=%i\n", __func__, speed);
/*
* Enable SmartDMA receive task
*/
fec_rx_task_enable(fec);
udelay(100000);
return 0;
}
static int __init coh901327_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int ret;
u16 val;
struct resource *res;
parent = dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
virtbase = devm_ioremap_resource(dev, res);
if (IS_ERR(virtbase))
return PTR_ERR(virtbase);
clk = clk_get(dev, NULL);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
dev_err(dev, "could not get clock\n");
return ret;
}
ret = clk_prepare_enable(clk);
if (ret) {
dev_err(dev, "could not prepare and enable clock\n");
goto out_no_clk_enable;
}
val = readw(virtbase + U300_WDOG_SR);
switch (val) {
case U300_WDOG_SR_STATUS_TIMED_OUT:
dev_info(dev, "watchdog timed out since last chip reset!\n");
coh901327_wdt.bootstatus |= WDIOF_CARDRESET;
/* Status will be cleared below */
break;
case U300_WDOG_SR_STATUS_NORMAL:
dev_info(dev, "in normal status, no timeouts have occurred.\n");
break;
default:
dev_info(dev, "contains an illegal status code (%08x)\n", val);
break;
}
val = readw(virtbase + U300_WDOG_D2R);
switch (val) {
case U300_WDOG_D2R_DISABLE_STATUS_DISABLED:
dev_info(dev, "currently disabled.\n");
break;
case U300_WDOG_D2R_DISABLE_STATUS_ENABLED:
dev_info(dev, "currently enabled! (disabling it now)\n");
coh901327_disable();
break;
default:
dev_err(dev, "contains an illegal enable/disable code (%08x)\n",
val);
break;
}
/* Reset the watchdog */
writew(U300_WDOG_SR_RESET_STATUS_RESET, virtbase + U300_WDOG_SR);
irq = platform_get_irq(pdev, 0);
if (request_irq(irq, coh901327_interrupt, 0,
DRV_NAME " Bark", pdev)) {
ret = -EIO;
goto out_no_irq;
}
watchdog_init_timeout(&coh901327_wdt, margin, dev);
coh901327_wdt.parent = dev;
ret = watchdog_register_device(&coh901327_wdt);
if (ret)
goto out_no_wdog;
dev_info(dev, "initialized. (timeout=%d sec)\n",
coh901327_wdt.timeout);
return 0;
out_no_wdog:
free_irq(irq, pdev);
out_no_irq:
clk_disable_unprepare(clk);
out_no_clk_enable:
clk_put(clk);
return ret;
}
/**
* Transmit one frame
* @param[in] dev Our ethernet device to handle
* @param[in] packet Pointer to the data to be transmitted
* @param[in] length Data count in bytes
* @return 0 on success
*/
static int fec_send(struct eth_device *dev, void *packet, int length)
{
unsigned int status;
uint32_t size, end;
uint32_t addr;
int timeout = FEC_XFER_TIMEOUT;
int ret = 0;
/*
* This routine transmits one frame. This routine only accepts
* 6-byte Ethernet addresses.
*/
struct fec_priv *fec = (struct fec_priv *)dev->priv;
/*
* Check for valid length of data.
*/
if ((length > 1500) || (length <= 0)) {
printf("Payload (%d) too large\n", length);
return -1;
}
/*
* Setup the transmit buffer. We are always using the first buffer for
* transmission, the second will be empty and only used to stop the DMA
* engine. We also flush the packet to RAM here to avoid cache trouble.
*/
#ifdef CONFIG_FEC_MXC_SWAP_PACKET
swap_packet((uint32_t *)packet, length);
#endif
addr = (uint32_t)packet;
end = roundup(addr + length, ARCH_DMA_MINALIGN);
addr &= ~(ARCH_DMA_MINALIGN - 1);
flush_dcache_range(addr, end);
writew(length, &fec->tbd_base[fec->tbd_index].data_length);
writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
/*
* update BD's status now
* This block:
* - is always the last in a chain (means no chain)
* - should transmitt the CRC
* - might be the last BD in the list, so the address counter should
* wrap (-> keep the WRAP flag)
*/
status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
writew(status, &fec->tbd_base[fec->tbd_index].status);
/*
* Flush data cache. This code flushes both TX descriptors to RAM.
* After this code, the descriptors will be safely in RAM and we
* can start DMA.
*/
size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
addr = (uint32_t)fec->tbd_base;
flush_dcache_range(addr, addr + size);
/*
* Below we read the DMA descriptor's last four bytes back from the
* DRAM. This is important in order to make sure that all WRITE
* operations on the bus that were triggered by previous cache FLUSH
* have completed.
*
* Otherwise, on MX28, it is possible to observe a corruption of the
* DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
* for the bus structure of MX28. The scenario is as follows:
*
* 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
* to DRAM due to flush_dcache_range()
* 2) ARM core writes the FEC registers via AHB_ARB2
* 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
*
* Note that 2) does sometimes finish before 1) due to reordering of
* WRITE accesses on the AHB bus, therefore triggering 3) before the
* DMA descriptor is fully written into DRAM. This results in occasional
* corruption of the DMA descriptor.
*/
readl(addr + size - 4);
/*
* Enable SmartDMA transmit task
*/
fec_tx_task_enable(fec);
/*
* Wait until frame is sent. On each turn of the wait cycle, we must
* invalidate data cache to see what's really in RAM. Also, we need
* barrier here.
*/
while (--timeout) {
if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
break;
}
if (!timeout)
ret = -EINVAL;
invalidate_dcache_range(addr, addr + size);
if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
ret = -EINVAL;
debug("fec_send: status 0x%x index %d ret %i\n",
readw(&fec->tbd_base[fec->tbd_index].status),
fec->tbd_index, ret);
/* for next transmission use the other buffer */
if (fec->tbd_index)
fec->tbd_index = 0;
else
fec->tbd_index = 1;
return ret;
}
/* IRQ-Handler for simcard interface */
void sim_irq_handler(enum irq_nr irq)
{
int regVal = readw(REG_SIM_IT);
/* Display interrupt information */
printd("SIM-ISR: ");
if(regVal & REG_SIM_IT_SIM_NATR) {
printd(" No answer to reset!\n");
}
/* Used by: calypso_sim_receive() to determine when the transmission
* is over
*/
if(regVal & REG_SIM_IT_SIM_WT) {
printd(" Character underflow!\n");
rxDoneFlag = 1;
}
if(regVal & REG_SIM_IT_SIM_OV) {
printd(" Receive overflow!\n");
}
/* Used by: calypso_sim_transmit() to transmit the data */
if(regVal & REG_SIM_IT_SIM_TX) {
printd(" Waiting for transmit...\n");
if(sim_tx_character_count >= sim_tx_character_length) {
txDoneFlag = 1;
} else {
writew(*tx_buffer,REG_SIM_DTX);
tx_buffer++;
sim_tx_character_count++;
/* its essential to immediately switch to RX after TX
* is done
*/
if(sim_tx_character_count >= sim_tx_character_length) {
/* TODO: set a proper delay here, 4 is to
long if not debugging and no delay is too
short */
// delay_ms(1);
/* Switch I/O direction to input */
writew(readw(REG_SIM_CONF1) &
~REG_SIM_CONF1_CONFTXRX, REG_SIM_CONF1);
}
}
}
/* Used by: calypso_sim_receive() to receive the incoming data */
if(regVal & REG_SIM_IT_SIM_RX) {
uint8_t ch = (uint8_t) (readw(REG_SIM_DRX) & 0xFF);
/* ignore NULL procedure byte */
if(ch == 0x60 && sim_ignore_waiting_char) {
printd(" 0x60 received...\n");
return;
}
printd(" Waiting for read (%02X)...\n", ch);
/* Increment character count - this is what
* calypso_sim_receive() hands back
*/
sim_rx_character_count++;
/* Read byte from rx-fifo and write it to the issued buffer */
*rx_buffer = ch;
rx_buffer++;
/* to maximise SIM access speed, stop waiting after
all the expected characters have been received. */
if (sim_rx_max_character_count
&& sim_rx_character_count >= sim_rx_max_character_count) {
printd(" Max characters received!\n");
rxDoneFlag = 1;
}
}
}
/**
* Pull one frame from the card
* @param[in] dev Our ethernet device to handle
* @return Length of packet read
*/
static int fec_recv(struct eth_device *dev)
{
struct fec_priv *fec = (struct fec_priv *)dev->priv;
struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
unsigned long ievent;
int frame_length, len = 0;
struct nbuf *frame;
uint16_t bd_status;
uint32_t addr, size, end;
int i;
ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
/*
* Check if any critical events have happened
*/
ievent = readl(&fec->eth->ievent);
writel(ievent, &fec->eth->ievent);
debug("fec_recv: ievent 0x%lx\n", ievent);
if (ievent & FEC_IEVENT_BABR) {
fec_halt(dev);
fec_init(dev, fec->bd);
printf("some error: 0x%08lx\n", ievent);
return 0;
}
if (ievent & FEC_IEVENT_HBERR) {
/* Heartbeat error */
writel(0x00000001 | readl(&fec->eth->x_cntrl),
&fec->eth->x_cntrl);
}
if (ievent & FEC_IEVENT_GRA) {
/* Graceful stop complete */
if (readl(&fec->eth->x_cntrl) & 0x00000001) {
fec_halt(dev);
writel(~0x00000001 & readl(&fec->eth->x_cntrl),
&fec->eth->x_cntrl);
fec_init(dev, fec->bd);
}
}
/*
* Read the buffer status. Before the status can be read, the data cache
* must be invalidated, because the data in RAM might have been changed
* by DMA. The descriptors are properly aligned to cachelines so there's
* no need to worry they'd overlap.
*
* WARNING: By invalidating the descriptor here, we also invalidate
* the descriptors surrounding this one. Therefore we can NOT change the
* contents of this descriptor nor the surrounding ones. The problem is
* that in order to mark the descriptor as processed, we need to change
* the descriptor. The solution is to mark the whole cache line when all
* descriptors in the cache line are processed.
*/
addr = (uint32_t)rbd;
addr &= ~(ARCH_DMA_MINALIGN - 1);
size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
invalidate_dcache_range(addr, addr + size);
bd_status = readw(&rbd->status);
debug("fec_recv: status 0x%x\n", bd_status);
if (!(bd_status & FEC_RBD_EMPTY)) {
if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
((readw(&rbd->data_length) - 4) > 14)) {
/*
* Get buffer address and size
*/
frame = (struct nbuf *)readl(&rbd->data_pointer);
frame_length = readw(&rbd->data_length) - 4;
/*
* Invalidate data cache over the buffer
*/
addr = (uint32_t)frame;
end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
addr &= ~(ARCH_DMA_MINALIGN - 1);
invalidate_dcache_range(addr, end);
/*
* Fill the buffer and pass it to upper layers
*/
#ifdef CONFIG_FEC_MXC_SWAP_PACKET
swap_packet((uint32_t *)frame->data, frame_length);
#endif
memcpy(buff, frame->data, frame_length);
NetReceive(buff, frame_length);
len = frame_length;
} else {
if (bd_status & FEC_RBD_ERR)
printf("error frame: 0x%08lx 0x%08x\n",
(ulong)rbd->data_pointer,
bd_status);
}
/*
* Free the current buffer, restart the engine and move forward
* to the next buffer. Here we check if the whole cacheline of
* descriptors was already processed and if so, we mark it free
* as whole.
*/
size = RXDESC_PER_CACHELINE - 1;
if ((fec->rbd_index & size) == size) {
i = fec->rbd_index - size;
addr = (uint32_t)&fec->rbd_base[i];
for (; i <= fec->rbd_index ; i++) {
fec_rbd_clean(i == (FEC_RBD_NUM - 1),
&fec->rbd_base[i]);
}
flush_dcache_range(addr,
addr + ARCH_DMA_MINALIGN);
}
fec_rx_task_enable(fec);
fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
}
debug("fec_recv: stop\n");
return len;
}
static inline u16
snd_nm256_readw(struct nm256 *chip, int offset)
{
return readw(chip->cport + offset);
}
static void readwriter(struct pl022 *pl022)
{
dev_dbg(&pl022->adev->dev,
"%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
__func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
&& (pl022->rx < pl022->rx_end)) {
switch (pl022->read) {
case READING_NULL:
readw(SSP_DR(pl022->virtbase));
break;
case READING_U8:
*(u8 *) (pl022->rx) =
readw(SSP_DR(pl022->virtbase)) & 0xFFU;
break;
case READING_U16:
*(u16 *) (pl022->rx) =
(u16) readw(SSP_DR(pl022->virtbase));
break;
case READING_U32:
*(u32 *) (pl022->rx) =
readl(SSP_DR(pl022->virtbase));
break;
}
pl022->rx += (pl022->cur_chip->n_bytes);
}
while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
&& (pl022->tx < pl022->tx_end)) {
switch (pl022->write) {
case WRITING_NULL:
writew(0x0, SSP_DR(pl022->virtbase));
break;
case WRITING_U8:
writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
break;
case WRITING_U16:
writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
break;
case WRITING_U32:
writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
break;
}
pl022->tx += (pl022->cur_chip->n_bytes);
while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
&& (pl022->rx < pl022->rx_end)) {
switch (pl022->read) {
case READING_NULL:
readw(SSP_DR(pl022->virtbase));
break;
case READING_U8:
*(u8 *) (pl022->rx) =
readw(SSP_DR(pl022->virtbase)) & 0xFFU;
break;
case READING_U16:
*(u16 *) (pl022->rx) =
(u16) readw(SSP_DR(pl022->virtbase));
break;
case READING_U32:
*(u32 *) (pl022->rx) =
readl(SSP_DR(pl022->virtbase));
break;
}
pl022->rx += (pl022->cur_chip->n_bytes);
}
}
}
static int
clear_stats (struct net_device *dev)
{
long ioaddr = dev->base_addr;
#ifdef MEM_MAPPING
int i;
#endif
/* All statistics registers need to be acknowledged,
else statistic overflow could cause problems */
readl (ioaddr + FramesRcvOk);
readl (ioaddr + FramesXmtOk);
readl (ioaddr + OctetRcvOk);
readl (ioaddr + OctetXmtOk);
readl (ioaddr + McstFramesRcvdOk);
readl (ioaddr + SingleColFrames);
readl (ioaddr + MultiColFrames);
readl (ioaddr + LateCollisions);
/* detailed rx errors */
readw (ioaddr + FrameTooLongErrors);
readw (ioaddr + InRangeLengthErrors);
readw (ioaddr + FramesCheckSeqErrors);
readw (ioaddr + FramesLostRxErrors);
/* detailed tx errors */
readw (ioaddr + FramesAbortXSColls);
readw (ioaddr + CarrierSenseErrors);
/* Clear all other statistic register. */
readl (ioaddr + McstOctetXmtOk);
readw (ioaddr + BcstFramesXmtdOk);
readl (ioaddr + McstFramesXmtdOk);
readw (ioaddr + BcstFramesRcvdOk);
readw (ioaddr + MacControlFramesRcvd);
readl (ioaddr + McstOctetXmtOk);
readl (ioaddr + BcstOctetXmtOk);
readl (ioaddr + McstFramesXmtdOk);
readl (ioaddr + FramesWDeferredXmt);
readw (ioaddr + BcstFramesXmtdOk);
readw (ioaddr + MacControlFramesXmtd);
readw (ioaddr + FramesWEXDeferal);
#ifdef MEM_MAPPING
for (i = 0x100; i <= 0x150; i += 4)
readl (ioaddr + i);
#endif
readw (ioaddr + TxJumboFrames);
readw (ioaddr + RxJumboFrames);
readw (ioaddr + TCPCheckSumErrors);
readw (ioaddr + UDPCheckSumErrors);
readw (ioaddr + IPCheckSumErrors);
return 0;
}
static int docg4_load_block_reliable(uint32_t flash_offset, void *dest_addr)
{
void __iomem *docptr = (void *)CONFIG_SYS_NAND_BASE;
unsigned int g4_page = flash_offset >> 11; /* 2k page */
const unsigned int last_g4_page = g4_page + 0x80; /* last in block */
int g4_index = 0;
uint16_t flash_status;
uint16_t *buf;
uint16_t discard, magic_high, magic_low;
/* flash_offset must be aligned to the start of a block */
if (flash_offset & 0x3ffff)
return -1;
writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE);
writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND);
write_nop(docptr);
write_nop(docptr);
poll_status(docptr);
write_nop(docptr);
writew(0x45, docptr + DOC_FLASHSEQUENCE);
writew(0xa3, docptr + DOC_FLASHCOMMAND);
write_nop(docptr);
writew(0x22, docptr + DOC_FLASHCOMMAND);
write_nop(docptr);
/* read 1st 4 oob bytes of first subpage of block */
address_sequence(g4_page, 0x0100, docptr); /* index at oob */
write_nop(docptr);
flash_status = readw(docptr + DOC_FLASHCONTROL);
flash_status = readw(docptr + DOC_FLASHCONTROL);
if (flash_status & 0x06) /* sequence or protection errors */
return -1;
writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND);
write_nop(docptr);
write_nop(docptr);
poll_status(docptr);
writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
write_nop(docptr);
write_nop(docptr);
write_nop(docptr);
write_nop(docptr);
write_nop(docptr);
/*
* Here we read the first four oob bytes of the first page of the block.
* The IPL on the palmtreo680 requires that this contain a 32 bit magic
* number, or the load aborts. We'll ignore it.
*/
discard = readw(docptr + 0x103c); /* hw quirk; 1st read discarded */
magic_low = readw(docptr + 0x103c);
magic_high = readw(docptr + DOCG4_MYSTERY_REG);
writew(0, docptr + DOC_DATAEND);
write_nop(docptr);
write_nop(docptr);
/* load contents of block to memory */
buf = (uint16_t *)dest_addr;
do {
int i;
address_sequence(g4_page, g4_index, docptr);
writew(DOCG4_CMD_READ2,
docptr + DOC_FLASHCOMMAND);
write_nop(docptr);
write_nop(docptr);
poll_status(docptr);
writew(DOC_ECCCONF0_READ_MODE |
DOC_ECCCONF0_ECC_ENABLE |
DOCG4_BCH_SIZE,
docptr + DOC_ECCCONF0);
write_nop(docptr);
write_nop(docptr);
write_nop(docptr);
write_nop(docptr);
write_nop(docptr);
/* read the 512 bytes of page data, 2 bytes at a time */
discard = readw(docptr + 0x103c);
for (i = 0; i < 256; i++)
*buf++ = readw(docptr + 0x103c);
/* read oob, but discard it */
for (i = 0; i < 7; i++)
discard = readw(docptr + 0x103c);
discard = readw(docptr + DOCG4_OOB_6_7);
discard = readw(docptr + DOCG4_OOB_6_7);
writew(0, docptr + DOC_DATAEND);
write_nop(docptr);
write_nop(docptr);
if (!(g4_index & 0x100)) {
/* not redundant subpage read; check for ecc error */
write_nop(docptr);
flash_status = readw(docptr + DOC_ECCCONF1);
flash_status = readw(docptr + DOC_ECCCONF1);
if (flash_status & 0x80) { /* ecc error */
g4_index += 0x108; /* read redundant subpage */
buf -= 256; /* back up ram ptr */
continue;
} else /* no ecc error */
g4_index += 0x210; /* skip redundant subpage */
} else /* redundant page was just read; skip ecc error check */
g4_index += 0x108;
if (g4_index == 0x420) { /* finished with 2k page */
g4_index = 0;
g4_page += 2; /* odd-numbered 2k pages skipped */
}
} while (g4_page != last_g4_page); /* while still on same block */
return 0;
}
