NoximPacket NoximProcessingElement::trafficTranspose2()
{
NoximPacket p;
p.src_id = local_id;
NoximCoord src, dst;
// Transpose 2 destination distribution
src = id2Coord(p.src_id);
dst.x = src.y;
dst.y = src.x;
dst.z = src.z;
fixRanges(src, dst);
p.dst_id = coord2Id(dst);
p.timestamp = sc_time_stamp().to_double() / 1000;
p.size = p.flit_left = getRandomSize();
// if (p.src_id == p.dst_id)
// cout << "Traffic generator has generated a packet is sent from a node to itself !!! \n";
return p;
}
Packet ProcessingElement::trafficButterfly()
{
int nbits =
(int)
log2ceil((double)
(GlobalParams::mesh_dim_x *
GlobalParams::mesh_dim_y));
int dnode = 0;
for (int i = 1; i < nbits - 1; i++)
setBit(dnode, i, getBit(local_id, i));
setBit(dnode, 0, getBit(local_id, nbits - 1));
setBit(dnode, nbits - 1, getBit(local_id, 0));
Packet p;
p.src_id = local_id;
p.dst_id = dnode;
p.timestamp = sc_time_stamp().to_double() / GlobalParams::clock_period_ps;
p.size = p.flit_left = getRandomSize();
return p;
}
void simple_bus_master_direct::main_action()
{
int mydata[4];
while (true)
{
bus_port->direct_read(&mydata[0], m_address);
bus_port->direct_read(&mydata[1], m_address+4);
bus_port->direct_read(&mydata[2], m_address+8);
bus_port->direct_read(&mydata[3], m_address+12);
if (m_verbose)
sb_fprintf(stdout, "%g %s : mem[%x:%x] = (%x, %x, %x, %x)\n",
sc_time_stamp().to_double(), name(), m_address,
m_address+15,
mydata[0], mydata[1], mydata[2], mydata[3]);
wait(m_timeout, SC_NS);
}
}
NoximPacket NoximProcessingElement::trafficShuffle()
{
int nbits = (int)log2ceil(
(double)(NoximGlobalParams::mesh_dim_x *
NoximGlobalParams::mesh_dim_y *
NoximGlobalParams::mesh_dim_z ));
int dnode = 0;
for (int i = 0; i < nbits - 1; i++)
setBit(dnode, i + 1, getBit(local_id, i ));
setBit(dnode, 0 , getBit(local_id, nbits - 1));
NoximPacket p;
p.src_id = local_id;
p.dst_id = dnode ;
p.timestamp = sc_time_stamp().to_double() / 1000;
p.size = p.flit_left = getRandomSize();
// if (p.src_id == p.dst_id)
// cout << "Traffic generator has generated a packet is sent from a node to itself !!! \n";
return p;
}
void bios::entry()
{
unsigned address;
while (true) {
do { wait(); } while ( !(cs == true) );
address = addr.read();
if (address < BOOT_LENGTH) { // in BOOTING STAGE
if (we.read() == true) { // Write operation
wait(wait_cycles-1);
imemory[address] = datain.read();
}
else { // Read operation
if (wait_cycles > 2)
wait(wait_cycles-2); // Introduce delay needed
dataout.write(imemory[address]);
if (PRINT_BIOS) {
printf("------------------------\n");
printf("BIOS: fetching mem[%d]\n", address);
printf("BIOS: (%0x)", imemory[address]);
cout.setf(ios::dec,ios::basefield);
cout << " at CSIM " << sc_time_stamp() << endl;
printf("------------------------\n");
}
bios_valid.write(true);
wait();
bios_valid.write(false);
wait();
}
} else {
bios_valid.write(false);
wait();
}
}
} // end of entry function
void TProcessingElement::txProcess()
{
if(reset.read())
{
req_tx.write(0);
current_level_tx = 0;
transmittedAtPreviousCycle = false;
}
else
{
TPacket packet;
if (canShot(packet))
{
packet_queue.push(packet);
transmittedAtPreviousCycle = true;
}
else
transmittedAtPreviousCycle = false;
if(ack_tx.read() == current_level_tx)
{
if(!packet_queue.empty())
{
TFlit flit = nextFlit(); // Generate a new flit
if(TGlobalParams::verbose_mode > VERBOSE_OFF)
{
cout << sc_time_stamp().to_double()/1000 << ": ProcessingElement[" << local_id << "] \033[22;31mSENDING\033[22;30m " << flit << endl;
}
flit_tx->write(flit); // Send the generated flit
current_level_tx = 1-current_level_tx; // Negate the old value for Alternating Bit Protocol (ABP)
req_tx.write(current_level_tx);
}
}
}
}
void dynamic_method()
{
static int state = 0;
switch ( state )
{
case 0:
m_dynamic_method = sc_get_current_process_handle();
next_trigger( m_clk.posedge_event() );
cout << sc_time_stamp() << ": dynamic method (" << __LINE__
<< "," << state << ") initialization call " << endl;
break;
case 1:
next_trigger( m_clk.posedge_event() );
cout << sc_time_stamp() << ": dynamic method (" << __LINE__
<< "," << state << ") after wait on m_clk.posedge_event() "
<< endl;
break;
case 2:
next_trigger( m_clk.negedge_event() );
cout << sc_time_stamp() << ": dynamic method (" << __LINE__
<< "," << state << ") after wait on m_clk.posedge_event() "
<< endl;
break;
case 3:
next_trigger( m_event1 & m_event2 );
cout << sc_time_stamp() << ": dynamic method (" << __LINE__
<< "," << state << ") after wait on m_clk.negedge() " << endl;
break;
case 4:
next_trigger( m_clk.posedge_event() );
cout << sc_time_stamp() << ": dynamic method (" << __LINE__
<< "," << state << ") after wait on m_event1 & m_event2 "
<< endl;
break;
default:
next_trigger( m_clk.posedge_event() );
cout << sc_time_stamp() << ": dynamic method (" << __LINE__
<< "," << state << ") after wait on m_clk.posedge_event() "
<< endl;
break;
}
state = state + 1;
if ( state == 5 ) state = 1;
}
void t3_fun() {
char in_var;
fifo_buffer<char> *in1;
if(fifo_buffer_char.find("fifo2")==fifo_buffer_char.end()) {
cout << "T3: Error retrieving fifo2 reference" << endl;
exit(-1);
}
in1 = fifo_buffer_char["fifo2"];
while(true) {
in1->read(in_var);
cout << "T3: recv: " << in_var << " at time " << sc_time_stamp() << endl;
CONSUME_T;
yield();
}
}
simple_bus_request * simple_bus::get_next_request()
{
// the slave is done with its action, m_current_request is
// empty, so go over the bag of request-forms and compose
// a set of likely requests. Pass it to the arbiter for the
// final selection
simple_bus_request_vec Q;
for (int i = 0; i < m_requests.size(); ++i)
{
simple_bus_request *request = m_requests[i];
if ((request->status == SIMPLE_BUS_REQUEST) ||
(request->status == SIMPLE_BUS_WAIT))
{
if (m_verbose)
sb_fprintf(stdout, "%g %s : request (%d) [%s]\n",
sc_time_stamp().to_double(), name(),
request->priority, simple_bus_status_str[request->status]);
Q.push_back(request);
}
}
if (Q.size() > 0)
return arbiter_port->arbitrate(Q);
return (simple_bus_request *)0;
}
NoximPacket NoximProcessingElement::trafficOneDest()
{
NoximPacket p;
p.src_id = local_id;
// double rnd = rand() / (double) RAND_MAX;
// double range_start = 0.0;
// Destination Set to id=20
do {
p.dst_id = 20;
// check for hotspot destination
//////// commented the hotspot mehanism
/* for (uint i = 0; i < NoximGlobalParams::hotspots.size(); i++) {
//cout << sc_time_stamp().to_double()/1000 << " PE " << local_id << " Checking node " << NoximGlobalParams::hotspots[i].first << " with P = " << NoximGlobalParams::hotspots[i].second << endl;
if (rnd >= range_start
&& rnd <
range_start + NoximGlobalParams::hotspots[i].second) {
if (local_id != NoximGlobalParams::hotspots[i].first) {
//cout << sc_time_stamp().to_double()/1000 << " PE " << local_id <<" That is ! " << endl;
p.dst_id = NoximGlobalParams::hotspots[i].first;
}
break;
} else
range_start += NoximGlobalParams::hotspots[i].second; // try next
} */
} while (p.dst_id == p.src_id);
p.timestamp = sc_time_stamp().to_double() / 1000;
p.size = p.flit_left = getRandomSize();
return p;
}
void
CPersSch::PersSch()
{
//sch_thr_idx_t wcid = (sch_thr_idx_t)RecvMsg_schPush().m_connId;
// UDP must go through the same queue based on pConn index
uint16_t nxtCid = RecvMsg_schPush().m_connId;
sch_thr_idx_t wcid = cid2que(nxtCid);
sch_que_idx_t wadr = S_queWrIdx[wcid];
m_queDat.write_addr(wcid, wadr);
if (!RecvMsgBusy_schPush()) {
m_queDat.write_mem(RecvMsg_schPush());
S_queWrIdx[wcid] += 1;
}
//
// Stage 1
//
sch_que_idx_t radr = S_queRdIdx[PR1_htId];
m_queDat.read_addr(PR1_htId, radr);
T1_bEmpty = SR_queWrIdx[PR1_htId] == SR_queRdIdx[PR1_htId];
//
// Stage 2
//
if (PR2_htValid) {
switch (PR2_htInst) {
case SCH_SPIN: {
if (SendCallBusy_ProcessPkt()
|| SendMsgBusy_schPop()
|| TR2_bEmpty) {
HtRetry();
break;
}
uint16_t cid = S_queDat.read_mem().m_connId;
conn_addr_t cidAddr = cid2addr(cid);
#ifndef _HTV
extern FILE *tfp;
if (tfp)
fprintf(tfp, "SCH: Calling Pkt cid=0x%04x blkIdx=%d @ %lld\n",
(int)cid, (int)S_queDat.read_mem().m_info.m_blkIndex,
(long long)sc_time_stamp().value() / 10000);
#endif
SendCall_ProcessPkt(SCH_RETURN,
S_queDat.read_mem().m_info,
cid, cidAddr);
S_queRdIdx[PR2_htId] += 1;
SendMsg_schPop(PR2_htId);
}
break;
case SCH_RETURN: {
HtContinue(SCH_SPIN);
}
break;
default:
if (SendReturnBusy_sch()) {
HtRetry();
break;
}
SendReturn_sch();
assert(0);
}
}
if (GR_htReset) {
for (int i=0; i<16; i++) {
S_queWrIdx[i] = 0;
S_queRdIdx[i] = 0;
}
}
}
void uvm_ml_run_test(const std::vector<std::string>& tops, const char * test) {
uvm_ml_run_test(tops, test, sc_time(~sc_dt::UINT64_ZERO, false) - sc_time_stamp());
}
const sc_time&
sc_clock::time_stamp()
{
return sc_time_stamp();
}
int sc_main (int argc, char *argv[]) {
sc_signal<bool> clk, reset, clear;
wait();
wait (clk.posedge_event());
wait (reset.negedge_event());
// negedge_event() and posedge_event() methods can
// be applied to a signal or a port to identify the
// specific event.
wait (clk.posedge_event() | reset.negedge_event() | clear.value_changed_event());
// A value_changed_event() method is true when any
// value change occu
sc_signal<sc_uint<4> > ready;
sc_signal<bool> data;
wait (clk.value_changed_event() & data.posedge_event() & ready.value_changed_event());
// The events can span over multiple simulation
// cycles. For example, if clk changes at 5ns,
// a positive edge on data occurs at 8ns and ready
// changes at 10ns, then the wait is triggered at
// time 10ns.
wait (20, SC_NS);
// does NOT work with sc_bit or sc_logic:
sc_signal<bool> speed_ctrl;
wait (10, SC_NS, speed_ctrl.posedge_event());
// Waits for positive edge to occur on speed_ctrl
// for 10ns and then times out.
wait (SC_ZERO_TIME);
wait (0, SC_NS);
sc_signal<sc_logic> sac;
// sc_in<sc_logic> sync_reset;
sc_signal<sc_logic> sync_reset;
wait (sac.posedge_event());
wait (sync_reset.negedge_event());
sc_event write_back;
// sensitive << write_back;
wait (write_back);
write_back.notify();
write_back.notify (20, SC_NS);
write_back.notify(SC_ZERO_TIME);
// Trigger event in next delta cycle.
write_back.cancel(); // Cancels a delayed notification.
sc_out<bool> out_port;
out_port.initialize(0);
sc_time t_res;
t_res = sc_get_time_resolution();
cout << "The time resolution is " << sc_get_time_resolution() << endl;
double time_in_dbl;
sc_time time_res = sc_get_time_resolution();
sc_time curr_time = sc_time_stamp();
time_in_dbl = curr_time / time_res;
cout << "Time as a double value is " << time_in_dbl << endl;
time_in_dbl = sc_simulation_time();
cout << "Time is " << time_in_dbl;
sc_set_default_time_unit (100, SC_PS);
sc_time t_unit (10, SC_NS);
// NOT WORKING:
// sc_set_default_time_unit (t_unit);
sc_set_default_time_unit (100, SC_PS);
sc_time tf_unit;
tf_unit = sc_get_default_time_unit();
// Wake up SC_METHOD process after 10ns:
next_trigger (10, SC_NS);
// Wake up SC_METHOD process on a rising edge
// of reset:
next_trigger (reset.posedge_event());
return 0;
}
void DebugConnector::connection()
{
int rv;
stop();
int m_listenfd;
struct sockaddr_in m_servaddr, m_cliaddr;
m_listenfd = socket(AF_INET, SOCK_STREAM, 0);
int on = 1;
rv = setsockopt(m_listenfd, SOL_SOCKET, SO_REUSEADDR, &on, sizeof(on));
bzero(&m_servaddr, sizeof(m_servaddr));
m_servaddr.sin_family = AF_INET;
m_servaddr.sin_addr.s_addr = htonl(INADDR_ANY);
m_servaddr.sin_port = htons(m_port);
if (bind(m_listenfd, (sockaddr *) &m_servaddr, sizeof(m_servaddr)) == -1) {
cerr << "Cannot bind" << endl;
return;
}
while (true) {
if (listen(m_listenfd, 1) == -1) {
cerr << "Listen error" << endl;
return;
}
cout << "Listening on port " << m_port << endl;
socklen_t clilen = sizeof(m_cliaddr);
m_connectionfd = accept(m_listenfd, (struct sockaddr *) &m_cliaddr,
&clilen);
if (m_connectionfd < 0) {
cerr << "Error on accept" << endl;
return;
}
cout << "Connected" << endl;
while (1) {
char headerbuf[2];
rv = recv(m_connectionfd, headerbuf, 2, MSG_DONTWAIT);
if (rv == -1) {
wait(1, SC_US);
continue;
} else if (rv == 0) {
cout << sc_time_stamp() << " Connection closed or error (rv="
<< rv << ")" << endl;
break;
}
int size = headerbuf[0];
int type = headerbuf[1];
uint8_t *payload;
unsigned int paylen = size - 2;
payload = (uint8_t*) malloc(paylen);
assert(read(m_connectionfd, payload, paylen) == paylen);
handleMessage(type, payload, paylen);
free(payload);
}
close(m_connectionfd);
stop();
}
}
int sc_main(int argc, char* argv[])
{
// signal declaration
sc_clock clk("clk", 1, SC_US, 0.5);
sc_signal<sc_logic> reset;
sc_signal<sc_lv<32> > instruction;
sc_signal<sc_logic> overflow;
// module declaration
top top0("top0");
// signal connection
top0.clock(clk);
top0.reset(reset);
top0.instruction(instruction);
top0.overflow(overflow);
// Open VCD file
sc_trace_file *wf = sc_create_vcd_trace_file("test_DM_wave");
wf->set_time_unit(1, SC_NS);
// error counter for tb
int tb_error = 0;
// set signal to .vcd wave file
sc_trace(wf,clk,"clk");
sc_trace(wf,instruction,"instruction");
sc_trace(wf,overflow,"overflow");
sc_trace(wf,reset,"reset");
sc_trace(wf,top0.r1_data,"r1_data");
sc_trace(wf,top0.r2_data,"r2_data");
sc_trace(wf,top0.r3_data,"r3_data");
sc_trace(wf,top0.out_data,"mem_output");
sc_trace(wf,top0.alu_output,"alu_output");
sc_trace(wf,top0.m31out,"rw_data");
// init
reset = sc_logic('0');
instruction = sc_lv<32>("00000000000000000000000000000000");
// run simulation
sc_start(0,SC_US);
instruction = sc_lv<32>("01000100000000000000001111111111");
sc_start(1,SC_US);
cout << "@" << sc_time_stamp() << endl
<< "instruction : " << instruction << endl
<< "reset : " << reset << endl
<< "r1data :" << top0.r1_data << endl
<< "r2data :" << top0.r2_data << endl
<< "r3data :" << top0.r3_data << endl
<< "mem_output :" << top0.out_data << endl
<< "alu_output :" << top0.alu_output << endl
<< "rw_data :" << top0.m31out << endl
<< endl;
/*
// start testing here
for(int i=0 ; i<SIZE_OF_TEST ; i++)
{
instruction = sc_lv<32>(in_data_list[i]);
// add simulation time
sc_start(1,SC_US);
cout << "@" << sc_time_stamp() <<" ,instruction : " << instruction << " ,reset : " << reset
<< endl;
// error check!
temp_output = out_data_list[i];
if(out_data.read() != temp_output){
tb_error++;
#ifdef REG_DEBUG
cout << " error! " << endl;
#endif
}
}
*/
if(tb_error != 0)
cout << tb_error << " errors!" << endl;
else
cout << "pass!" << endl;
sc_start(2,SC_NS);
sc_close_vcd_trace_file(wf);
return 0;
}
// task 1 specified simply as a void(void) C-function
void task1_functionality()
{
cout << "task 1 " << " t_begin=" << sc_time_stamp() << endl; // function body
}
int sc_main (int, char *[]) {
// Definition of a task set (set to be assigned to a processor)
// with the kista::taskset_by_name_t and task_info_t classes
taskset_by_name_t task_set1;
task_info_t task_info_t1("task1",task1);
task_info_t task_info_t2("task2",task2);
task_set1["task1"] = &task_info_t1;
task_set1["task2"] = &task_info_t2;
// gs->tasks_assigned["task1"] = task_info_t("task1",task1, gs);
// gs->tasks_assigned["task2"] = task_info_t("task2",task2, gs);
// Declaration of an scheduler and assignation of the task set
// with the kista::scheduler class
scheduler scheduler1(&task_set1, "scheduler1");
// Equivalently, the scheduler can be declared...
// scheduler *scheduler1;
// ... and assigned the task set afterwards
// scheduler1 = new scheduler(&task_set1, "scheduler1"); // by default, non-preemptive, one processor
// configuring the scheduler
// enabling time slicing
#ifdef _SET_ROUND_ROBIN
#ifdef _COMPACT_STYLE
scheduler1.set_Round_Robin();
#else
scheduler1.set_preemptive();
scheduler1.enable_time_slicing();
#endif
#endif
#ifdef _SET_COOPERATIVE
scheduler1.set_preemptive();
#endif
// Tracing of the tasks and scheduler ocupation signals
// with the kista::trace method of the kista::scheduler class
scheduler1.trace_utilizations();
set_global_simulation_time_limit(sc_time(1,SC_SEC));
#ifdef _SET_ROUND_ROBIN
sc_start(); // here simulation ends through the simulation limit enabled by default by KisTA library
// That limit can be changed through the set_global_simulation_time_limit function
// The end of the simulation might not exactly end at the time fixed by the global_time_limit,
// since this limit is checked by the schedulers (so it is done at the time the first scheduling
// performed at a time over the global time limit
#else
// sc_start() // in this case, an sc_start would involve a neverending simulation, since the scheduler never gets
// the controls and no detection to check if it is over the simulation time limit is done.
sc_start(1,SC_SEC); // This way, simulation is "abruptly" terminated
// ("abruptly" in the sense that it can happenm in the middle of the execution of a task
// not necessary in the execution of
#endif
sc_stop(); // to ensure call to call backs (end_of_simulation),
// this is required for a right accounting of execution times, and starvation assesment
taskset_by_name_t::iterator ts_it;
cout << "-------------------------" << endl;
cout << "Simulation reports" << endl;
cout << "-------------------------" << endl;
for(ts_it = task_set1.begin(); ts_it != task_set1.end(); ts_it++) {
cout << ts_it->first << " task utilization : (after simulation): " << (float)(scheduler1.get_task_utilization(ts_it->first)*100.0) << "%" << endl;
}
cout << "Task Set utilization : (after simulation) " << (float)(scheduler1.get_tasks_utilization()*100.0) << "%" << endl;
cout << scheduler1.name() << " (sim) number of schedulings: " << (unsigned int)scheduler1.get_number_of_schedulings() << endl;
cout << scheduler1.name() << " (sim) number of context switches: " << (unsigned int)scheduler1.get_number_of_context_switches() << endl;
cout << scheduler1.name() << " (sim) scheduler utilization: " << (float)(scheduler1.get_scheduler_utilization()*100.0) << "%" << endl;
cout << scheduler1.name() << " (sim) platform utilization : " << (float)(scheduler1.get_platform_utilization()*100.0) << "%" << endl;
cout << "last simulation time: " << sc_time_stamp() << endl;
if(scheduler1.assess_starvation()!=true) {
cout << scheduler1.name() << " scheduler: No starvation detected. All tasks had chance to execute." << endl;
}
return 0;
}
void t3_fun() {
cout << "T3: exec. at time " << sc_time_stamp() << endl;
}
bool TProcessingElement::canShot(TPacket& packet)
{
bool shot;
double threshold;
if (TGlobalParams::traffic_distribution != TRAFFIC_TABLE_BASED)
{
if (!transmittedAtPreviousCycle)
threshold = TGlobalParams::packet_injection_rate;
else
threshold = TGlobalParams::probability_of_retransmission;
shot = (((double)rand())/RAND_MAX < threshold);
if (shot)
{
switch(TGlobalParams::traffic_distribution)
{
case TRAFFIC_RANDOM:
packet = trafficRandom();
break;
case TRAFFIC_TRANSPOSE1:
packet = trafficTranspose1();
break;
case TRAFFIC_TRANSPOSE2:
packet = trafficTranspose2();
break;
case TRAFFIC_BIT_REVERSAL:
packet = trafficBitReversal();
break;
case TRAFFIC_SHUFFLE:
packet = trafficShuffle();
break;
case TRAFFIC_BUTTERFLY:
packet = trafficButterfly();
break;
default:
assert(false);
}
}
}
else
{ // Table based communication traffic
if (never_transmit)
return false;
double now = sc_time_stamp().to_double()/1000;
bool use_pir = (transmittedAtPreviousCycle == false);
vector<pair<int,double> > dst_prob;
double threshold = traffic_table->getCumulativePirPor(local_id, (int)now, use_pir, dst_prob);
double prob = (double)rand()/RAND_MAX;
shot = (prob < threshold);
if (shot)
{
for (unsigned int i=0; i<dst_prob.size(); i++)
{
if (prob < dst_prob[i].second)
{
packet.make(local_id, dst_prob[i].first, now, getRandomSize());
break;
}
}
}
}
return shot;
}
int sc_main(int argc,char *argv[])
{
sc_signal<bool> clk, rst;
clock100 u_clkgen("u_clkgen");
u_clkgen.clk(clk);
/* MAX=128;
uint32 *code = (uint32 *) malloc(MAX * sizeof(uint32));
A = new assembler(code, MAX);
A->assemble(name(), test_program);
*/
// First processor unit (A):
sc_signal <bool> irq_0;
// sc_signal <memport_if> port1_0;
nominalunit *nominalunit_0 = new nominalunit("nominalunit_0");
nominalunit_0->clk(clk);
nominalunit_0->rst(rst);
nominalunit_0->irq(irq_0);
// nominalunit_0->port1(port1_0);
/*
sc_signal <bool> irq_1;
sc_signal <memport_if> port1_1;
nominalunit *nominalunit_1 = new nominalunit("nominalunit_1");
nominalunit_1->clk(clk);
nominalunit_1->rst(rst);
nominalunit_1->irq(irq_1);
// nominalunit_1->port1(port1_1);
sc_signal <bool> irq_2;
sc_signal <memport_if> port1_2;
nominalunit *nominalunit_2 = new nominalunit("nominalunit_2");
nominalunit_2->clk(clk);
nominalunit_2->rst(rst);
nominalunit_2->irq(irq_2);
// nominalunit_2->port1(port1_2);
sc_signal <bool> irq_3;
sc_signal <memport_if> port1_3;
nominalunit *nominalunit_3 = new nominalunit("nominalunit_3");
nominalunit_3->clk(clk);
nominalunit_3->rst(rst);
nominalunit_3->irq(irq_3);
// nominalunit_3->port1(port1_3);
sc_signal <bool> irq_4;
sc_signal <memport_if> port1_4;
nominalunit *nominalunit_4 = new nominalunit("nominalunit_4");
nominalunit_4->clk(clk);
nominalunit_4->rst(rst);
nominalunit_4->irq(irq_4);
// nominalunit_4->port1(port1_4);
sc_signal <bool> irq_5;
sc_signal <memport_if> port1_5;
nominalunit *nominalunit_5 = new nominalunit("nominalunit_5");
nominalunit_5->clk(clk);
nominalunit_5->rst(rst);
nominalunit_5->irq(irq_5);
// nominalunit_5->port1(port1_5);
sc_signal <bool> irq_6;
sc_signal <memport_if> port1_6;
nominalunit *nominalunit_6 = new nominalunit("nominalunit_6");
nominalunit_6->clk(clk);
nominalunit_6->rst(rst);
nominalunit_6->irq(irq_6);
// nominalunit_6->port1(port1_6);
#if 1
// Second processor unit (B):
sc_signal <bool> irq_7;
sc_signal <memport_if> port1_7;
nominalunit *nominalunit_7 = new nominalunit("nominalunit_7");
nominalunit_7->clk(clk);
nominalunit_7->rst(rst);
nominalunit_7->irq(irq_7);
nominalunit_7->port1(port1_7);
#endif
*/
irq_0 = 0;
/* irq_1 = 0;
irq_2 = 0;
irq_3 = 0;
irq_4 = 0;
irq_5 = 0;
irq_6 = 0;
irq_7 = 0;
*/
rst = 1;
sc_start(100, SC_NS);
// rst = 0;
printf("End of reset\n");
sc_start(5, SC_US);
cout << ("Interrupt to B\n") << sc_time_stamp() << "\n";
sc_start(10, SC_US);
cout << "Dual CPU SystemC nominal proc finished at " << sc_time_stamp() << "\n";
return 0;
}
int sc_main(int argc, char* argv[]) {
sc_signal<sc_fixed<WIDTH, 9, SC_RND> > in_data, c;
sc_signal<sc_fixed<3*WIDTH, 34, SC_RND> > d_out, d_in;
sc_signal<bool> clock;
sc_signal<bool> reset;
sc_signal<bool> wr_en;
sc_signal<bool> out_wr_en;
processing_element pe("PE");
pe.in_data(in_data);
pe.d_out(d_out);
pe.c(c);
pe.d_in(d_in);
pe.clock(clock);
pe.reset(reset);
pe.wr_en(wr_en);
pe.out_wr_en(out_wr_en);
int i = 0;
reset = 1;
cout << "@" << sc_time_stamp() << "::Asserting reset" << endl;
for(i = 0; i< 2; i++) {
clock = 0;
sc_start(1, SC_NS);
clock = 1;
sc_start(1, SC_NS);
}
reset = 0;
for(i = 0; i< 2; i++) {
clock = 0;
sc_start(1, SC_NS);
clock = 1;
sc_start(1, SC_NS);
}
cout << "@" << sc_time_stamp() << "::De-asserting reset" << endl;
wr_en = 1;
in_data = 255;
c = 0;
// sc_start(1, SC_NS);
cout << "@" << sc_time_stamp() << "::Asserting write enable for input ff and setting the input to " << in_data << endl;
for(i = 0; i < 2; i++) {
clock = 0;
sc_start(1, SC_NS);
clock = 1;
sc_start(1, SC_NS);
}
c = -1.25;
//sc_start(1, SC_NS);
cout << "@" << sc_time_stamp() << "::setting the other input to multiplier as " << c.read() << endl;
for(i = 0; i < 2; i++) {
clock = 0;
sc_start(1, SC_NS);
clock = 1;
sc_start(1, SC_NS);
}
out_wr_en = 1;
d_in = 32.125;
//sc_start(1, SC_NS);
cout << "@" << sc_time_stamp() << "::setting the other input to adder as " << d_in << endl;
for(i = 0; i < 2; i++) {
clock = 0;
sc_start(1, SC_NS);
clock = 1;
sc_start(1, SC_NS);
}
/* dff3 dff("D-FLIP FLOP");
}*/
}
virtual void run()
{
cout << sc_time_stamp() << " In Channel run() " << endl;
}
void cl_cru::fsm(int id)
{
int burst = 0, burst_ctr = 0;
PINOUT pinout, pinout_temp;
bool fill_line = false;
cs[id] = IDLE;
int hit_line=0/*,j*/;
while(true)
{
switch(cs[id]) {
case IDLE :
wait( request_cache[id].posedge_event() );
pinout = pinout_cache[id].read();
#ifdef __DEBUG_MISS_CACHE
// _drugo_ check for last address
cout << endl << name() << " ADDR " << hex << pinout.address << " - requested by " << dec << id << " @ " << sc_time_stamp() << endl;
int k,r;
for(k=0;k<miss_buff_depth;k++)
{
cout << "\t[LINE " << dec << k << "]\t";
for(r=0;r<4;r++)
printf("- %08X ", miss_buffer[k][r].address);
cout << "\n";
cout << "\t DATA\t\t";
for(r=0;r<4;r++)
printf("- %08X ", miss_buffer[k][r].data);
cout << "\n";
}
#endif
burst = (int)pinout.burst;
hit_line = IsInMissBuffer(pinout.address, id, true);
if(hit_line != RETVAL_ICACHE_MISS)
cs[id] = HIT;
else
cs[id] = MISS;
break;
case HIT :
// cout << "[" << name() << "] HIT state - core " << dec << id << " line " << dec << hit_line << " @ " << sc_time_stamp() << endl;
for (burst_ctr = 0; burst_ctr < burst; burst_ctr++)
{
wait(clock.posedge_event());
pinout_cache[id].write(miss_buffer[hit_line][burst_ctr]);
ready_cache[id].write(true);
wait(clock.posedge_event());
ready_cache[id].write(false);
//wait();
}
cs[id] = IDLE;
break;
case MISS :
//request to L3 memory only if line is not cached
pinout_L3[id].write( pinout );
request_L3[id].write( true );
// cout << "[" << name() << "] MISS state - core " << id << " addr " << hex << pinout.address << " curr line " << dec << curr_buff_line << " @ " << sc_time_stamp() << endl;
for (burst_ctr = 0; burst_ctr < burst; burst_ctr ++)
{
wait(ready_L3[id].posedge_event());
pinout_temp = pinout_L3[id].read();
// --- fill current miss buffer line ---
//check if another core has brought the line in the meanwhile
fill_line = (IsInMissBuffer(pinout.address, id, false) == RETVAL_ICACHE_MISS);
if(fill_line)
{
// if(burst_ctr == 0)
// cout << "[" << name() << "] FILLING BUFFER - core " << id << " addr " << hex << pinout.address << " curr line " << dec << curr_buff_line << " @ " << sc_time_stamp() << endl;
miss_buffer[curr_buff_line][burst_ctr] = pinout_temp;
miss_buffer[curr_buff_line][burst_ctr].address += burst_ctr*0x4;
}
pinout_cache[id].write(pinout_temp);
ready_cache[id].write(true);
wait( ready_L3[id].negedge_event() );
request_L3[id].write( false );
ready_cache[id].write( false);
}
//update line pointer if line was written
if(fill_line)
{
curr_buff_line++;
curr_buff_line %= miss_buff_depth;
}
cs[id] = IDLE;
break;
}
}
}
int sc_main (int argc, char* argv[])
{
sc_signal<bool> clock;
sc_signal<bool> reset;
sc_signal<bool> enable;
sc_signal<sc_uint<4> > counter_out;
int i = 0;
// Connect the DUT
counter_m counter("COUNTER");
counter.clock(clock);
counter.reset(reset);
counter.enable(enable);
counter.counter_out(counter_out);
// Open VCD file
sc_trace_file *wf = sc_create_vcd_trace_file("counter");
wf->set_time_unit(1, SC_NS);
// Dump the desired signals
sc_trace(wf, clock, "clock");
sc_trace(wf, reset, "reset");
sc_trace(wf, enable, "enable");
sc_trace(wf, counter_out, "count");
// Initialize all variables
reset = 0; // initial value of reset
enable = 0; // initial value of enable
for (i=0;i<5;i++) {
clock = 0;
sc_start(10, SC_NS);
clock = 1;
sc_start(10, SC_NS);
}
reset = 1; // Assert the reset
cout << "(" << sc_time_stamp() <<") Asserting Reset\n";
for (i=0;i<10;i++) {
clock = 0;
sc_start(10, SC_NS);
clock = 1;
sc_start(10, SC_NS);
}
reset = 0; // De-assert the reset
cout << "(" << sc_time_stamp() <<") De-Asserting Reset\n";
for (i=0;i<5;i++) {
clock = 0;
sc_start(10, SC_NS);
clock = 1;
sc_start(10, SC_NS);
}
cout << "(" << sc_time_stamp() <<") Asserting Enable\n";
enable = 1; // Assert enable
for (i=0;i<20;i++) {
clock = 0;
sc_start(10, SC_NS);
clock = 1;
sc_start(10, SC_NS);
}
cout << "(" << sc_time_stamp() <<") De-Asserting Enable\n";
enable = 0; // De-assert enable
cout << "(" << sc_time_stamp() <<") Terminating simulation\n";
sc_close_vcd_trace_file(wf);
// Terminate simulation
return 0;
}
END_PERIODIC_TASK
int sc_main (int, char *[]) {
sc_time sim_time;
// Definition of a task set (set to be assigned to a processor)
// with the kista::taskset_by_name_t and task_info_t classes
taskset_by_name_t task_set1;
task_info_t task_info_t1("task1",task1);
task_info_t task_info_t2("task2",task2);
task_info_t1.set_WCET(WCET_T1);
task_info_t2.set_WCET(WCET_T2);
task_info_t1.set_Period(PERIOD_T1);
task_info_t2.set_Period(PERIOD_T2);
//
// NOW WE ESTABLISH PRIORITIES (In KisTA: the lowest the value, the highest the priority, 0 reserved)
// (The user assignation of this example is the opposite to Rate Monotonic scheduling)
// You later can see how the set_rate_monotonic method makes an automatic assignation,
// which overrides the user assignation once it is invoked afterwards, within the task set
//
#ifdef _SET_USER_PRIORITIES
task_info_t1.set_priority(5);
task_info_t2.set_priority(3);
#endif
#ifdef _SET_USER_DEADLINES
task_info_t1.set_Deadline(DEADLINE_T1);
task_info_t2.set_Deadline(DEADLINE_T2);
#endif
task_set1["task1"] = &task_info_t1;
task_set1["task2"] = &task_info_t2;
// gs->tasks_assigned["task1"] = task_info_t("task1",task1, gs);
// gs->tasks_assigned["task2"] = task_info_t("task2",task2, gs);
// Declaration of an scheduler and assignation of the task set
// with the kista::scheduler class
scheduler scheduler1(&task_set1, "scheduler1");
// Equivalently, the scheduler can be declared...
// scheduler *scheduler1;
// ... and assigned the task set afterwards, at construnction time
// scheduler1 = new scheduler(&task_set1, "scheduler1"); // by default, non-preemptive, one processor
// configuring the scheduler
scheduler1.set_preemptive();
// enabling time slicing (we keep it disabled)
// scheduler1.enable_time_slicing();
#ifdef _SET_STATIC_PRIORITIES
scheduler1.set_policy(STATIC_PRIORITIES);
#endif
#ifdef _SET_RATE_MONOTONIC
scheduler1.set_rate_monotonic(); // it already includes the set_dispatch_policy(STATIC_PRIORITIES)
#endif
#ifdef _SET_DEADLINE_MONOTONIC
scheduler1.set_deadline_monotonic(); // it already includes the set_dispatch_policy(STATIC_PRIORITIES)
#endif
// Tracing of the tasks and scheduler ocupation signals
// with the kista::trace method of the kista::scheduler class
scheduler1.trace_utilizations();
tikz_activity_trace_handler gen_tikz_report_handler;
// create_tikz_activity_trace();
//gen_tikz_report_handler = create_tikz_activity_trace();
gen_tikz_report_handler = create_tikz_activity_trace("2tasks_tikz_trace");
set_scale(gen_tikz_report_handler,1.25);
set_landscape(gen_tikz_report_handler);
no_text_in_traces(gen_tikz_report_handler);
do_not_show_unactive_boxes(gen_tikz_report_handler);
set_time_stamps_max_separation(gen_tikz_report_handler,3);
only_image(gen_tikz_report_handler);
// cluster(gen_tikz_report_handler);
// compact(gen_tikz_report_handler);
sketch_report.set_file_name("ex3_sketch"); // This will set the file name of the sketch report to "ex3_sketch.tex"
// otherwise, the default name "system_sketch.tex" will be applied
sketch_report.enable();
// sketch_report.set_file_name("ex3_sketch"); // Here, it would be overriden, and the the default name used
sim_time = get_hyperperiod(task_set1);
cout << "Hyperperiod of task set : " << sim_time << endl;
cout << "Global simulation time limit : " << get_global_simulation_time_limit() << endl;
// to enable scheduling times
enable_scheduling_times();
set_scheduling_time(sc_time(1,SC_NS));
set_default_scheduling_time_calculators();
sc_start(sim_time);
cout << "End of simulation at " << sc_time_stamp() << endl;
sc_stop();
taskset_by_name_t::iterator ts_it;
cout << "-------------------------" << endl;
cout << "POST-SIM. REPORTS" << endl;
cout << "-------------------------" << endl;
cout << "*********************************************" << endl;
cout << " Utilization and Starvation Report " << endl;
cout << "*********************************************" << endl;
cout << "Hyperperiod of task set task_set1: " << get_hyperperiod(task_set1) << endl;
for(ts_it = task_set1.begin(); ts_it != task_set1.end(); ts_it++) {
cout << ts_it->first << " task utilization : (static) " << (float)(ts_it->second->utilization()*100.0) << "% (simulation): " << (float)(scheduler1.get_task_utilization(ts_it->first)*100.0) << "%" << endl;
}
cout << "Task Set utilization : (static) " << (float)(utilization(task_set1)*100.0) << "% (simulation) " << (float)(scheduler1.get_tasks_utilization()*100.0) << "%" << endl;
for(ts_it = task_set1.begin(); ts_it != task_set1.end(); ts_it++) {
cout << ts_it->first << " task density : (static) " << (float)(ts_it->second->density()*100.0) << "%" << endl;
}
cout << "Task Set density : (static) " << (float)(density(task_set1)*100.0) << "% " << endl;
cout << scheduler1.name() << " (sim) number of schedulings: " << (unsigned int)scheduler1.get_number_of_schedulings() << endl;
cout << scheduler1.name() << " (sim) scheduler utilization : " << (float)(scheduler1.get_scheduler_utilization()*100.0) << "%" << endl;
cout << scheduler1.name() << " (sim) platform utilization : " << (float)(scheduler1.get_platform_utilization()*100.0) << "%" << endl;
cout << "last simulation time: " << sc_time_stamp() << endl;
if(scheduler1.assess_starvation()!=true) {
cout << scheduler1.name() << " scheduler: No starvation detected. All tasks had chance to execute." << endl;
}
scheduler1.report_miss_deadlines();
scheduler1.report_response_times();
return 0;
}
void cl_memory::working()
{
uint32_t addr, prev_addr, size;
int burst = 0, bw, i,j;
bool wr;
PINOUT mast_pinout;
unsigned long int data;
bool must_wait = true;
ready.write(false);
while (true) {
must_wait = true;
__DELTA_L1;
if(!request.read())
wait(request.posedge_event());
// What's up?
mast_pinout = pinout.read();
bw = mast_pinout.bw;
// Word, half word or byte?
switch (bw)
{
case 0 :
size = 0x4;
break;
case 1 :
size = 0x1;
break;
case 2 :
size = 0x2;
break;
default :
cout << "Fatal error: Master " << ID << " detected a malformed data size at " << sc_time_stamp() << endl;
exit(1);
}
burst = (int)mast_pinout.burst;
wr = mast_pinout.rw;
addr = mast_pinout.address;
//////////////////////////////////
// Wait for MEM_IN_WS cycles if != 0
for(i = 0; i < (int)mem_in_ws; i++)
wait();
// ------------------------------ READ ACCESS ------------------------------
if (!wr)
{
status = CLM_ST_READ ;
trace_status = (int) status ;
for (i = 0; i < burst; i ++)
{
do {
wait();
ready.write(false);
data = this->Read(addr, bw, &must_wait);
} while(must_wait == true);
// Wait cycles between burst beat
for(j=0; j<(int)mem_bb_ws && i!=0; j++)
wait();
prev_addr = addr;
// Increment the address for the next beat
addr += size;
mast_pinout.data = data;
pinout.write(mast_pinout);
ready.write(true);
}
wait();
ready.write(false);
}
// ------------------------------ WRITE ACCESS ------------------------------
else
{
status = CLM_ST_WRITE ;
trace_status = (int) status ;
for (i = 0; i < burst; i ++)
{
do {
wait();
mast_pinout = pinout.read();
data = mast_pinout.data;
ready.write(false);
this->Write(addr, data, bw, &must_wait);
} while(must_wait == true);
// Wait cycles between burst beat
for(j=0; j<(int)mem_bb_ws && i!=0; j++)
wait( (int)mem_bb_ws );
// Increment the address for the next beat
prev_addr = addr;
addr += size;
ready.write(true);
}
wait();
ready.write(false);
}
status = CLM_ST_INACTIVE ;
trace_status = (int) status ;
}
}
void able()
{
wait();
cout << "able: " << sc_time_stamp() << endl;
}
END_TASK_AFTER_WCET
int sc_main (int, char *[]) {
// DESCRIPTION OF THE KISTA MODEL (POST-PROCESSING)
// Definition of a task set (set to be assigned to a processor)
// with the kista::taskset_by_name_t and task_info_t classes
taskset_by_name_t task_set1;
task_info_t task1_info("task1",task1);
task_info_t task2_info("task2",task2);
task_info_t task3_info("task3",task3);
task_info_t task4_info("task4",task4);
task_info_t task5_info("task5",task5);
// set WCETS
task1_info.set_WCET(WCET_task1);
task2_info.set_WCET(WCET_task2);
task3_info.set_WCET(WCET_task3);
task4_info.set_WCET(WCET_task4);
task5_info.set_WCET(WCET_task5);
// create task set
task_set1["task1"] = &task1_info;
task_set1["task2"] = &task2_info;
task_set1["task3"] = &task3_info;
task_set1["task4"] = &task4_info;
task_set1["task5"] = &task5_info;
// Declaration of an scheduler and assignation of the task set
// with the kista::scheduler class
scheduler scheduler1(&task_set1, "scheduler1");
// Equivalently, the scheduler can be declared...
// scheduler *scheduler1;
// ... and assigned the task set afterwards
// scheduler1 = new scheduler(&task_set1, "scheduler1"); // by default, non-preemptive, one processor
// configuring the scheduler
scheduler1.set_policy(STATIC_SCHEDULING);
#ifdef _ALTERNATIVE_1
scheduler1.set_static_schedule({"task2","task5", "task4", "task1", "task2","task1","task3"});
#endif
#ifdef _ALTERNATIVE_2
static_schedule_by_task_names_t my_static_schedule = {"task2","task5", "task4", "task1", "task2","task1","task3"};
scheduler1.set_static_schedule(my_static_schedule);
#endif
#ifdef _ALTERNATIVE_3
static_schedule_by_task_info_pointers_t my_static_schedule = {&task2_info,&task5_info, &task4_info, &task1_info, &task2_info, &task1_info, &task3_info};
scheduler1.set_static_schedule_by_task_ptrs(my_static_schedule);
#endif
#ifdef _ALTERNATIVE_4
static_schedule_by_task_names_t my_static_schedule2 = {"task5","task1", "task4", "task1", "task3","task2"};
scheduler1.set_static_schedule(my_static_schedule2);
#endif
#ifdef _ALTERNATIVE_5
static_schedule_by_task_names_t my_static_schedule3 = {"task2","task5","task4"}; // This is detected by kiss code
scheduler1.set_static_schedule(my_static_schedule3);
#endif
#ifdef _ALTERNATIVE_6
static_schedule_by_task_names_t my_static_schedule3 = {"task2","task5", "task4", "task1", "task2","task1","task3", "task6"}; // This is detected by kiss code
scheduler1.set_static_schedule(my_static_schedule3);
#endif
// Tracing of the tasks and scheduler ocupation signals
// with the kista::trace method of the kista::scheduler class
scheduler1.trace_utilizations();
// scheduler1.set_sufficient_global_simulation_time(0); // provoques KisTA
// scheduler1.set_sufficient_global_simulation_time(); // equivalent to ...set_sufficient_global_simulation_time(1)
scheduler1.set_sufficient_global_simulation_time(2);
sketch_report.set_file_name("ex6_sketch");
sketch_report.enable();
// SIMULATION START
sc_start();
// REPORTS (POST-PROCESSING)
// print ocupation of scheduler...
cout << scheduler1.name() << " scheduler utilization : " << (float)(scheduler1.get_scheduler_utilization()*100.0) << "%" << endl;
// ... and of assigned tasks ...
taskset_by_name_t::iterator ts_it;
for(ts_it = task_set1.begin(); ts_it != task_set1.end(); ts_it++) {
cout << ts_it->first << " task utilization : " << (float)(scheduler1.get_task_utilization(ts_it->first)*100.0) << "%" << endl;
}
cout << "Total tasks utilization : " << (float)(scheduler1.get_tasks_utilization()*100.0) << "%" << endl;
cout << scheduler1.name() << " number of schedulings: " << (unsigned int)scheduler1.get_number_of_schedulings() << endl;
cout << scheduler1.name() << " platform utilization : " << (float)(scheduler1.get_platform_utilization()*100.0) << "%" << endl;
scheduler1.assess_starvation();
cout << "last simulation time:" << sc_time_stamp() << endl;
return 0;
}
void paging::entry()
{
int address=0;
int address_conversion_factor = 0;
int dataout_tmp =0;
while (true)
{
do
{
wait();
}
while ( !(paging_csin == true) );
address = logical_address.read();
address_conversion_factor = paging_din.read();
if (address >= 5)
{
if (paging_wein.read() == true) // Write operation
{
paging_dout.write(paging_din.read());
paging_csout.write(true);
paging_weout.write(true);
physical_address.write(logical_address.read());
wait();
paging_csout.write(false);
paging_weout.write(false);
}
else // Read operation
{
paging_csout.write(true);
paging_weout.write(false);
physical_address.write(logical_address.read());
wait();
do
{
wait();
}
while ( !(icache_validin == true) );
dataout_tmp = icache_din.read();
if (PRINT_PU)
{
cout << "-----------------------" << endl;
printf( "PAGE : mem=%x\n",dataout_tmp);
cout << "PAGE : " ;
cout << " at CSIM " << sc_time_stamp() << endl;
cout << "-----------------------" << endl;
}
dataout.write(icache_din.read());
data_valid.write(true);
paging_csout.write(false);
wait();
data_valid.write(false);
wait();
}
}
}
} // end of entry function
