int sc_main(int ac, char *av[])
{
sc_trace_file *tf;
sc_signal<bool> clock;
sc_signal<sc_bv<4> > bv;
sc_signal<sc_lv<4> > sv;
proc1 P1("P1", clock, bv, sv);
tf = sc_create_wif_trace_file("test07");
sc_trace(tf, P1.obj1, "Signed");
sc_trace(tf, P1.obj2, "Unsigned");
sc_trace(tf, bv, "BV");
sc_trace(tf, sv, "SV");
clock.write(0);
sc_start(0, SC_NS);
for (int i = 0; i< 10; i++) {
clock.write(1);
sc_start(10, SC_NS);
clock.write(0);
sc_start(10, SC_NS);
}
sc_close_wif_trace_file( tf );
return 0;
}
int sc_main(int argc, char *argv[]) //(int ac, char** av)
{
sc_signal<sc_uint<1> > int1 ;
sc_signal<sc_uint<1> > int2 ;
sc_clock clk("clk", 20, SC_NS, 0.5);
// instanciate Processes
flop FLOP("flip_flop");
FLOP.clk(clk) ;
FLOP.in(int1) ;
FLOP.out(int2) ;
sc_trace_file * tf = sc_create_wif_trace_file("test");
sc_trace( tf, clk, "clk");
sc_trace( tf, int1, "int1");
sc_trace( tf, int2, "int2");
/*
sc_trace_file * tf2 = sc_create_vcd_trace_file("dump_vcd");
sc_trace( tf2, clk, "clk");
sc_trace( tf2, int1, "int1");
sc_trace( tf2, int2, "int2");
*/
sc_start(1000, SC_NS);
sc_close_wif_trace_file( tf );
return 0;
}
int sc_main(int argc, char* argv[]) {
sc_signal<bool> input_1, input_2, output;
sc_clock test_clock("TestClock", 10, SC_NS, 0.5);
sc_trace_file *trace_file;
stimulus stimulus_1("Stimulus");
stimulus_1.input_1(input_1);
stimulus_1.input_2(input_2);
stimulus_1.clock(test_clock);
monitor monitor_1("Monitor");
monitor_1.input_1(input_1);
monitor_1.input_2(input_2);
monitor_1.output(output);
monitor_1.clock(test_clock);
xor_ xor_1("Xor");
xor_1.input_1(input_1);
xor_1.input_2(input_2);
xor_1.output(output);
trace_file = sc_create_vcd_trace_file("wave");
sc_trace(trace_file, test_clock, "Clock");
sc_trace(trace_file, input_1, "Input_1");
sc_trace(trace_file, input_2, "Input_2");
sc_trace(trace_file, output, "Output");
sc_start();
sc_close_vcd_trace_file(trace_file);
return 0;
}
int sc_main(int argc, char* argv[])
{
sc_signal <unsigned int> sinalA, sinalB, sinalC;
sc_clock clock(" Clock", 10, SC_NS,0.5, 1, SC_NS);
Estimulos est("Estimulos");
Maior m("Maior");
est.A(sinalA);
est.B(sinalB);
est.Clk(clock);
m.A(sinalA);
m.B(sinalB);
m.C(sinalC);
sc_trace_file* Tf;
Tf = sc_create_vcd_trace_file("traces");
sc_trace (Tf,sinalA,"A");
sc_trace (Tf,sinalB,"B");
sc_trace (Tf,sinalC,"C");
sc_trace (Tf,clock,"Clk");
sc_start();
sc_close_vcd_trace_file(Tf);
return 0;
}
int sc_main(int argc, char* argv[]) {
sc_signal<int> out_free ;
sc_signal<int> out_available ;
sc_signal<bool> out_full ;
sc_signal<bool> out_empty ;
test_fifo u_test_fifo( "u_test_fifo" ) ;
u_test_fifo.out_free ( out_free );
u_test_fifo.out_available( out_available );
u_test_fifo.out_full ( out_full );
u_test_fifo.out_empty ( out_empty );
sc_trace_file * vcd_file;
vcd_file = sc_create_vcd_trace_file( "test_fifo" );
sc_trace( vcd_file , out_free , "out_free" );
sc_trace( vcd_file , out_available , "out_available" );
sc_trace( vcd_file , out_full , "out_full" );
sc_trace( vcd_file , out_empty , "out_empty" );
sc_start(1000, SC_NS);
sc_close_vcd_trace_file( vcd_file );
return 0;
}
int sc_main(int ac, char *av[])
{
sc_trace_file *tf;
sc_signal<bool> clock;
sc_signal<int> I;
sc_signal<char> C;
sc_signal<float> F;
sc_signal<sc_logic> L;
proc1 P1("P1", clock, I, C, F, L);
tf = sc_create_wif_trace_file("test08");
sc_trace(tf, clock, "Clock");
sc_trace(tf, I, "Int", 32);
sc_trace(tf, C, "Char", 8);
sc_trace(tf, F, "Float");
sc_trace(tf, L, "Logic");
clock.write(0);
sc_start(0, SC_NS);
for (int i = 0; i< 10; i++) {
clock.write(1);
sc_start(10, SC_NS);
clock.write(0);
sc_start(10, SC_NS);
}
sc_close_wif_trace_file( tf );
return 0;
}
int sc_main(int argc, char* argv[]) {
sc_signal<bool> t_a, t_b, t_cin, t_sum, t_cout;
full_adder f1 ("FullAdderWithHalfAdder");
// Positional association:
f1 << t_a << t_b << t_cin << t_sum << t_cout;
driver d1 ("GenerateWaveforms");
d1 << t_a << t_b << t_cin;
monitor mo1 ("MonitorWaveforms");
mo1 << t_a << t_b << t_cin << t_sum << t_cout;
if (! mo1.outfile) {
cerr << "ERROR: Unable to open output file," << " fa_with_ha.out!\n";
return (-2);
}
sc_trace_file *tf = sc_create_vcd_trace_file ("full_adder");
sc_trace(tf, t_a,"A");
sc_trace(tf, t_b, "B");
sc_trace(tf, t_cin, "CarryIn");
sc_trace(tf, t_sum, "Sum");
sc_trace(tf, t_cout, "CarryOut");
sc_start(100, SC_NS);
// mo1.outfile.close();
// d1.infile.close();
sc_close_vcd_trace_file (tf);
return(0);
}
int sc_main(int argc, char* argv[])
{
// Turn off warnings due to deprecated features
sc_core::sc_report_handler::set_actions("/IEEE_Std_1666/deprecated",
sc_core::SC_DO_NOTHING);
// Declare the channel to communicate between or_gate and its TB
sc_buffer<sc_logic> A, B, C;
// MODULE INST USING POINTERS
or_gate *OR;
OR = new or_gate("OR");
OR->a(A);// NAME BINDING
OR->b(B);
OR->c(C);
TB_or_gate TB_OR("TB_OR");
TB_OR.a(A); // NAME BINDING
TB_OR.b(B);
TB_OR.c(C);
//TB_OR(A, B, C); // POSITIONAL BINDING
#ifdef WAVE
// Generate waveform
sc_trace_file *wf = sc_create_vcd_trace_file("OR_GATE");
sc_trace(wf, OR->a, "a");
sc_trace(wf, OR->b, "b");
sc_trace(wf, OR->c, "c");
#endif
sc_start(20, SC_NS);
//sc_close_vcd_trace_file(wf);
return(0);
}
int sc_main(int argc, char* argv[])
{
sc_signal<bool> din, dout;
sc_clock clk("clk",10,SC_NS,0.5,0, SC_NS,false); // Create a clock signal
delta DUT("delta"); // Instantiate Device Under Test
DUT.din(din); // Connect ports
DUT.dout(dout);
DUT.clk(clk);
sc_trace_file *fp; // Create VCD file
fp=sc_create_vcd_trace_file("wave");// open(fp), create wave.vcd file
fp->set_time_unit(100, SC_PS); // set tracing resolution to ns
sc_trace(fp,clk,"clk"); // Add signals to trace file
sc_trace(fp,DUT.q_s,"q_s");
sc_trace(fp,din,"din");
sc_trace(fp,dout,"dout");
sc_start(31, SC_NS); // Run simulation
din=true;
sc_start(31, SC_NS); // Run simulation
din=false;
sc_start(31, SC_NS); // Run simulation
sc_close_vcd_trace_file(fp); // close(fp)
return 0;
}
int sc_main(int, char **)
{
sc_signal<bool> a, b, f;
sc_clock clk("Clk", 20, SC_NS); // 时钟周期为 20ns
// 分别定义模块 NAND 和 TB 的实例，并通过局部变量（如 a、b）将这两个实例连接起来
nand NAND("NAND");
NAND.A(a);
NAND.B(b);
NAND.F(f);
tb TB("TB");
TB.clk(clk);
TB.a(a);
TB.b(b);
TB.f(f);
// 生成仿真结果波形文件
sc_trace_file *tf = sc_create_vcd_trace_file("NAND");
sc_trace(tf, NAND.A, "A");
sc_trace(tf, NAND.B, "B");
sc_trace(tf, NAND.F, "F");
sc_trace(tf, TB.clk, "CLK");
sc_start(200, SC_NS); // 仿真时长 200ns
sc_close_vcd_trace_file(tf);
return 0;
}
/**
* main
*/
int sc_main(int argc, char* argv[]) {
sc_set_time_resolution(1, SC_PS);
sc_clock clock("clk", 1, SC_NS);
// Shift reg is declared but not implemented
sc_signal<int> shiftreg_in;
sc_signal<int> shiftreg_out;
sc_trace_file *tf = sc_create_vcd_trace_file("wave");
sc_write_comment(tf, "Simulation of Shift Reg at Elaboration Time Resolution");
sc_trace(tf, clock, "Clock");
sc_trace(tf, shiftreg_in, "shiftreg_in");
sc_trace(tf, shiftreg_out, "shiftreg_out");
sc_start(30, SC_NS);
sc_close_vcd_trace_file(tf);
system("pause");
return 0;
}
void sc_trace(sc_trace_file *tf, const packet &p, const std::string &name)
{
sc_trace(tf, p.src_x, name+".src.x");
sc_trace(tf, p.src_y, name+".src.y");
sc_trace(tf, p.dest_x, name+".dest.x");
sc_trace(tf, p.dest_y, name+".dest.y");
sc_trace(tf, p.token, name+".token");
}
//------------------------------------------------------------------------
void DAT_CNT::AddToTrace(sc_trace_file *tf)
{
char s[255];
printf("Module name: %s(%s)\n",name(),basename());
sprintf(s,"QI(0)_%s(%s)",name(),basename());
printf(" %s\n",s);
sc_trace(tf,QI[0],s);
sprintf(s,"QI(1)_%s(%s)",name(),basename());
printf(" %s\n",s);
sc_trace(tf,QI[1],s);
}
/*
* evt_start_event()
*
* Change an event from WAITING to RUNNING.
*/
static void
evt_start_event (sc_gameref_t game, sc_int event)
{
const sc_filterref_t filter = gs_get_filter (game);
const sc_prop_setref_t bundle = gs_get_bundle (game);
sc_vartype_t vt_key[4];
sc_int time1, time2, obj1, obj1dest;
if (evt_trace)
sc_trace ("Event: starting event %ld\n", event);
/* If event is visible, print its start text. */
if (evt_can_see_event (game, event))
{
const sc_char *starttext;
/* Get and print start text. */
vt_key[0].string = "Events";
vt_key[1].integer = event;
vt_key[2].string = "StartText";
starttext = prop_get_string (bundle, "S<-sis", vt_key);
if (!sc_strempty (starttext))
{
pf_buffer_string (filter, starttext);
pf_buffer_character (filter, '\n');
}
/* Handle any associated resource. */
vt_key[2].string = "Res";
vt_key[3].integer = 0;
res_handle_resource (game, "sisi", vt_key);
}
/* Move event object to destination. */
vt_key[0].string = "Events";
vt_key[1].integer = event;
vt_key[2].string = "Obj1";
obj1 = prop_get_integer (bundle, "I<-sis", vt_key) - 1;
vt_key[2].string = "Obj1Dest";
obj1dest = prop_get_integer (bundle, "I<-sis", vt_key) - 1;
evt_move_object (game, obj1, obj1dest);
/* Set the event's state and time. */
gs_set_event_state (game, event, ES_RUNNING);
vt_key[2].string = "Time1";
time1 = prop_get_integer (bundle, "I<-sis", vt_key);
vt_key[2].string = "Time2";
time2 = prop_get_integer (bundle, "I<-sis", vt_key);
gs_set_event_time (game, event, sc_randomint (time1, time2));
if (evt_trace)
sc_trace ("Event: start event handling done, %ld\n", event);
}
wave::wave(sc_module_name nm) //Constructor{{{
: sc_module(nm)
{
// Process registration
SC_THREAD(wave_thread);
// temperature initialization
tracefile = sc_create_vcd_trace_file("wave");
sc_trace(tracefile,oscillate,"osc");
sc_trace(tracefile,pressure,"pressure");
sc_trace(tracefile,temperature,"temperature");
sc_trace(tracefile,cylinder,"cylinder");
}//endconstructor }}}
//----------------------------------------------------------------------------
// Architecture implementation and test of pitch detector
//----------------------------------------------------------------------------
Arch::Arch(sc_module_name name,
int samples) :
sc_module(name),
inAdapt("inAdapt"),
outAdapt("outAdapt"),
clock("clock", 20, SC_NS), // 50 mHz
sample_clock("sample_clock", 21, SC_US), // 48 kHz
reset("reset"),
in_data("in_data"),
out_data("out_data"),
instNSDFArch("NSDFArch"),
monitor_rtl("monitor_rtl", samples, rtl_file, false),
m_samples(samples)
{
reset.write(false);
// Input adapter that wraps the fifo fir input to signals
inAdapt.clock(clock);
inAdapt.reset(reset);
inAdapt.sample_clock(sample_clock);
inAdapt.out_data(in_data);
// Timed architecture version of NSDF algorithm
instNSDFArch.clock(clock);
instNSDFArch.reset(reset);
instNSDFArch.sample_clock(sample_clock);
instNSDFArch.in_data(in_data);
instNSDFArch.out_data(out_data);
// Output adapter that wraps the fir signals to output fifo
outAdapt.clock(clock);
outAdapt.reset(reset);
outAdapt.sample_clock(sample_clock);
outAdapt.in_data(out_data);
// Monitor of filtered output result from RTL level
monitor_rtl.in(outAdapt);
// Create tacefile
tracefile = sc_create_vcd_trace_file("PitchDetector");
if (!tracefile) cout << "Could not create trace file." << endl;
else cout << "Created PitchDetector.vcd" << endl;
// Set resolution of trace file to be in 1 NS
tracefile->set_time_unit(1, SC_NS);
sc_trace(tracefile, clock.signal(), "clock");
sc_trace(tracefile, sample_clock.signal(), "sample_clock");
sc_trace(tracefile, reset, "reset");
sc_trace(tracefile, in_data, "in_data");
sc_trace(tracefile, out_data, "out_data");
}
static void
loc_debug_dump_bool_table (const sc_char *label,
sc_int count, const sc_bool table[])
{
sc_int index_;
sc_trace ("loc_locale_tables.%s = {\n ", label);
for (index_ = 0; index_ < TABLE_SIZE; index_++)
{
sc_trace ("%s%s", table[index_] ? "T" : "F",
loc_debug_dump_new_line (index_, count) ? "\n " : "");
}
sc_trace ("\n}\n");
}
static void
loc_debug_dump_char_table (const sc_char *label,
sc_int count, const sc_char table[])
{
sc_int index_;
sc_trace ("loc_locale_tables.%s = {\n ", label);
for (index_ = 0; index_ < TABLE_SIZE; index_++)
{
sc_trace ("%02lx%s", (sc_int) (sc_byte) table[index_],
loc_debug_dump_new_line (index_, count) ? "\n " : " ");
}
sc_trace ("\n}\n");
}
int
sc_main(int argc, char *argv[])
{
// sc_clock clk1("clk1", 10, SC_NS, 0.5);
// sc_clock clk2("clk2", 12, SC_NS, 0.5);
sc_signal<bool> clk1( "clk1" );
sc_signal<bool> clk2( "clk2" );
foo FOO("FOO");
FOO.clk1(clk1);
FOO.clk2(clk2);
sc_trace_file *tf = sc_create_vcd_trace_file("test");
// sc_trace(tf, clk1.signal(), "clk1");
// sc_trace(tf, clk2.signal(), "clk2");
sc_trace(tf, clk1, "clk1");
sc_trace(tf, clk2, "clk2");
sc_start(0, SC_NS);
clk1 = 0;
clk2 = 0; // 0 ns
sc_start(3, SC_NS);
clk2 = 1; // 3 ns +
sc_start(2, SC_NS);
clk1 = 1; // 5 ns +
sc_start(4, SC_NS);
clk2 = 0; // 9 ns
sc_start(1, SC_NS);
clk1 = 0; // 10 ns
sc_start(5, SC_NS);
clk2 = 1; // 15 ns +
sc_start(0, SC_NS);
clk1 = 1; // 15 ns +
sc_start(5, SC_NS);
clk1 = 0; // 20 ns
sc_start(1, SC_NS);
clk2 = 0; // 21 ns
sc_start(4, SC_NS);
clk1 = 1; // 25 ns +
sc_start(2, SC_NS);
clk2 = 1; // 27 ns +
sc_start(3, SC_NS);
clk1 = 0; // 30 ns
sc_close_vcd_trace_file(tf);
return 0;
}
int sc_main(int argc, char *argv[]) {
sc_set_time_resolution(1.0, SC_NS);
sc_clock clk("clock", 20.84, SC_NS);
sc_signal<bool> rst;
sc_signal<bool> data_out_wr, oe_wr;
sc_signal<sc_uint<8>> data_out, oe, data_in;
sc_signal_rv<8> pins;
gpio i_gpio("GPIO");
test_gpio i_test("TEST");
i_gpio.clk(clk);
i_gpio.rst(rst);
i_test.clk(clk);
i_test.rst(rst);
i_test.data_out(data_out);
i_test.data_out_wr(data_out_wr);
i_test.oe(oe);
i_test.oe_wr(oe_wr);
i_test.data_in(data_in);
i_test.pin(pins);
i_gpio.data_out(data_out);
i_gpio.data_out_wr(data_out_wr);
i_gpio.oe(oe);
i_gpio.oe_wr(oe_wr);
i_gpio.data_in(data_in);
i_gpio.pin(pins);
#ifdef VCD_OUTPUT_ENABLE
sc_trace_file *vcd_log = sc_create_vcd_trace_file("TEST_GPIO");
sc_trace(vcd_log, clk, "Clk");
sc_trace(vcd_log, rst, "Reset_n");
sc_trace(vcd_log, pins, "Pins");
#endif
srand((unsigned int)(time(NULL) & 0xffffffff));
sc_start();
#ifdef VCD_OUTPUT_ENABLE
sc_close_vcd_trace_file(vcd_log);
#endif
return i_test.error_cnt;
}
void
loc_debug_dump (void)
{
sc_trace ("Locale: debug dump follows...\n");
loc_check_tables_synchronized (loc_locale);
sc_trace ("loc_locale_tables"
".locale->name = %s\n", loc_locale_tables.locale->name);
loc_debug_dump_bool_table ("isspace", 64, loc_locale_tables.isspace);
loc_debug_dump_bool_table ("isdigit", 64, loc_locale_tables.isdigit);
loc_debug_dump_bool_table ("isalpha", 64, loc_locale_tables.isalpha);
loc_debug_dump_char_table ("toupper", 16, loc_locale_tables.toupper);
loc_debug_dump_char_table ("tolower", 16, loc_locale_tables.tolower);
}
int sc_main(int argc, char* argv[]){
sc_signal<bool> reset;
sc_signal<bool> ld;
sc_signal<bool> lshift;
sc_signal<bool> rshift;
sc_signal<bool> leftin;
sc_signal<bool> rightin;
sc_signal<sc_bv<8> > in;
sc_signal<sc_bv<8> > out;
sc_clock clk ("clk", 2, SC_US); // a clock with a period of 2 �-sec
shiftreg sr("sr0");
sr.clk(clk);
sr.reset(reset);
sr.ld(ld);
sr.lshift(lshift);
sr.rshift(rshift);
sr.leftin(leftin);
sr.rightin(rightin);
sr.in(in);
sr.out(out);
stim st("stim0");
st.reset(reset);
st.ld(ld);
st.lshift(lshift);
st.rshift(rshift);
st.leftin(leftin);
st.rightin(rightin);
st.in(out);
st.out(in);
sc_trace_file *tf; // Signal tracing
tf=sc_create_vcd_trace_file("shiftreg"); // create new trace file
tf->set_time_unit(0.5,SC_US); // set time resolution to 0.5 �-sec (let's do a bit oversampling ;-))
sc_trace(tf,clk,"clk");
sc_trace(tf,reset,"reset");
sc_trace(tf,ld,"ld");
sc_trace(tf,lshift,"lshift");
sc_trace(tf,rshift,"rshift");
sc_trace(tf,leftin,"leftin");
sc_trace(tf,rightin,"rightin");
sc_trace(tf,in,"in");
sc_trace(tf,out,"out");
sc_start(100,SC_US); // run the simulation for 100 �-sec
sc_close_vcd_trace_file(tf); // close trace file
return 0;
};
/*
* evt_fixup_v390_v380_immediate_restart()
*
* Versions 3.9 and 3.8 differ from version 4.0 on immediate restart; they
* "miss" the event start actions and move one step into the event without
* comment. It's arguable if this is a feature or a bug; nevertheless, we
* can do the same thing here, though it's ugly.
*/
static sc_bool
evt_fixup_v390_v380_immediate_restart (sc_gameref_t game, sc_int event)
{
const sc_prop_setref_t bundle = gs_get_bundle (game);
sc_vartype_t vt_key[3];
sc_int version;
vt_key[0].string = "Version";
version = prop_get_integer (bundle, "I<-s", vt_key);
if (version < TAF_VERSION_400)
{
sc_int time1, time2;
if (evt_trace)
sc_trace ("Event: applying 3.9/3.8 restart fixup\n");
/* Set to running state. */
gs_set_event_state (game, event, ES_RUNNING);
/* Set up event time to be one less than a proper start. */
vt_key[0].string = "Events";
vt_key[1].integer = event;
vt_key[2].string = "Time1";
time1 = prop_get_integer (bundle, "I<-sis", vt_key);
vt_key[2].string = "Time2";
time2 = prop_get_integer (bundle, "I<-sis", vt_key);
gs_set_event_time (game, event, sc_randomint (time1, time2) - 1);
}
/* Return TRUE if we applied the fixup. */
return version < TAF_VERSION_400;
}
int sc_main(int argc, char* argv[])
{
sc_signal<bool> s_sig;
sc_signal<bool> q_sig, qn_sig;
sc_clock clk_sig("TestClock", 10, SC_NS, 0.5);
TestGenerator tg("test_generator");
tg.s_out(s_sig);
tg.clk(clk_sig);
//#define TEST_S_LATCH_V0
//#define TEST_S_LATCH_V1
#define TEST_S_LATCH_WITH_TWO_OUT
#ifdef TEST_S_LATCH_V0
SLatchV0 DUT("SLatchV0");
#endif
#ifdef TEST_S_LATCH_V1
SLatchV1 DUT("SLatchV1");
#endif
#ifdef TEST_S_LATCH_WITH_TWO_OUT
SLatchWithTwoOut DUT("SLatchWithTwoOut");
#endif
DUT.clk_in(clk_sig);
DUT.set_in(s_sig);
#ifndef TEST_S_LATCH_V0
DUT.q_out(q_sig);
DUT.qn_out(qn_sig);
#endif
sc_trace_file* p_trace_file;
p_trace_file = sc_create_vcd_trace_file("traces");
sc_trace(p_trace_file, s_sig , "set" );
sc_trace(p_trace_file, DUT.reset_sig , "reset" );
sc_trace(p_trace_file, clk_sig , "clk" );
sc_trace(p_trace_file, DUT.a_sig , "a" );
sc_trace(p_trace_file, DUT.b_sig , "b" );
sc_trace(p_trace_file, DUT.q_internal_sig , "q_internal_sig" );
sc_trace(p_trace_file, DUT.qn_internal_sig , "qn_internal_sig" );
#ifndef TEST_S_LATCH_V0
sc_trace(p_trace_file, q_sig , "q_sig" );
sc_trace(p_trace_file, qn_sig , "qn_sig" );
#endif
cout << "start simulation for " << DUT.name() << endl;
sc_start(70, SC_NS);
sc_close_vcd_trace_file(p_trace_file);
return 0;
}
int sc_main(int argc, char *argv[])
{
sc_signal<bool> or_1,or_2,and_3,and_4,and_5,and_6,nor_7,CO,SUM,A,B,CI;
OR2 or1("or1");
OR2 or8("or8");
OR3 or2("or2");
AND2 and3("and3");
AND2 and4("and4");
AND2 and5("and5");
AND3 and6("and6");
NOR2 nor7("nor7");
INV inv9("inv9");
or1.a(A); or1.b(B); or1.o(or_1);
or2.a(A); or2.b(B); or2.c(CI); or2.o(or_2);
and3.a(or_1); and3.b(CI); and3.o(and_3);
and4.a(A); and4.b(B); and4.o(and_4);
and5.a(nor_7); and5.b(or_2); and5.o(and_5);
and6.a(A); and6.b(B); and6.c(CI); and6.o(and_6);
nor7.a(and_3); nor7.b(and_4); nor7.o(nor_7);
or8.a(and_5); or8.b(and_6); or8.o(SUM);
inv9.a(nor_7); inv9.o(CO);
//sc_initialize(); // initialize the simulation engine
// create the file to store simulation results
sc_trace_file *tf = sc_create_vcd_trace_file("trace");
// 4: specify the signals we’d like to record in the trace file
sc_trace(tf, A, "A"); sc_trace(tf, B, "B");
sc_trace(tf, CI, "CI");
sc_trace(tf, SUM, "SUM"); sc_trace(tf, CO, "CO");
// 5: put values on the input signals
A=0; B=0; CI=0; // initialize the input values
sc_start(10, SC_PS);
for( int i = 0 ; i < 8 ; i++ ) // generate all input combinations
{
A = ((i & 0x1) != 0); // value of A is the bit0 of i
B = ((i & 0x2) != 0); // value of B is the bit1 of i
CI = ((i & 0x4) != 0); // value of CI is the bit2 of i
sc_start(10, SC_PS); // evaluate
}
sc_close_vcd_trace_file(tf); // close file and we’re done
return 0;
}
Mod(const sc_module_name& name) : sc_module(name), a("a")
{
SC_METHOD(foo);
sensitive << clk.pos();
dont_initialize();
sc_trace(sc_tf, a, a.name());
}
int sc_main(int argc, char *argv[]){
sc_signal<bool> clock, reset;
sc_signal<unsigned short int> count_val;
sc_signal<char> v_hi, v_lo;
sc_set_time_resolution(1, SC_US);
stimul stim("stimuli_mod");
stim.clk(clock);
stim.res(reset);
counter count("counter");
count.clk(clock);
count.res(reset);
count.cnt(count_val);
bcd_decoder bcd("bcd_decode");
bcd.val(count_val);
bcd.hi(v_hi);
bcd.lo(v_lo);
sc_trace_file *tf = sc_create_vcd_trace_file("traces");
sc_trace(tf, reset, "reset");
sc_trace(tf, clock, "clock");
sc_trace(tf, count_val, "counter_value");
sc_trace(tf, v_hi, "BCD_High");
sc_trace(tf, v_lo, "BCD_low");
int n_cycles;
if(argc != 2){
cout << "default n_cycles = 200\n";
n_cycles = 200;
}
else
n_cycles = atoi(argv[1]);
sc_start(n_cycles, SC_US);
sc_close_vcd_trace_file(tf);
return 0;
}
int
sc_main (int argc, char *argv[])
{
sc_clock clk ("clk", 1, SC_US);
rng *rng1;
stimulus *st1;
rng1 = new rng ("rng");
st1 = new stimulus ("stimulus");
sc_signal < bool > reset;
sc_signal < bool > loadseed_i;
sc_signal < sc_uint < 32 > >seed_i;
sc_signal < sc_uint < 32 > >number_o;
rng1->clk (clk);
rng1->reset (reset);
rng1->loadseed_i (loadseed_i);
rng1->seed_i (seed_i);
rng1->number_o (number_o);
st1->clk (clk);
st1->reset (reset);
st1->loadseed_o (loadseed_i);
st1->seed_o (seed_i);
st1->number_i (number_o);
sc_trace_file *tf = sc_create_vcd_trace_file("rng_wave");
sc_write_comment(tf, "Random Number Generator wave trace");
tf->set_time_unit(1, SC_US);
sc_trace(tf, reset, "Reset");
sc_trace(tf, loadseed_i, "InitialSeed");
sc_trace(tf, seed_i, "Seed");
sc_trace(tf, number_o, "RandomNumber");
sc_start (1, SC_SEC);
sc_close_vcd_trace_file(tf);
return 0;
}
int sc_main(int argc, char* argv[])
{
sc_signal<sc_uint<8> > ain, bin, ra, rb;
sc_signal<sc_uint<16> > result ,rc;
sc_signal<bool> ready, start;
sc_clock clk("clk",10,SC_NS,0.5); // Create a clock signal
sc_trace(fp, clk, "clk");
sc_trace(fp, ain, "A");
sc_trace(fp, bin, "B");
sc_trace(fp, result, "C");
sc_trace(fp, ra, "RA");
sc_trace(fp, rb, "RB");
sc_trace(fp, rc, "RC");
sc_trace(fp, ready, "Ready");
sc_trace(fp, start, "Start");
multiplier DUT("multiplier"); // Instantiate Device Under Test
DUT.ain(ain);
DUT.bin(bin);
DUT.ra(ra);
DUT.rb(rb);
DUT.rc(rc);
DUT.ready(ready);
DUT.start(start);
DUT.result(result);
DUT.clk(clk);
stim STIM("stimulus"); // Instantiate stimulus generator
STIM.clk(clk);
STIM.ain(ain);
STIM.bin(bin);
STIM.ready(ready);
STIM.start(start);
check CHECK("check");
CHECK.clk(clk);
CHECK.ain(ain);
CHECK.bin(bin);
CHECK.ready(ready);
CHECK.result(result);
sc_start(150, SC_NS); // Run simulation
sc_close_vcd_trace_file(fp);
return 0; // Return OK, no errors.
}
int sc_main (int argc, char * argv[]) {
sc_clock clk ("my_clock",1,0.5);
RegisterTest *rs = new RegisterTest("RegisterTest");
rs->clock(clk.signal());
sc_trace_file *tf = sc_create_vcd_trace_file("RegisterTest");
sc_trace(tf,rs->clock,"clock");
sc_trace(tf,rs->sel,"sel");
sc_trace(tf,rs->in, "in");
sc_trace(tf,rs->out, "out");
sc_trace(tf,rs->rwBit, "rwBit");
sc_start();
sc_close_vcd_trace_file(tf);
return 0;
}