int up_timerisr(int irq, void *context, void *priv)
{
/* Process timer interrupt */
sched_process_timer();
return 0;
}
int up_timerisr(int irq, uint32_t *regs, FAR void *arg)
{
/* Process timer interrupt */
#ifdef CONFIG_DVFS
lc823450_dvfs_tick_callback();
#endif
#ifdef CONFIG_LC823450_MTM0_TICK
/* Clear the interrupt (BEVT) */
putreg32(1 << 1, rMT00STS);
#endif
sched_process_timer();
#ifdef CONFIG_LCA_SOUNDSKIP_CHECK
extern void lca_check_soundskip(void);
lca_check_soundskip();
#endif
#ifdef CHECK_INTERVAL
_timer_val = !_timer_val;
lc823450_gpio_write(TIMER_PIN, _timer_val);
#endif
#ifdef CONFIG_HSUART
hsuart_wdtimer();
#endif /* CONFIG_HSUART */
return 0;
}
int up_timerisr(int irq, uint32_t * regs)
#endif
{
static uint32_t tick;
/* Process timer interrupt */
sched_process_timer();
/* Clear the MR0 match interrupt */
tmr_putreg8(TMR_IR_MR0I, TMR_IR_OFFSET);
/* Reset the VIC as well */
#ifdef CONFIG_VECTORED_INTERRUPTS
/* write any value to VICAddress to acknowledge the interrupt */
vic_putreg(0, VIC_ADDRESS_OFFSET);
#endif
if (tick++ > 100)
{
tick = 0;
up_statledoff();
}
else
up_statledon();
return 0;
}
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
sched_process_timer();
#else
/* This would be an appropriate place to put some MCU-specific logic to
* sleep in a reduced power mode until an interrupt occurs to save power
*/
/* This is a kludge that I still don't understand. The call to kmm_trysemaphore()
* in the os_start.c IDLE loop seems necessary for the good health of the IDLE
* loop. When the work queue is enabled, this logic is removed from the IDLE
* loop and it appears that we are somehow left idling with interrupts non-
* functional. The following should be no-op, it just disables then re-enables
* interrupts. But it fixes the problem and will stay here until I understand
* the problem/fix better.
*
* And no, the contents of the CP0 status register are not incorrect. But for
* some reason the status register needs to be re-written again on this thread
* for it to take effect. This might be a PIC32-only issue?
*/
#ifdef CONFIG_SCHED_WORKQUEUE
irqstate_t flags = enter_critical_section();
leave_critical_section(flags);
#endif
#endif
}
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
sched_process_timer();
#else
/* If the g_dma_inprogress is zero, then there is no DMA in progress. This
* value is needed in the IDLE loop to determine if the IDLE loop should
* go into lower power power consumption modes. According to the LPC17xx
* User Manual: "The DMA controller can continue to work in Sleep mode, and
* has access to the peripheral SRAMs and all peripheral registers. The
* flash memory and the Main SRAM are not available in Sleep mode, they are
* disabled in order to save power."
*/
#ifdef CONFIG_LPC17_GPDMA
if (g_dma_inprogress == 0)
#endif
{
/* Sleep until an interrupt occurs in order to save power */
BEGIN_IDLE();
asm("WFI");
END_IDLE();
}
#endif
}
static int sam_timerisr(int irq, uint32_t *regs, void *arg)
{
/* Process timer interrupt */
sched_process_timer();
return 0;
}
int up_timerisr(int irq, uint32_t *regs)
{
/* Process timer interrupt */
sched_process_timer();
return 0;
}
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts,
* then process "fake" timer interrupts. Hopefully, something
* will wake up.
*/
sched_process_timer();
#endif
}
int up_timerisr(int irq, uint32_t *regs)
{
/* Clear the pending timer interrupt */
putreg32(RTC_INT_TOPI, AVR32_RTC_ICR);
/* Process timer interrupt */
sched_process_timer();
return 0;
}
int up_timerisr(int irq, void *context)
{
/* Clear event pending */
timer0_ev_pending_write(timer0_ev_pending_read());
/* Process timer interrupt */
sched_process_timer();
return 0;
}
int up_timerisr(int irq, uint32_t *regs)
{
/* Clear the pending timer interrupt */
putreg32(INT_T1, PIC32MX_INT_IFS0CLR);
/* Process timer interrupt */
sched_process_timer();
return 0;
}
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
sched_process_timer();
#else
up_idlepm();
/* SW-425 */
if (tsb_get_rev_id() > tsb_rev_es2) {
asm("wfi");
} else {
/* We theorize that instruction fetch on the bridge silicon may stall an
* in-progress USB DMA transfer. The ideal solution is to halt the processor
* during idle via WFI (wait for interrupt), but that degrades the JTAG
* debugging experience (see discussion below).
*
* For es2 builds, we'll try a work-around suggested by Olin Siebert, namely
* to execute a sequence of 16-bit nop instructions. The theory is that the CM3
* core will fetch two 16-bit instructions at a time, but execute them
* sequentially, dropping instruction fetch bandwidth by 50% during idle
* periods, and offering USB DMA transfers the opportunity to progress and
* complete.
*/
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
}
#endif
}
int up_timerisr(int irq, uint32_t *regs)
{
uint8_t reg8;
/* Process timer interrupt */
sched_process_timer();
/* Clear ITU0 interrupt status flag */
reg8 = getreg8(SH1_ITU0_TSR);
reg8 &= ~SH1_ITUTSR_IMFA;
putreg8(reg8, SH1_ITU0_TSR);
return 0;
}
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
sched_process_timer();
#else
/* Sleep until an interrupt occurs to save power */
asm("WFI");
#endif
}
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
sched_process_timer();
#else
/* Perform IDLE mode power management */
BEGIN_IDLE();
stm32_idlepm();
END_IDLE();
#endif
}
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
sched_process_timer();
#else
/* Perform IDLE mode power management */
up_idlepm();
/* Sleep until an interrupt occurs to save power.
*
* NOTE: There is an STM32F107 errata that is fixed by the following
* workaround:
*
* "2.17.11 Ethernet DMA not working after WFI/WFE instruction
* Description
* If a WFI/WFE instruction is executed to put the system in sleep mode
* while the Ethernet MAC master clock on the AHB bus matrix is ON and all
* remaining masters clocks are OFF, the Ethernet DMA will be not able to
* perform any AHB master accesses during sleep mode."
*
* Workaround
* Enable DMA1 or DMA2 clocks in the RCC_AHBENR register before
* executing the WFI/WFE instruction."
*
* Here the workaround is just to avoid SLEEP mode for the connectivity
* line parts if Ethernet is enabled. The errate recommends a more
* general solution: Enabling DMA1/2 clocking in stm32f10xx_rcc.c if the
* STM32107 Ethernet peripheral is enabled.
*/
#if !defined(CONFIG_STM32_CONNECTIVITYLINE) || !defined(CONFIG_STM32_ETHMAC)
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG))
BEGIN_IDLE();
asm("WFI");
END_IDLE();
#endif
#endif
#endif
}
int up_timerisr(int irq, uint32_t *regs)
#endif
{
/* Process timer interrupt */
sched_process_timer();
/* Clear the MR0 match interrupt */
tmr_putreg8(LPC214X_TMR_IR_MR0I, LPC214X_TMR_IR_OFFSET);
/* Reset the VIC as well */
#ifdef CONFIG_VECTORED_INTERRUPTS
vic_putreg(0, LPC214X_VIC_VECTADDR_OFFSET);
#endif
return 0;
}
int up_timerisr(int irq, uint32_t *regs)
{
uint32_t tstat;
int ret = -EIO;
/* Get and clear the interrupt status */
tstat = getreg32(IMX_TIMER1_TSTAT);
putreg32(0, IMX_TIMER1_TSTAT);
/* Verify that this is a timer interrupt */
if ((tstat & TIMER_TSTAT_COMP) != 0)
{
/* Process timer interrupt */
sched_process_timer();
ret = OK;
}
return ret;
}
int up_timerisr(int irq, uint32_t *regs)
{
uint16_t ocar;
/* Clear all the output compare A interrupt status bit */
putreg16(~STR71X_TIMERSR_OCFA, STR71X_TIMER0_SR);
/* Set up for the next compare match. We could either reset
* the OCAR and CNTR to restart, or simply update the OCAR as
* follows to that the match occurs later without resetting:
*/
ocar = getreg16(STR71X_TIMER0_OCAR);
ocar += OCAR_VALUE;
putreg16(ocar, STR71X_TIMER0_OCAR);
/* Process timer interrupt */
sched_process_timer();
return 0;
}
void up_idle(void)
{
#if defined(CONFIG_ARCH_LEDS) && defined(CONFIG_ARCH_BRINGUP)
g_ledtoggle++;
if (g_ledtoggle == 0x80)
{
up_ledon(LED_IDLE);
}
else if (g_ledtoggle == 0x00)
{
up_ledoff(LED_IDLE);
}
#endif
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts,
* then process "fake" timer interrupts. Hopefully, something
* will wake up.
*/
sched_process_timer();
#endif
}
static int ez80_timerisr(int irq, chipreg_t *regs, void *arg)
{
/* Read the appropriate timer0 register to clear the interrupt */
#ifdef _EZ80F91
(void)inp(EZ80_TMR0_IIR);
#else
/* _EZ80190, _EZ80L92, _EZ80F92, _EZ80F93 */
(void)inp(EZ80_TMR0_CTL);
#endif
/* Process timer interrupt */
sched_process_timer();
/* Architecture specific hook into the timer interrupt handler */
#ifdef CONFIG_ARCH_TIMERHOOK
up_timerhook();
#endif
return 0;
}
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
sched_process_timer();
#else
/* Perform IDLE mode power management */
up_idlepm();
/* Sleep until an interrupt occurs to save power. */
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG))
BEGIN_IDLE();
asm("WFI");
END_IDLE();
#endif
#endif
}
static bool systemtick(FAR uint32_t *next_interval_us)
{
sched_process_timer();
return true; // reload, no change to interval
}
void up_idle(void)
{
/* If the system is idle, then process "fake" timer interrupts.
* Hopefully, something will wake up.
*/
sched_process_timer();
/* Run the network if enabled */
#ifdef CONFIG_NET
uipdriver_loop();
#endif
/* Fake some power management stuff for testing purposes */
#ifdef CONFIG_PM
{
static enum pm_state_e state = PM_NORMAL;
enum pm_state_e newstate;
newstate = pm_checkstate();
if (newstate != state)
{
if (pm_changestate(newstate) == OK)
{
state = newstate;
}
}
}
#endif
/* Wait a bit so that the sched_process_timer() is called close to the
* correct rate.
*/
#if defined(CONFIG_SIM_WALLTIME) || defined(CONFIG_SIM_X11FB)
(void)up_hostusleep(1000000 / CLK_TCK);
/* Handle X11-related events */
#ifdef CONFIG_SIM_X11FB
if (g_x11initialized)
{
/* Drive the X11 event loop */
#ifdef CONFIG_SIM_TOUCHSCREEN
if (g_eventloop)
{
up_x11events();
}
#endif
/* Update the display periodically */
g_x11refresh += 1000000 / CLK_TCK;
if (g_x11refresh > 500000)
{
up_x11update();
}
}
#endif
#endif
}
void up_idle(void)
{
#ifdef CONFIG_SMP
/* In the SMP configuration, only one CPU should do these operations. It
* should not matter which, however.
*/
static volatile spinlock_t lock;
/* The one that gets the lock is the one that executes the IDLE operations */
if (up_testset(&lock) != SP_UNLOCKED)
{
/* We didn't get it... Give other pthreads/CPUs a shot and try again
* later.
*/
pthread_yield();
return;
}
#endif
#ifdef CONFIG_SCHED_TICKLESS
/* Driver the simulated interval timer */
up_timer_update();
#else
/* If the system is idle, then process "fake" timer interrupts.
* Hopefully, something will wake up.
*/
sched_process_timer();
#endif
#if defined(CONFIG_DEV_CONSOLE) && !defined(CONFIG_SIM_UART_DATAPOST)
/* Handle UART data availability */
if (g_uart_data_available)
{
g_uart_data_available = 0;
simuart_post();
}
#endif
#ifdef CONFIG_NET_ETHERNET
/* Run the network if enabled */
netdriver_loop();
#endif
#ifdef CONFIG_PM
/* Fake some power management stuff for testing purposes */
{
static enum pm_state_e state = PM_NORMAL;
enum pm_state_e newstate;
newstate = pm_checkstate();
if (newstate != state)
{
if (pm_changestate(newstate) == OK)
{
state = newstate;
}
}
}
#endif
#if defined(CONFIG_SIM_WALLTIME) || defined(CONFIG_SIM_X11FB)
/* Wait a bit so that the sched_process_timer() is called close to the
* correct rate.
*/
(void)up_hostusleep(1000000 / CLK_TCK);
/* Handle X11-related events */
#ifdef CONFIG_SIM_X11FB
if (g_x11initialized)
{
#if defined(CONFIG_SIM_TOUCHSCREEN) || defined(CONFIG_SIM_AJOYSTICK)
/* Drive the X11 event loop */
if (g_eventloop)
{
up_x11events();
}
#endif
/* Update the display periodically */
g_x11refresh += 1000000 / CLK_TCK;
if (g_x11refresh > 500000)
{
up_x11update();
}
}
#endif
#endif
#ifdef CONFIG_SMP
/* Release the spinlock */
lock = SP_UNLOCKED;
/* Give other pthreads/CPUs a shot */
pthread_yield();
#endif
}